amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

42 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
43 			uint32_t queue, uint32_t vmid)
55 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
56 				uint32_t queue_id)
58 	uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
59 	uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
65 			       uint32_t pipe_id, uint32_t queue_id)
78 static void program_sh_mem_settings_v11(struct amdgpu_device *adev, uint32_t vmid,
79 					uint32_t sh_mem_config,
80 					uint32_t sh_mem_ape1_base,
81 					uint32_t sh_mem_ape1_limit,
82 					uint32_t sh_mem_bases, uint32_t inst)
93 					unsigned int vmid, uint32_t inst)
95 	uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
105 static int init_interrupts_v11(struct amdgpu_device *adev, uint32_t pipe_id,
106 				uint32_t inst)
108 	uint32_t mec;
109 	uint32_t pipe;
125 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
129 	uint32_t sdma_engine_reg_base = 0;
130 	uint32_t sdma_rlc_reg_offset;
164 static int hqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
165 			uint32_t queue_id, uint32_t __user *wptr,
166 			uint32_t wptr_shift, uint32_t wptr_mask,
167 			struct mm_struct *mm, uint32_t inst)
170 	uint32_t *mqd_hqd;
171 	uint32_t reg, hqd_base, data;
180 		uint32_t value, mec, pipe;
224 		uint32_t queue_size =
243 			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
245 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
262 			      uint32_t pipe_id, uint32_t queue_id,
263 			      uint32_t doorbell_off, uint32_t inst)
267 	uint32_t mec, pipe;
314 			uint32_t pipe_id, uint32_t queue_id,
315 			uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
317 	uint32_t i = 0, reg;
326 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
345 			     uint32_t __user *wptr, struct mm_struct *mm)
348 	uint32_t sdma_rlc_reg_offset;
350 	uint32_t data;
414 			     uint32_t engine_id, uint32_t queue_id,
415 			     uint32_t (**dump)[2], uint32_t *n_regs)
417 	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
419 	uint32_t i = 0, reg;
423 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
450 				uint32_t pipe_id, uint32_t queue_id, uint32_t inst)
452 	uint32_t act;
454 	uint32_t low, high;
473 	uint32_t sdma_rlc_reg_offset;
474 	uint32_t sdma_rlc_rb_cntl;
490 				unsigned int utimeout, uint32_t pipe_id,
491 				uint32_t queue_id, uint32_t inst)
495 	uint32_t temp;
539 	uint32_t sdma_rlc_reg_offset;
540 	uint32_t temp;
575 					uint32_t gfx_index_val,
576 					uint32_t sq_cmd, uint32_t inst)
578 	uint32_t data = 0;
599 		uint32_t vmid, uint64_t page_table_base)
620 static uint32_t kgd_gfx_v11_enable_debug_trap(struct amdgpu_device *adev,
622 					    uint32_t vmid)
624 	uint32_t data = 0;
634 static uint32_t kgd_gfx_v11_disable_debug_trap(struct amdgpu_device *adev,
636 						uint32_t vmid)
638 	uint32_t data = 0;
648 							uint32_t trap_override,
649 							uint32_t *trap_mask_supported)
672 static uint32_t trap_mask_map_sw_to_hw(uint32_t mask)
674 	uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0;
675 	uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0;
676 	uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID |
685 	uint32_t ret;
694 static uint32_t trap_mask_map_hw_to_sw(uint32_t mask)
696 	uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
708 static uint32_t kgd_gfx_v11_set_wave_launch_trap_override(struct amdgpu_device *adev,
709 					uint32_t vmid,
710 					uint32_t trap_override,
711 					uint32_t trap_mask_bits,
712 					uint32_t trap_mask_request,
713 					uint32_t *trap_mask_prev,
714 					uint32_t kfd_dbg_trap_cntl_prev)
716 	uint32_t data = 0;
729 static uint32_t kgd_gfx_v11_set_wave_launch_mode(struct amdgpu_device *adev,
731 					uint32_t vmid)
733 	uint32_t data = 0;
741 static uint32_t kgd_gfx_v11_set_address_watch(struct amdgpu_device *adev,
743 					uint32_t watch_address_mask,
744 					uint32_t watch_id,
745 					uint32_t watch_mode,
746 					uint32_t debug_vmid,
747 					uint32_t inst)
749 	uint32_t watch_address_high;
750 	uint32_t watch_address_low;
751 	uint32_t watch_address_cntl;
783 static uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev,
784 						uint32_t watch_id)