amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

44 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
45 			uint32_t queue, uint32_t vmid)
57 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
58 				uint32_t queue_id)
60 	uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 	uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
67 			       uint32_t pipe_id, uint32_t queue_id)
80 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
81 					uint32_t sh_mem_config,
82 					uint32_t sh_mem_ape1_base,
83 					uint32_t sh_mem_ape1_limit,
84 					uint32_t sh_mem_bases, uint32_t inst)
96 					unsigned int vmid, uint32_t inst)
105 	uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
140 static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
141 				uint32_t inst)
143 	uint32_t mec;
144 	uint32_t pipe;
160 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
164 	uint32_t sdma_engine_reg_base[2] = {
177 	uint32_t retval = sdma_engine_reg_base[engine_id]
187 static uint32_t get_watch_base_addr(struct amdgpu_device *adev)
189 	uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
209 			uint32_t pipe_id, uint32_t queue_id,
210 			uint32_t __user *wptr, uint32_t wptr_shift,
211 			uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
214 	uint32_t *mqd_hqd;
215 	uint32_t reg, hqd_base, data;
253 		uint32_t queue_size =
272 			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
274 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
291 			    uint32_t pipe_id, uint32_t queue_id,
292 			    uint32_t doorbell_off, uint32_t inst)
296 	uint32_t mec, pipe;
343 			uint32_t pipe_id, uint32_t queue_id,
344 			uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
346 	uint32_t i = 0, reg;
355 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
374 			     uint32_t __user *wptr, struct mm_struct *mm)
377 	uint32_t sdma_rlc_reg_offset;
379 	uint32_t data;
443 			     uint32_t engine_id, uint32_t queue_id,
444 			     uint32_t (**dump)[2], uint32_t *n_regs)
446 	uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
448 	uint32_t i = 0, reg;
452 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
474 				uint64_t queue_address, uint32_t pipe_id,
475 				uint32_t queue_id, uint32_t inst)
477 	uint32_t act;
479 	uint32_t low, high;
498 	uint32_t sdma_rlc_reg_offset;
499 	uint32_t sdma_rlc_rb_cntl;
515 				unsigned int utimeout, uint32_t pipe_id,
516 				uint32_t queue_id, uint32_t inst)
520 	uint32_t temp;
630 	uint32_t sdma_rlc_reg_offset;
631 	uint32_t temp;
668 	uint32_t value;
678 					uint32_t gfx_index_val,
679 					uint32_t sq_cmd, uint32_t inst)
681 	uint32_t data = 0;
702 		uint32_t vmid, uint64_t page_table_base)
736 static void kgd_gfx_v10_set_wave_launch_stall(struct amdgpu_device *adev, uint32_t vmid, bool stall)
738 	uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
753 uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev,
755 				uint32_t vmid)
764 		uint32_t data = 0;
790 uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev,
792 					uint32_t vmid)
808 					      uint32_t trap_override,
809 					      uint32_t *trap_mask_supported)
825 uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev,
826 					      uint32_t vmid,
827 					      uint32_t trap_override,
828 					      uint32_t trap_mask_bits,
829 					      uint32_t trap_mask_request,
830 					      uint32_t *trap_mask_prev,
831 					      uint32_t kfd_dbg_trap_cntl_prev)
833 	uint32_t data, wave_cntl_prev;
859 uint32_t kgd_gfx_v10_set_wave_launch_mode(struct amdgpu_device *adev,
861 					uint32_t vmid)
863 	uint32_t data = 0;
885 uint32_t kgd_gfx_v10_set_address_watch(struct amdgpu_device *adev,
887 					uint32_t watch_address_mask,
888 					uint32_t watch_id,
889 					uint32_t watch_mode,
890 					uint32_t debug_vmid,
891 					uint32_t inst)
896 	uint32_t watch_address_high;
897 	uint32_t watch_address_low;
898 	uint32_t tcp_watch_address_cntl;
899 	uint32_t sq_watch_address_cntl;
984 uint32_t kgd_gfx_v10_clear_address_watch(struct amdgpu_device *adev,
985 					uint32_t watch_id)
987 	uint32_t watch_address_cntl;
1017 					uint32_t *wait_times,
1018 					uint32_t inst)
1025 						uint32_t wait_times,
1026 						uint32_t grace_period,
1027 						uint32_t *reg_offset,
1028 						uint32_t *reg_data)
1048 		uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
1049 		uint32_t inst)