Lines Matching refs:uint32_t
87 uint32_t DP_STREAM_MAPPER_CONTROL0;\
88 uint32_t DP_STREAM_MAPPER_CONTROL1;\
89 uint32_t DP_STREAM_MAPPER_CONTROL2;\
90 uint32_t DP_STREAM_MAPPER_CONTROL3;\
91 uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\
92 uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\
93 uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\
94 uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\
95 uint32_t DP_SYM32_ENC_CONTROL;\
96 uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\
97 uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\
98 uint32_t DP_SYM32_ENC_VID_MSA0;\
99 uint32_t DP_SYM32_ENC_VID_MSA1;\
100 uint32_t DP_SYM32_ENC_VID_MSA2;\
101 uint32_t DP_SYM32_ENC_VID_MSA3;\
102 uint32_t DP_SYM32_ENC_VID_MSA4;\
103 uint32_t DP_SYM32_ENC_VID_MSA5;\
104 uint32_t DP_SYM32_ENC_VID_MSA6;\
105 uint32_t DP_SYM32_ENC_VID_MSA7;\
106 uint32_t DP_SYM32_ENC_VID_MSA8;\
107 uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\
108 uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\
109 uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\
110 uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\
111 uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\
112 uint32_t DP_SYM32_ENC_SDP_CONTROL;\
113 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\
114 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\
115 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\
116 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\
117 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\
118 uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\
119 uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\
120 uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\
121 uint32_t DP_SYM32_ENC_HBLANK_CONTROL
221 DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
236 uint32_t inst,