1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30#ifndef AMDGPU_MODE_H 31#define AMDGPU_MODE_H 32 33#include <drm/display/drm_dp_helper.h> 34#include <drm/drm_crtc.h> 35#include <drm/drm_encoder.h> 36#include <drm/drm_fixed.h> 37#include <drm/drm_framebuffer.h> 38#include <drm/drm_probe_helper.h> 39#include <linux/i2c.h> 40#include <linux/i2c-algo-bit.h> 41#include <linux/hrtimer.h> 42#include "amdgpu_irq.h" 43 44#include <drm/display/drm_dp_mst_helper.h> 45#include "modules/inc/mod_freesync.h" 46#include "amdgpu_dm_irq_params.h" 47 48struct amdgpu_bo; 49struct amdgpu_device; 50struct amdgpu_encoder; 51struct amdgpu_router; 52struct amdgpu_hpd; 53struct edid; 54 55#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 56#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 57#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 58#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 59 60#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base) 61 62#define AMDGPU_MAX_HPD_PINS 6 63#define AMDGPU_MAX_CRTCS 6 64#define AMDGPU_MAX_PLANES 6 65#define AMDGPU_MAX_AFMT_BLOCKS 9 66 67enum amdgpu_rmx_type { 68 RMX_OFF, 69 RMX_FULL, 70 RMX_CENTER, 71 RMX_ASPECT 72}; 73 74enum amdgpu_underscan_type { 75 UNDERSCAN_OFF, 76 UNDERSCAN_ON, 77 UNDERSCAN_AUTO, 78}; 79 80#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 81#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 82 83enum amdgpu_hpd_id { 84 AMDGPU_HPD_1 = 0, 85 AMDGPU_HPD_2, 86 AMDGPU_HPD_3, 87 AMDGPU_HPD_4, 88 AMDGPU_HPD_5, 89 AMDGPU_HPD_6, 90 AMDGPU_HPD_NONE = 0xff, 91}; 92 93enum amdgpu_crtc_irq { 94 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 95 AMDGPU_CRTC_IRQ_VBLANK2, 96 AMDGPU_CRTC_IRQ_VBLANK3, 97 AMDGPU_CRTC_IRQ_VBLANK4, 98 AMDGPU_CRTC_IRQ_VBLANK5, 99 AMDGPU_CRTC_IRQ_VBLANK6, 100 AMDGPU_CRTC_IRQ_VLINE1, 101 AMDGPU_CRTC_IRQ_VLINE2, 102 AMDGPU_CRTC_IRQ_VLINE3, 103 AMDGPU_CRTC_IRQ_VLINE4, 104 AMDGPU_CRTC_IRQ_VLINE5, 105 AMDGPU_CRTC_IRQ_VLINE6, 106 AMDGPU_CRTC_IRQ_NONE = 0xff 107}; 108 109enum amdgpu_pageflip_irq { 110 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 111 AMDGPU_PAGEFLIP_IRQ_D2, 112 AMDGPU_PAGEFLIP_IRQ_D3, 113 AMDGPU_PAGEFLIP_IRQ_D4, 114 AMDGPU_PAGEFLIP_IRQ_D5, 115 AMDGPU_PAGEFLIP_IRQ_D6, 116 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 117}; 118 119enum amdgpu_flip_status { 120 AMDGPU_FLIP_NONE, 121 AMDGPU_FLIP_PENDING, 122 AMDGPU_FLIP_SUBMITTED 123}; 124 125#define AMDGPU_MAX_I2C_BUS 16 126 127/* amdgpu gpio-based i2c 128 * 1. "mask" reg and bits 129 * grabs the gpio pins for software use 130 * 0=not held 1=held 131 * 2. "a" reg and bits 132 * output pin value 133 * 0=low 1=high 134 * 3. "en" reg and bits 135 * sets the pin direction 136 * 0=input 1=output 137 * 4. "y" reg and bits 138 * input pin value 139 * 0=low 1=high 140 */ 141struct amdgpu_i2c_bus_rec { 142 bool valid; 143 /* id used by atom */ 144 uint8_t i2c_id; 145 /* id used by atom */ 146 enum amdgpu_hpd_id hpd; 147 /* can be used with hw i2c engine */ 148 bool hw_capable; 149 /* uses multi-media i2c engine */ 150 bool mm_i2c; 151 /* regs and bits */ 152 uint32_t mask_clk_reg; 153 uint32_t mask_data_reg; 154 uint32_t a_clk_reg; 155 uint32_t a_data_reg; 156 uint32_t en_clk_reg; 157 uint32_t en_data_reg; 158 uint32_t y_clk_reg; 159 uint32_t y_data_reg; 160 uint32_t mask_clk_mask; 161 uint32_t mask_data_mask; 162 uint32_t a_clk_mask; 163 uint32_t a_data_mask; 164 uint32_t en_clk_mask; 165 uint32_t en_data_mask; 166 uint32_t y_clk_mask; 167 uint32_t y_data_mask; 168}; 169 170#define AMDGPU_MAX_BIOS_CONNECTOR 16 171 172/* pll flags */ 173#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 174#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 175#define AMDGPU_PLL_USE_REF_DIV (1 << 2) 176#define AMDGPU_PLL_LEGACY (1 << 3) 177#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 178#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 179#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 180#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 181#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 182#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 183#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 184#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 185#define AMDGPU_PLL_USE_POST_DIV (1 << 12) 186#define AMDGPU_PLL_IS_LCD (1 << 13) 187#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 188 189struct amdgpu_pll { 190 /* reference frequency */ 191 uint32_t reference_freq; 192 193 /* fixed dividers */ 194 uint32_t reference_div; 195 uint32_t post_div; 196 197 /* pll in/out limits */ 198 uint32_t pll_in_min; 199 uint32_t pll_in_max; 200 uint32_t pll_out_min; 201 uint32_t pll_out_max; 202 uint32_t lcd_pll_out_min; 203 uint32_t lcd_pll_out_max; 204 uint32_t best_vco; 205 206 /* divider limits */ 207 uint32_t min_ref_div; 208 uint32_t max_ref_div; 209 uint32_t min_post_div; 210 uint32_t max_post_div; 211 uint32_t min_feedback_div; 212 uint32_t max_feedback_div; 213 uint32_t min_frac_feedback_div; 214 uint32_t max_frac_feedback_div; 215 216 /* flags for the current clock */ 217 uint32_t flags; 218 219 /* pll id */ 220 uint32_t id; 221}; 222 223struct amdgpu_i2c_chan { 224 struct i2c_adapter adapter; 225 struct drm_device *dev; 226 struct i2c_algo_bit_data bit; 227 struct amdgpu_i2c_bus_rec rec; 228 struct drm_dp_aux aux; 229 bool has_aux; 230 struct mutex mutex; 231}; 232 233struct amdgpu_afmt { 234 bool enabled; 235 int offset; 236 bool last_buffer_filled_status; 237 int id; 238 struct amdgpu_audio_pin *pin; 239}; 240 241/* 242 * Audio 243 */ 244struct amdgpu_audio_pin { 245 int channels; 246 int rate; 247 int bits_per_sample; 248 u8 status_bits; 249 u8 category_code; 250 u32 offset; 251 bool connected; 252 u32 id; 253}; 254 255struct amdgpu_audio { 256 bool enabled; 257 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 258 int num_pins; 259}; 260 261struct amdgpu_display_funcs { 262 /* display watermarks */ 263 void (*bandwidth_update)(struct amdgpu_device *adev); 264 /* get frame count */ 265 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 266 /* set backlight level */ 267 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 268 u8 level); 269 /* get backlight level */ 270 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 271 /* hotplug detect */ 272 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 273 void (*hpd_set_polarity)(struct amdgpu_device *adev, 274 enum amdgpu_hpd_id hpd); 275 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 276 /* pageflipping */ 277 void (*page_flip)(struct amdgpu_device *adev, 278 int crtc_id, u64 crtc_base, bool async); 279 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 280 u32 *vbl, u32 *position); 281 /* display topology setup */ 282 void (*add_encoder)(struct amdgpu_device *adev, 283 uint32_t encoder_enum, 284 uint32_t supported_device, 285 u16 caps); 286 void (*add_connector)(struct amdgpu_device *adev, 287 uint32_t connector_id, 288 uint32_t supported_device, 289 int connector_type, 290 struct amdgpu_i2c_bus_rec *i2c_bus, 291 uint16_t connector_object_id, 292 struct amdgpu_hpd *hpd, 293 struct amdgpu_router *router); 294 295 296}; 297 298struct amdgpu_framebuffer { 299 struct drm_framebuffer base; 300 301 uint64_t tiling_flags; 302 bool tmz_surface; 303 304 /* caching for later use */ 305 uint64_t address; 306}; 307 308struct amdgpu_mode_info { 309 struct atom_context *atom_context; 310 struct card_info *atom_card_info; 311 bool mode_config_initialized; 312 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 313 struct drm_plane *planes[AMDGPU_MAX_PLANES]; 314 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 315 /* DVI-I properties */ 316 struct drm_property *coherent_mode_property; 317 /* DAC enable load detect */ 318 struct drm_property *load_detect_property; 319 /* underscan */ 320 struct drm_property *underscan_property; 321 struct drm_property *underscan_hborder_property; 322 struct drm_property *underscan_vborder_property; 323 /* audio */ 324 struct drm_property *audio_property; 325 /* FMT dithering */ 326 struct drm_property *dither_property; 327 /* hardcoded DFP edid from BIOS */ 328 struct edid *bios_hardcoded_edid; 329 int bios_hardcoded_edid_size; 330 331 /* firmware flags */ 332 u32 firmware_flags; 333 /* pointer to backlight encoder */ 334 struct amdgpu_encoder *bl_encoder; 335 u8 bl_level; /* saved backlight level */ 336 struct amdgpu_audio audio; /* audio stuff */ 337 int num_crtc; /* number of crtcs */ 338 int num_hpd; /* number of hpd pins */ 339 int num_dig; /* number of dig blocks */ 340 bool gpu_vm_support; /* supports display from GTT */ 341 int disp_priority; 342 const struct amdgpu_display_funcs *funcs; 343 const enum drm_plane_type *plane_type; 344 345 /* Driver-private color mgmt props */ 346 347 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to 348 * convert encoded values to light linear values before sampling or 349 * blending. 350 */ 351 struct drm_property *plane_degamma_lut_property; 352 /* @plane_degamma_lut_size_property: Plane property to define the max 353 * size of degamma LUT as supported by the driver (read-only). 354 */ 355 struct drm_property *plane_degamma_lut_size_property; 356 /** 357 * @plane_degamma_tf_property: Plane pre-defined transfer function to 358 * to go from scanout/encoded values to linear values. 359 */ 360 struct drm_property *plane_degamma_tf_property; 361 /** 362 * @plane_hdr_mult_property: 363 */ 364 struct drm_property *plane_hdr_mult_property; 365 366 struct drm_property *plane_ctm_property; 367 /** 368 * @shaper_lut_property: Plane property to set pre-blending shaper LUT 369 * that converts color content before 3D LUT. If 370 * plane_shaper_tf_property != Identity TF, AMD color module will 371 * combine the user LUT values with pre-defined TF into the LUT 372 * parameters to be programmed. 373 */ 374 struct drm_property *plane_shaper_lut_property; 375 /** 376 * @shaper_lut_size_property: Plane property for the size of 377 * pre-blending shaper LUT as supported by the driver (read-only). 378 */ 379 struct drm_property *plane_shaper_lut_size_property; 380 /** 381 * @plane_shaper_tf_property: Plane property to set a predefined 382 * transfer function for pre-blending shaper (before applying 3D LUT) 383 * with or without LUT. There is no shaper ROM, but we can use AMD 384 * color modules to program LUT parameters from predefined TF (or 385 * from a combination of pre-defined TF and the custom 1D LUT). 386 */ 387 struct drm_property *plane_shaper_tf_property; 388 /** 389 * @plane_lut3d_property: Plane property for color transformation using 390 * a 3D LUT (pre-blending), a three-dimensional array where each 391 * element is an RGB triplet. Each dimension has the size of 392 * lut3d_size. The array contains samples from the approximated 393 * function. On AMD, values between samples are estimated by 394 * tetrahedral interpolation. The array is accessed with three indices, 395 * one for each input dimension (color channel), blue being the 396 * outermost dimension, red the innermost. 397 */ 398 struct drm_property *plane_lut3d_property; 399 /** 400 * @plane_degamma_lut_size_property: Plane property to define the max 401 * size of 3D LUT as supported by the driver (read-only). The max size 402 * is the max size of one dimension and, therefore, the max number of 403 * entries for 3D LUT array is the 3D LUT size cubed; 404 */ 405 struct drm_property *plane_lut3d_size_property; 406 /** 407 * @plane_blend_lut_property: Plane property for output gamma before 408 * blending. Userspace set a blend LUT to convert colors after 3D LUT 409 * conversion. It works as a post-3DLUT 1D LUT. With shaper LUT, they 410 * are sandwiching 3D LUT with two 1D LUT. If plane_blend_tf_property 411 * != Identity TF, AMD color module will combine the user LUT values 412 * with pre-defined TF into the LUT parameters to be programmed. 413 */ 414 struct drm_property *plane_blend_lut_property; 415 /** 416 * @plane_blend_lut_size_property: Plane property to define the max 417 * size of blend LUT as supported by the driver (read-only). 418 */ 419 struct drm_property *plane_blend_lut_size_property; 420 /** 421 * @plane_blend_tf_property: Plane property to set a predefined 422 * transfer function for pre-blending blend/out_gamma (after applying 423 * 3D LUT) with or without LUT. There is no blend ROM, but we can use 424 * AMD color modules to program LUT parameters from predefined TF (or 425 * from a combination of pre-defined TF and the custom 1D LUT). 426 */ 427 struct drm_property *plane_blend_tf_property; 428 /* @regamma_tf_property: Transfer function for CRTC regamma 429 * (post-blending). Possible values are defined by `enum 430 * amdgpu_transfer_function`. There is no regamma ROM, but we can use 431 * AMD color modules to program LUT parameters from predefined TF (or 432 * from a combination of pre-defined TF and the custom 1D LUT). 433 */ 434 struct drm_property *regamma_tf_property; 435}; 436 437#define AMDGPU_MAX_BL_LEVEL 0xFF 438 439struct amdgpu_backlight_privdata { 440 struct amdgpu_encoder *encoder; 441 uint8_t negative; 442}; 443 444struct amdgpu_atom_ss { 445 uint16_t percentage; 446 uint16_t percentage_divider; 447 uint8_t type; 448 uint16_t step; 449 uint8_t delay; 450 uint8_t range; 451 uint8_t refdiv; 452 /* asic_ss */ 453 uint16_t rate; 454 uint16_t amount; 455}; 456 457struct amdgpu_crtc { 458 struct drm_crtc base; 459 int crtc_id; 460 bool enabled; 461 bool can_tile; 462 uint32_t crtc_offset; 463 struct drm_gem_object *cursor_bo; 464 uint64_t cursor_addr; 465 int cursor_x; 466 int cursor_y; 467 int cursor_hot_x; 468 int cursor_hot_y; 469 int cursor_width; 470 int cursor_height; 471 int max_cursor_width; 472 int max_cursor_height; 473 enum amdgpu_rmx_type rmx_type; 474 u8 h_border; 475 u8 v_border; 476 fixed20_12 vsc; 477 fixed20_12 hsc; 478 struct drm_display_mode native_mode; 479 u32 pll_id; 480 /* page flipping */ 481 struct amdgpu_flip_work *pflip_works; 482 enum amdgpu_flip_status pflip_status; 483 int deferred_flip_completion; 484 /* parameters access from DM IRQ handler */ 485 struct dm_irq_params dm_irq_params; 486 /* pll sharing */ 487 struct amdgpu_atom_ss ss; 488 bool ss_enabled; 489 u32 adjusted_clock; 490 int bpc; 491 u32 pll_reference_div; 492 u32 pll_post_div; 493 u32 pll_flags; 494 struct drm_encoder *encoder; 495 struct drm_connector *connector; 496 /* for dpm */ 497 u32 line_time; 498 u32 wm_low; 499 u32 wm_high; 500 u32 lb_vblank_lead_lines; 501 struct drm_display_mode hw_mode; 502 /* for virtual dce */ 503 struct hrtimer vblank_timer; 504 enum amdgpu_interrupt_state vsync_timer_enabled; 505 506 int otg_inst; 507 struct drm_pending_vblank_event *event; 508 509 bool wb_pending; 510 bool wb_enabled; 511 struct drm_writeback_connector *wb_conn; 512}; 513 514struct amdgpu_encoder_atom_dig { 515 bool linkb; 516 /* atom dig */ 517 bool coherent_mode; 518 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 519 /* atom lvds/edp */ 520 uint32_t lcd_misc; 521 uint16_t panel_pwr_delay; 522 uint32_t lcd_ss_id; 523 /* panel mode */ 524 struct drm_display_mode native_mode; 525 struct backlight_device *bl_dev; 526 int dpms_mode; 527 uint8_t backlight_level; 528 int panel_mode; 529 struct amdgpu_afmt *afmt; 530}; 531 532struct amdgpu_encoder { 533 struct drm_encoder base; 534 uint32_t encoder_enum; 535 uint32_t encoder_id; 536 uint32_t devices; 537 uint32_t active_device; 538 uint32_t flags; 539 uint32_t pixel_clock; 540 enum amdgpu_rmx_type rmx_type; 541 enum amdgpu_underscan_type underscan_type; 542 uint32_t underscan_hborder; 543 uint32_t underscan_vborder; 544 struct drm_display_mode native_mode; 545 void *enc_priv; 546 int audio_polling_active; 547 bool is_ext_encoder; 548 u16 caps; 549}; 550 551struct amdgpu_connector_atom_dig { 552 /* displayport */ 553 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 554 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 555 u8 dp_sink_type; 556 int dp_clock; 557 int dp_lane_count; 558 bool edp_on; 559}; 560 561struct amdgpu_gpio_rec { 562 bool valid; 563 u8 id; 564 u32 reg; 565 u32 mask; 566 u32 shift; 567}; 568 569struct amdgpu_hpd { 570 enum amdgpu_hpd_id hpd; 571 u8 plugged_state; 572 struct amdgpu_gpio_rec gpio; 573}; 574 575struct amdgpu_router { 576 u32 router_id; 577 struct amdgpu_i2c_bus_rec i2c_info; 578 u8 i2c_addr; 579 /* i2c mux */ 580 bool ddc_valid; 581 u8 ddc_mux_type; 582 u8 ddc_mux_control_pin; 583 u8 ddc_mux_state; 584 /* clock/data mux */ 585 bool cd_valid; 586 u8 cd_mux_type; 587 u8 cd_mux_control_pin; 588 u8 cd_mux_state; 589}; 590 591enum amdgpu_connector_audio { 592 AMDGPU_AUDIO_DISABLE = 0, 593 AMDGPU_AUDIO_ENABLE = 1, 594 AMDGPU_AUDIO_AUTO = 2 595}; 596 597enum amdgpu_connector_dither { 598 AMDGPU_FMT_DITHER_DISABLE = 0, 599 AMDGPU_FMT_DITHER_ENABLE = 1, 600}; 601 602struct amdgpu_dm_dp_aux { 603 struct drm_dp_aux aux; 604 struct ddc_service *ddc_service; 605}; 606 607struct amdgpu_i2c_adapter { 608 struct i2c_adapter base; 609 610 struct ddc_service *ddc_service; 611}; 612 613#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux) 614 615struct amdgpu_connector { 616 struct drm_connector base; 617 uint32_t connector_id; 618 uint32_t devices; 619 struct amdgpu_i2c_chan *ddc_bus; 620 /* some systems have an hdmi and vga port with a shared ddc line */ 621 bool shared_ddc; 622 bool use_digital; 623 /* we need to mind the EDID between detect 624 and get modes due to analog/digital/tvencoder */ 625 struct edid *edid; 626 void *con_priv; 627 bool dac_load_detect; 628 bool detected_by_load; /* if the connection status was determined by load */ 629 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 630 uint16_t connector_object_id; 631 struct amdgpu_hpd hpd; 632 struct amdgpu_router router; 633 struct amdgpu_i2c_chan *router_bus; 634 enum amdgpu_connector_audio audio; 635 enum amdgpu_connector_dither dither; 636 unsigned pixelclock_for_modeset; 637}; 638 639/* TODO: start to use this struct and remove same field from base one */ 640struct amdgpu_mst_connector { 641 struct amdgpu_connector base; 642 643 struct drm_dp_mst_topology_mgr mst_mgr; 644 struct amdgpu_dm_dp_aux dm_dp_aux; 645 struct drm_dp_mst_port *mst_output_port; 646 struct amdgpu_connector *mst_root; 647 bool is_mst_connector; 648 struct amdgpu_encoder *mst_encoder; 649}; 650 651#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 652 ((em) == ATOM_ENCODER_MODE_DP_MST)) 653 654/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */ 655#define DRM_SCANOUTPOS_VALID (1 << 0) 656#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 657#define DRM_SCANOUTPOS_ACCURATE (1 << 2) 658#define USE_REAL_VBLANKSTART (1 << 30) 659#define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 660 661void amdgpu_link_encoder_connector(struct drm_device *dev); 662 663struct drm_connector * 664amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 665struct drm_connector * 666amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 667bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 668 u32 pixel_clock); 669 670u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 671struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 672 673bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 674 bool use_aux); 675 676void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 677 678int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 679 unsigned int pipe, unsigned int flags, int *vpos, 680 int *hpos, ktime_t *stime, ktime_t *etime, 681 const struct drm_display_mode *mode); 682 683int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 684 685void amdgpu_enc_destroy(struct drm_encoder *encoder); 686void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 687bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 688 const struct drm_display_mode *mode, 689 struct drm_display_mode *adjusted_mode); 690void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 691 struct drm_display_mode *adjusted_mode); 692int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 693 694bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 695 bool in_vblank_irq, int *vpos, 696 int *hpos, ktime_t *stime, ktime_t *etime, 697 const struct drm_display_mode *mode); 698 699/* amdgpu_display.c */ 700void amdgpu_display_print_display_setup(struct drm_device *dev); 701int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); 702int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 703 struct drm_modeset_acquire_ctx *ctx); 704int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 705 struct drm_framebuffer *fb, 706 struct drm_pending_vblank_event *event, 707 uint32_t page_flip_flags, uint32_t target, 708 struct drm_modeset_acquire_ctx *ctx); 709extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 710 711#endif 712