1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef SMU13_DRIVER_IF_V13_0_0_H 25#define SMU13_DRIVER_IF_V13_0_0_H 26 27#define SMU13_0_0_DRIVER_IF_VERSION 0x3D 28 29//Increment this version if SkuTable_t or BoardTable_t change 30#define PPTABLE_VERSION 0x2B 31 32#define NUM_GFXCLK_DPM_LEVELS 16 33#define NUM_SOCCLK_DPM_LEVELS 8 34#define NUM_MP0CLK_DPM_LEVELS 2 35#define NUM_DCLK_DPM_LEVELS 8 36#define NUM_VCLK_DPM_LEVELS 8 37#define NUM_DISPCLK_DPM_LEVELS 8 38#define NUM_DPPCLK_DPM_LEVELS 8 39#define NUM_DPREFCLK_DPM_LEVELS 8 40#define NUM_DCFCLK_DPM_LEVELS 8 41#define NUM_DTBCLK_DPM_LEVELS 8 42#define NUM_UCLK_DPM_LEVELS 4 43#define NUM_LINK_LEVELS 3 44#define NUM_FCLK_DPM_LEVELS 8 45#define NUM_OD_FAN_MAX_POINTS 6 46 47// Feature Control Defines 48#define FEATURE_FW_DATA_READ_BIT 0 49#define FEATURE_DPM_GFXCLK_BIT 1 50#define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 51#define FEATURE_DPM_UCLK_BIT 3 52#define FEATURE_DPM_FCLK_BIT 4 53#define FEATURE_DPM_SOCCLK_BIT 5 54#define FEATURE_DPM_MP0CLK_BIT 6 55#define FEATURE_DPM_LINK_BIT 7 56#define FEATURE_DPM_DCN_BIT 8 57#define FEATURE_VMEMP_SCALING_BIT 9 58#define FEATURE_VDDIO_MEM_SCALING_BIT 10 59#define FEATURE_DS_GFXCLK_BIT 11 60#define FEATURE_DS_SOCCLK_BIT 12 61#define FEATURE_DS_FCLK_BIT 13 62#define FEATURE_DS_LCLK_BIT 14 63#define FEATURE_DS_DCFCLK_BIT 15 64#define FEATURE_DS_UCLK_BIT 16 65#define FEATURE_GFX_ULV_BIT 17 66#define FEATURE_FW_DSTATE_BIT 18 67#define FEATURE_GFXOFF_BIT 19 68#define FEATURE_BACO_BIT 20 69#define FEATURE_MM_DPM_BIT 21 70#define FEATURE_SOC_MPCLK_DS_BIT 22 71#define FEATURE_BACO_MPCLK_DS_BIT 23 72#define FEATURE_THROTTLERS_BIT 24 73#define FEATURE_SMARTSHIFT_BIT 25 74#define FEATURE_GTHR_BIT 26 75#define FEATURE_ACDC_BIT 27 76#define FEATURE_VR0HOT_BIT 28 77#define FEATURE_FW_CTF_BIT 29 78#define FEATURE_FAN_CONTROL_BIT 30 79#define FEATURE_GFX_DCS_BIT 31 80#define FEATURE_GFX_READ_MARGIN_BIT 32 81#define FEATURE_LED_DISPLAY_BIT 33 82#define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 34 83#define FEATURE_OUT_OF_BAND_MONITOR_BIT 35 84#define FEATURE_OPTIMIZED_VMIN_BIT 36 85#define FEATURE_GFX_IMU_BIT 37 86#define FEATURE_BOOT_TIME_CAL_BIT 38 87#define FEATURE_GFX_PCC_DFLL_BIT 39 88#define FEATURE_SOC_CG_BIT 40 89#define FEATURE_DF_CSTATE_BIT 41 90#define FEATURE_GFX_EDC_BIT 42 91#define FEATURE_BOOT_POWER_OPT_BIT 43 92#define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 44 93#define FEATURE_DS_VCN_BIT 45 94#define FEATURE_BACO_CG_BIT 46 95#define FEATURE_MEM_TEMP_READ_BIT 47 96#define FEATURE_ATHUB_MMHUB_PG_BIT 48 97#define FEATURE_SOC_PCC_BIT 49 98#define FEATURE_EDC_PWRBRK_BIT 50 99#define FEATURE_BOMXCO_SVI3_PROG_BIT 51 100#define FEATURE_SPARE_52_BIT 52 101#define FEATURE_SPARE_53_BIT 53 102#define FEATURE_SPARE_54_BIT 54 103#define FEATURE_SPARE_55_BIT 55 104#define FEATURE_SPARE_56_BIT 56 105#define FEATURE_SPARE_57_BIT 57 106#define FEATURE_SPARE_58_BIT 58 107#define FEATURE_SPARE_59_BIT 59 108#define FEATURE_SPARE_60_BIT 60 109#define FEATURE_SPARE_61_BIT 61 110#define FEATURE_SPARE_62_BIT 62 111#define FEATURE_SPARE_63_BIT 63 112#define NUM_FEATURES 64 113 114#define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 115#define ALLOWED_FEATURE_CTRL_SCPM ((1 << FEATURE_DPM_GFXCLK_BIT) | \ 116 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 117 (1 << FEATURE_DPM_UCLK_BIT) | \ 118 (1 << FEATURE_DPM_FCLK_BIT) | \ 119 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 120 (1 << FEATURE_DPM_MP0CLK_BIT) | \ 121 (1 << FEATURE_DPM_LINK_BIT) | \ 122 (1 << FEATURE_DPM_DCN_BIT) | \ 123 (1 << FEATURE_DS_GFXCLK_BIT) | \ 124 (1 << FEATURE_DS_SOCCLK_BIT) | \ 125 (1 << FEATURE_DS_FCLK_BIT) | \ 126 (1 << FEATURE_DS_LCLK_BIT) | \ 127 (1 << FEATURE_DS_DCFCLK_BIT) | \ 128 (1 << FEATURE_DS_UCLK_BIT) | \ 129 (1ULL << FEATURE_DS_VCN_BIT)) 130 131//For use with feature control messages 132typedef enum { 133 FEATURE_PWR_ALL, 134 FEATURE_PWR_S5, 135 FEATURE_PWR_BACO, 136 FEATURE_PWR_SOC, 137 FEATURE_PWR_GFX, 138 FEATURE_PWR_DOMAIN_COUNT, 139} FEATURE_PWR_DOMAIN_e; 140 141 142// Debug Overrides Bitmask 143#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 144#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 145#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 146#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 147#define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 148#define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 149#define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 150#define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 151#define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 152#define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 153#define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 154#define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 155#define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 156 157// VR Mapping Bit Defines 158#define VR_MAPPING_VR_SELECT_MASK 0x01 159#define VR_MAPPING_VR_SELECT_SHIFT 0x00 160 161#define VR_MAPPING_PLANE_SELECT_MASK 0x02 162#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 163 164// PSI Bit Defines 165#define PSI_SEL_VR0_PLANE0_PSI0 0x01 166#define PSI_SEL_VR0_PLANE0_PSI1 0x02 167#define PSI_SEL_VR0_PLANE1_PSI0 0x04 168#define PSI_SEL_VR0_PLANE1_PSI1 0x08 169#define PSI_SEL_VR1_PLANE0_PSI0 0x10 170#define PSI_SEL_VR1_PLANE0_PSI1 0x20 171#define PSI_SEL_VR1_PLANE1_PSI0 0x40 172#define PSI_SEL_VR1_PLANE1_PSI1 0x80 173 174typedef enum { 175 SVI_PSI_0, // Full phase count (default) 176 SVI_PSI_1, // Phase count 1st level 177 SVI_PSI_2, // Phase count 2nd level 178 SVI_PSI_3, // Single phase operation + active diode emulation 179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 180 SVI_PSI_5, // Reserved 181 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 182 SVI_PSI_7, // Automated phase shedding and diode emulation 183} SVI_PSI_e; 184 185// Throttler Control/Status Bits 186#define THROTTLER_TEMP_EDGE_BIT 0 187#define THROTTLER_TEMP_HOTSPOT_BIT 1 188#define THROTTLER_TEMP_HOTSPOT_G_BIT 2 189#define THROTTLER_TEMP_HOTSPOT_M_BIT 3 190#define THROTTLER_TEMP_MEM_BIT 4 191#define THROTTLER_TEMP_VR_GFX_BIT 5 192#define THROTTLER_TEMP_VR_MEM0_BIT 6 193#define THROTTLER_TEMP_VR_MEM1_BIT 7 194#define THROTTLER_TEMP_VR_SOC_BIT 8 195#define THROTTLER_TEMP_VR_U_BIT 9 196#define THROTTLER_TEMP_LIQUID0_BIT 10 197#define THROTTLER_TEMP_LIQUID1_BIT 11 198#define THROTTLER_TEMP_PLX_BIT 12 199#define THROTTLER_TDC_GFX_BIT 13 200#define THROTTLER_TDC_SOC_BIT 14 201#define THROTTLER_TDC_U_BIT 15 202#define THROTTLER_PPT0_BIT 16 203#define THROTTLER_PPT1_BIT 17 204#define THROTTLER_PPT2_BIT 18 205#define THROTTLER_PPT3_BIT 19 206#define THROTTLER_FIT_BIT 20 207#define THROTTLER_GFX_APCC_PLUS_BIT 21 208#define THROTTLER_COUNT 22 209 210// FW DState Features Control Bits 211#define FW_DSTATE_SOC_ULV_BIT 0 212#define FW_DSTATE_G6_HSR_BIT 1 213#define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 214#define FW_DSTATE_SMN_DS_BIT 3 215#define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 216#define FW_DSTATE_SOC_LIV_MIN_BIT 5 217#define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 218#define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 219#define FW_DSTATE_MALL_ALLOC_BIT 8 220#define FW_DSTATE_MEM_PSI_BIT 9 221#define FW_DSTATE_HSR_NON_STROBE_BIT 10 222#define FW_DSTATE_MP0_ENTER_WFI_BIT 11 223#define FW_DSTATE_U_ULV_BIT 12 224#define FW_DSTATE_MALL_FLUSH_BIT 13 225#define FW_DSTATE_SOC_PSI_BIT 14 226#define FW_DSTATE_U_PSI_BIT 15 227#define FW_DSTATE_UCP_DS_BIT 16 228#define FW_DSTATE_CSRCLK_DS_BIT 17 229#define FW_DSTATE_MMHUB_INTERLOCK_BIT 18 230#define FW_DSTATE_D0i3_2_QUIET_FW_BIT 19 231#define FW_DSTATE_CLDO_PRG_BIT 20 232#define FW_DSTATE_DF_PLL_PWRDN_BIT 21 233#define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT 22 234#define FW_DSTATE_GFX_PSI6_BIT 23 235#define FW_DSTATE_GFX_VR_PWR_STAGE_BIT 24 236 237//LED Display Mask & Control Bits 238#define LED_DISPLAY_GFX_DPM_BIT 0 239#define LED_DISPLAY_PCIE_BIT 1 240#define LED_DISPLAY_ERROR_BIT 2 241 242 243#define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244#define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245#define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246 247typedef enum { 248 SMARTSHIFT_VERSION_1, 249 SMARTSHIFT_VERSION_2, 250 SMARTSHIFT_VERSION_3, 251} SMARTSHIFT_VERSION_e; 252 253typedef enum { 254 FOPT_CALC_AC_CALC_DC, 255 FOPT_PPTABLE_AC_CALC_DC, 256 FOPT_CALC_AC_PPTABLE_DC, 257 FOPT_PPTABLE_AC_PPTABLE_DC, 258} FOPT_CALC_e; 259 260typedef enum { 261 DRAM_BIT_WIDTH_DISABLED = 0, 262 DRAM_BIT_WIDTH_X_8 = 8, 263 DRAM_BIT_WIDTH_X_16 = 16, 264 DRAM_BIT_WIDTH_X_32 = 32, 265 DRAM_BIT_WIDTH_X_64 = 64, 266 DRAM_BIT_WIDTH_X_128 = 128, 267 DRAM_BIT_WIDTH_COUNT, 268} DRAM_BIT_WIDTH_TYPE_e; 269 270//I2C Interface 271#define NUM_I2C_CONTROLLERS 8 272 273#define I2C_CONTROLLER_ENABLED 1 274#define I2C_CONTROLLER_DISABLED 0 275 276#define MAX_SW_I2C_COMMANDS 24 277 278typedef enum { 279 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281 I2C_CONTROLLER_PORT_COUNT, 282} I2cControllerPort_e; 283 284typedef enum { 285 I2C_CONTROLLER_NAME_VR_GFX = 0, 286 I2C_CONTROLLER_NAME_VR_SOC, 287 I2C_CONTROLLER_NAME_VR_VMEMP, 288 I2C_CONTROLLER_NAME_VR_VDDIO, 289 I2C_CONTROLLER_NAME_LIQUID0, 290 I2C_CONTROLLER_NAME_LIQUID1, 291 I2C_CONTROLLER_NAME_PLX, 292 I2C_CONTROLLER_NAME_FAN_INTAKE, 293 I2C_CONTROLLER_NAME_COUNT, 294} I2cControllerName_e; 295 296typedef enum { 297 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298 I2C_CONTROLLER_THROTTLER_VR_GFX, 299 I2C_CONTROLLER_THROTTLER_VR_SOC, 300 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302 I2C_CONTROLLER_THROTTLER_LIQUID0, 303 I2C_CONTROLLER_THROTTLER_LIQUID1, 304 I2C_CONTROLLER_THROTTLER_PLX, 305 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 306 I2C_CONTROLLER_THROTTLER_INA3221, 307 I2C_CONTROLLER_THROTTLER_COUNT, 308} I2cControllerThrottler_e; 309 310typedef enum { 311 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 312 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 313 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 314 I2C_CONTROLLER_PROTOCOL_INA3221, 315 I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 316 I2C_CONTROLLER_PROTOCOL_COUNT, 317} I2cControllerProtocol_e; 318 319typedef struct { 320 uint8_t Enabled; 321 uint8_t Speed; 322 uint8_t SlaveAddress; 323 uint8_t ControllerPort; 324 uint8_t ControllerName; 325 uint8_t ThermalThrotter; 326 uint8_t I2cProtocol; 327 uint8_t PaddingConfig; 328} I2cControllerConfig_t; 329 330typedef enum { 331 I2C_PORT_SVD_SCL = 0, 332 I2C_PORT_GPIO, 333} I2cPort_e; 334 335typedef enum { 336 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 337 I2C_SPEED_FAST_100K, //100 Kbits/s 338 I2C_SPEED_FAST_400K, //400 Kbits/s 339 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 340 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 341 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 342 I2C_SPEED_COUNT, 343} I2cSpeed_e; 344 345typedef enum { 346 I2C_CMD_READ = 0, 347 I2C_CMD_WRITE, 348 I2C_CMD_COUNT, 349} I2cCmdType_e; 350 351#define CMDCONFIG_STOP_BIT 0 352#define CMDCONFIG_RESTART_BIT 1 353#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 354 355#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 356#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 357#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 358 359typedef struct { 360 uint8_t ReadWriteData; //Return data for read. Data to send for write 361 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 362} SwI2cCmd_t; //SW I2C Command Table 363 364typedef struct { 365 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 366 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 367 uint8_t SlaveAddress; //Slave address of device 368 uint8_t NumCmds; //Number of commands 369 370 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 371} SwI2cRequest_t; // SW I2C Request Table 372 373typedef struct { 374 SwI2cRequest_t SwI2cRequest; 375 376 uint32_t Spare[8]; 377 uint32_t MmHubPadding[8]; // SMU internal use 378} SwI2cRequestExternal_t; 379 380typedef struct { 381 uint64_t mca_umc_status; 382 uint64_t mca_umc_addr; 383 384 uint16_t ce_count_lo_chip; 385 uint16_t ce_count_hi_chip; 386 387 uint32_t eccPadding; 388} EccInfo_t; 389 390typedef struct { 391 EccInfo_t EccInfo[24]; 392} EccInfoTable_t; 393 394//D3HOT sequences 395typedef enum { 396 BACO_SEQUENCE, 397 MSR_SEQUENCE, 398 BAMACO_SEQUENCE, 399 ULPS_SEQUENCE, 400 D3HOT_SEQUENCE_COUNT, 401} D3HOTSequence_e; 402 403//This is aligned with RSMU PGFSM Register Mapping 404typedef enum { 405 PG_DYNAMIC_MODE = 0, 406 PG_STATIC_MODE, 407} PowerGatingMode_e; 408 409//This is aligned with RSMU PGFSM Register Mapping 410typedef enum { 411 PG_POWER_DOWN = 0, 412 PG_POWER_UP, 413} PowerGatingSettings_e; 414 415typedef struct { 416 uint32_t a; // store in IEEE float format in this variable 417 uint32_t b; // store in IEEE float format in this variable 418 uint32_t c; // store in IEEE float format in this variable 419} QuadraticInt_t; 420 421typedef struct { 422 uint32_t m; // store in IEEE float format in this variable 423 uint32_t b; // store in IEEE float format in this variable 424} LinearInt_t; 425 426typedef struct { 427 uint32_t a; // store in IEEE float format in this variable 428 uint32_t b; // store in IEEE float format in this variable 429 uint32_t c; // store in IEEE float format in this variable 430} DroopInt_t; 431 432typedef enum { 433 DCS_ARCH_DISABLED, 434 DCS_ARCH_FADCS, 435 DCS_ARCH_ASYNC, 436} DCS_ARCH_e; 437 438//Only Clks that have DPM descriptors are listed here 439typedef enum { 440 PPCLK_GFXCLK = 0, 441 PPCLK_SOCCLK, 442 PPCLK_UCLK, 443 PPCLK_FCLK, 444 PPCLK_DCLK_0, 445 PPCLK_VCLK_0, 446 PPCLK_DCLK_1, 447 PPCLK_VCLK_1, 448 PPCLK_DISPCLK, 449 PPCLK_DPPCLK, 450 PPCLK_DPREFCLK, 451 PPCLK_DCFCLK, 452 PPCLK_DTBCLK, 453 PPCLK_COUNT, 454} PPCLK_e; 455 456typedef enum { 457 VOLTAGE_MODE_PPTABLE = 0, 458 VOLTAGE_MODE_FUSES, 459 VOLTAGE_MODE_COUNT, 460} VOLTAGE_MODE_e; 461 462 463typedef enum { 464 AVFS_VOLTAGE_GFX = 0, 465 AVFS_VOLTAGE_SOC, 466 AVFS_VOLTAGE_COUNT, 467} AVFS_VOLTAGE_TYPE_e; 468 469typedef enum { 470 AVFS_TEMP_COLD = 0, 471 AVFS_TEMP_HOT, 472 AVFS_TEMP_COUNT, 473} AVFS_TEMP_e; 474 475typedef enum { 476 AVFS_D_G, 477 AVFS_D_M_B, 478 AVFS_D_M_S, 479 AVFS_D_COUNT, 480} AVFS_D_e; 481 482typedef enum { 483 UCLK_DIV_BY_1 = 0, 484 UCLK_DIV_BY_2, 485 UCLK_DIV_BY_4, 486 UCLK_DIV_BY_8, 487} UCLK_DIV_e; 488 489typedef enum { 490 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 491 GPIO_INT_POLARITY_ACTIVE_HIGH, 492} GpioIntPolarity_e; 493 494typedef enum { 495 PWR_CONFIG_TDP = 0, 496 PWR_CONFIG_TGP, 497 PWR_CONFIG_TCP_ESTIMATED, 498 PWR_CONFIG_TCP_MEASURED, 499} PwrConfig_e; 500 501typedef struct { 502 uint8_t Padding; 503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 504 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 505 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 507 uint32_t Padding3[3]; 508 uint16_t Padding4; 509 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 510 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 511 uint16_t Padding2; 512} DpmDescriptor_t; 513 514typedef enum { 515 PPT_THROTTLER_PPT0, 516 PPT_THROTTLER_PPT1, 517 PPT_THROTTLER_PPT2, 518 PPT_THROTTLER_PPT3, 519 PPT_THROTTLER_COUNT 520} PPT_THROTTLER_e; 521 522typedef enum { 523 TEMP_EDGE, 524 TEMP_HOTSPOT, 525 TEMP_HOTSPOT_G, 526 TEMP_HOTSPOT_M, 527 TEMP_MEM, 528 TEMP_VR_GFX, 529 TEMP_VR_MEM0, 530 TEMP_VR_MEM1, 531 TEMP_VR_SOC, 532 TEMP_VR_U, 533 TEMP_LIQUID0, 534 TEMP_LIQUID1, 535 TEMP_PLX, 536 TEMP_COUNT, 537} TEMP_e; 538 539typedef enum { 540 TDC_THROTTLER_GFX, 541 TDC_THROTTLER_SOC, 542 TDC_THROTTLER_U, 543 TDC_THROTTLER_COUNT 544} TDC_THROTTLER_e; 545 546typedef enum { 547 SVI_PLANE_GFX, 548 SVI_PLANE_SOC, 549 SVI_PLANE_VMEMP, 550 SVI_PLANE_VDDIO_MEM, 551 SVI_PLANE_U, 552 SVI_PLANE_COUNT, 553} SVI_PLANE_e; 554 555typedef enum { 556 PMFW_VOLT_PLANE_GFX, 557 PMFW_VOLT_PLANE_SOC, 558 PMFW_VOLT_PLANE_COUNT 559} PMFW_VOLT_PLANE_e; 560 561typedef enum { 562 CUSTOMER_VARIANT_ROW, 563 CUSTOMER_VARIANT_FALCON, 564 CUSTOMER_VARIANT_COUNT, 565} CUSTOMER_VARIANT_e; 566 567typedef enum { 568 POWER_SOURCE_AC, 569 POWER_SOURCE_DC, 570 POWER_SOURCE_COUNT, 571} POWER_SOURCE_e; 572 573typedef enum { 574 MEM_VENDOR_PLACEHOLDER0, 575 MEM_VENDOR_SAMSUNG, 576 MEM_VENDOR_INFINEON, 577 MEM_VENDOR_ELPIDA, 578 MEM_VENDOR_ETRON, 579 MEM_VENDOR_NANYA, 580 MEM_VENDOR_HYNIX, 581 MEM_VENDOR_MOSEL, 582 MEM_VENDOR_WINBOND, 583 MEM_VENDOR_ESMT, 584 MEM_VENDOR_PLACEHOLDER1, 585 MEM_VENDOR_PLACEHOLDER2, 586 MEM_VENDOR_PLACEHOLDER3, 587 MEM_VENDOR_PLACEHOLDER4, 588 MEM_VENDOR_PLACEHOLDER5, 589 MEM_VENDOR_MICRON, 590 MEM_VENDOR_COUNT, 591} MEM_VENDOR_e; 592 593typedef enum { 594 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 595 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 596 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 597 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 598 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 599 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 600 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 601 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 602 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 603 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 604 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 605 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 606 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 607 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 608 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 609 PP_GRTAVFS_HW_ZONE0_VF, 610 PP_GRTAVFS_HW_ZONE1_VF1, 611 PP_GRTAVFS_HW_ZONE2_VF2, 612 PP_GRTAVFS_HW_ZONE3_VF3, 613 PP_GRTAVFS_HW_VOLTAGE_GB, 614 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 615 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 616 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 617 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 618 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 619 PP_GRTAVFS_HW_RESERVED_0, 620 PP_GRTAVFS_HW_RESERVED_1, 621 PP_GRTAVFS_HW_RESERVED_2, 622 PP_GRTAVFS_HW_RESERVED_3, 623 PP_GRTAVFS_HW_RESERVED_4, 624 PP_GRTAVFS_HW_RESERVED_5, 625 PP_GRTAVFS_HW_RESERVED_6, 626 PP_GRTAVFS_HW_FUSE_COUNT, 627} PP_GRTAVFS_HW_FUSE_e; 628 629typedef enum { 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 633 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 634 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 635 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 636 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 637 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 638 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 639 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 640 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 641 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 642 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 643 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 644} PP_GRTAVFS_FW_COMMON_FUSE_e; 645 646typedef enum { 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 648 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 649 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 650 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 651 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 652 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 654 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 655 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 656 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 657 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 658 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 659 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 660 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 661 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 662 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 663 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 664 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 665 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 666 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 667} PP_GRTAVFS_FW_SEP_FUSE_e; 668 669#define PP_NUM_RTAVFS_PWL_ZONES 5 670 671#define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 672#define PP_OD_FEATURE_PPT_BIT 2 673#define PP_OD_FEATURE_FAN_CURVE_BIT 3 674#define PP_OD_FEATURE_GFXCLK_BIT 7 675#define PP_OD_FEATURE_UCLK_BIT 8 676#define PP_OD_FEATURE_ZERO_FAN_BIT 9 677#define PP_OD_FEATURE_TEMPERATURE_BIT 10 678#define PP_OD_FEATURE_COUNT 13 679 680// VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 681// Slope Q1.7, Offset Q1.2 682typedef struct { 683 int8_t Offset; // in Amps 684 uint8_t Padding; 685 uint16_t MaxCurrent; // in Amps 686} SviTelemetryScale_t; 687 688#define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 689 690typedef enum { 691 FAN_MODE_AUTO = 0, 692 FAN_MODE_MANUAL_LINEAR, 693} FanMode_e; 694 695typedef struct { 696 uint32_t FeatureCtrlMask; 697 698 //Voltage control 699 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 700 701 uint32_t Reserved; 702 703 //Frequency changes 704 int16_t GfxclkFmin; // MHz 705 int16_t GfxclkFmax; // MHz 706 uint16_t UclkFmin; // MHz 707 uint16_t UclkFmax; // MHz 708 709 //PPT 710 int16_t Ppt; // % 711 int16_t Tdc; 712 713 //Fan control 714 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 715 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 716 uint16_t FanMinimumPwm; 717 uint16_t AcousticTargetRpmThreshold; 718 uint16_t AcousticLimitRpmThreshold; 719 uint16_t FanTargetTemperature; // Degree Celcius 720 uint8_t FanZeroRpmEnable; 721 uint8_t FanZeroRpmStopTemp; 722 uint8_t FanMode; 723 uint8_t MaxOpTemp; 724 725 uint32_t Spare[13]; 726 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 727} OverDriveTable_t; 728 729typedef struct { 730 OverDriveTable_t OverDriveTable; 731 732} OverDriveTableExternal_t; 733 734typedef struct { 735 uint32_t FeatureCtrlMask; 736 737 int16_t VoltageOffsetPerZoneBoundary; 738 uint16_t Reserved1; 739 740 uint16_t Reserved2; 741 742 int16_t GfxclkFmin; // MHz 743 int16_t GfxclkFmax; // MHz 744 uint16_t UclkFmin; // MHz 745 uint16_t UclkFmax; // MHz 746 747 //PPT 748 int16_t Ppt; // % 749 int16_t Tdc; 750 751 uint8_t FanLinearPwmPoints; 752 uint8_t FanLinearTempPoints; 753 uint16_t FanMinimumPwm; 754 uint16_t AcousticTargetRpmThreshold; 755 uint16_t AcousticLimitRpmThreshold; 756 uint16_t FanTargetTemperature; // Degree Celcius 757 uint8_t FanZeroRpmEnable; 758 uint8_t FanZeroRpmStopTemp; 759 uint8_t FanMode; 760 uint8_t MaxOpTemp; 761 762 uint32_t Spare[13]; 763 764} OverDriveLimits_t; 765 766 767typedef enum { 768 BOARD_GPIO_SMUIO_0, 769 BOARD_GPIO_SMUIO_1, 770 BOARD_GPIO_SMUIO_2, 771 BOARD_GPIO_SMUIO_3, 772 BOARD_GPIO_SMUIO_4, 773 BOARD_GPIO_SMUIO_5, 774 BOARD_GPIO_SMUIO_6, 775 BOARD_GPIO_SMUIO_7, 776 BOARD_GPIO_SMUIO_8, 777 BOARD_GPIO_SMUIO_9, 778 BOARD_GPIO_SMUIO_10, 779 BOARD_GPIO_SMUIO_11, 780 BOARD_GPIO_SMUIO_12, 781 BOARD_GPIO_SMUIO_13, 782 BOARD_GPIO_SMUIO_14, 783 BOARD_GPIO_SMUIO_15, 784 BOARD_GPIO_SMUIO_16, 785 BOARD_GPIO_SMUIO_17, 786 BOARD_GPIO_SMUIO_18, 787 BOARD_GPIO_SMUIO_19, 788 BOARD_GPIO_SMUIO_20, 789 BOARD_GPIO_SMUIO_21, 790 BOARD_GPIO_SMUIO_22, 791 BOARD_GPIO_SMUIO_23, 792 BOARD_GPIO_SMUIO_24, 793 BOARD_GPIO_SMUIO_25, 794 BOARD_GPIO_SMUIO_26, 795 BOARD_GPIO_SMUIO_27, 796 BOARD_GPIO_SMUIO_28, 797 BOARD_GPIO_SMUIO_29, 798 BOARD_GPIO_SMUIO_30, 799 BOARD_GPIO_SMUIO_31, 800 MAX_BOARD_GPIO_SMUIO_NUM, 801 BOARD_GPIO_DC_GEN_A, 802 BOARD_GPIO_DC_GEN_B, 803 BOARD_GPIO_DC_GEN_C, 804 BOARD_GPIO_DC_GEN_D, 805 BOARD_GPIO_DC_GEN_E, 806 BOARD_GPIO_DC_GEN_F, 807 BOARD_GPIO_DC_GEN_G, 808 BOARD_GPIO_DC_GENLK_CLK, 809 BOARD_GPIO_DC_GENLK_VSYNC, 810 BOARD_GPIO_DC_SWAPLOCK_A, 811 BOARD_GPIO_DC_SWAPLOCK_B, 812} BOARD_GPIO_TYPE_e; 813 814#define INVALID_BOARD_GPIO 0xFF 815 816#define MARKETING_BASE_CLOCKS 0 817#define MARKETING_GAME_CLOCKS 1 818#define MARKETING_BOOST_CLOCKS 2 819 820typedef struct { 821 //PLL 0 822 uint16_t InitGfxclk_bypass; 823 uint16_t InitSocclk; 824 uint16_t InitMp0clk; 825 uint16_t InitMpioclk; 826 uint16_t InitSmnclk; 827 uint16_t InitUcpclk; 828 uint16_t InitCsrclk; 829 //PLL 1 830 831 uint16_t InitDprefclk; 832 uint16_t InitDcfclk; 833 uint16_t InitDtbclk; 834 //PLL 2 835 uint16_t InitDclk; //assume same DCLK/VCLK for both instances 836 uint16_t InitVclk; 837 // PLL 3 838 uint16_t InitUsbdfsclk; 839 uint16_t InitMp1clk; 840 uint16_t InitLclk; 841 uint16_t InitBaco400clk_bypass; 842 uint16_t InitBaco1200clk_bypass; 843 uint16_t InitBaco700clk_bypass; 844 // PLL 4 845 uint16_t InitFclk; 846 // PLL 5 847 uint16_t InitGfxclk_clkb; 848 849 //PLL 6 850 uint8_t InitUclkDPMState; // =0,1,2,3, frequency from FreqTableUclk 851 852 uint8_t Padding[3]; 853 854 uint32_t InitVcoFreqPll0; 855 uint32_t InitVcoFreqPll1; 856 uint32_t InitVcoFreqPll2; 857 uint32_t InitVcoFreqPll3; 858 uint32_t InitVcoFreqPll4; 859 uint32_t InitVcoFreqPll5; 860 uint32_t InitVcoFreqPll6; 861 862 //encoding will change depending on SVI2/SVI3 863 uint16_t InitGfx; // In mV(Q2) , should be 0? 864 uint16_t InitSoc; // In mV(Q2) 865 uint16_t InitU; // In Mv(Q2) 866 867 uint16_t Padding2; 868 869 uint32_t Spare[8]; 870 871} BootValues_t; 872 873 874typedef struct { 875 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 876 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 877 878 uint16_t Temperature[TEMP_COUNT]; // Celsius 879 880 uint8_t PwmLimitMin; 881 uint8_t PwmLimitMax; 882 uint8_t FanTargetTemperature; 883 uint8_t Spare1[1]; 884 885 uint16_t AcousticTargetRpmThresholdMin; 886 uint16_t AcousticTargetRpmThresholdMax; 887 888 uint16_t AcousticLimitRpmThresholdMin; 889 uint16_t AcousticLimitRpmThresholdMax; 890 891 uint16_t PccLimitMin; 892 uint16_t PccLimitMax; 893 894 uint16_t FanStopTempMin; 895 uint16_t FanStopTempMax; 896 uint16_t FanStartTempMin; 897 uint16_t FanStartTempMax; 898 899 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 900 uint32_t Spare[11]; 901 902} MsgLimits_t; 903 904typedef struct { 905 uint16_t BaseClockAc; 906 uint16_t GameClockAc; 907 uint16_t BoostClockAc; 908 uint16_t BaseClockDc; 909 uint16_t GameClockDc; 910 uint16_t BoostClockDc; 911 912 uint32_t Reserved[4]; 913} DriverReportedClocks_t; 914 915typedef struct { 916 uint8_t DcBtcEnabled; 917 uint8_t Padding[3]; 918 919 uint16_t DcTol; // mV Q2 920 uint16_t DcBtcGb; // mV Q2 921 922 uint16_t DcBtcMin; // mV Q2 923 uint16_t DcBtcMax; // mV Q2 924 925 LinearInt_t DcBtcGbScalar; 926 927} AvfsDcBtcParams_t; 928 929typedef struct { 930 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 931 uint16_t VftFMin; // in MHz 932 uint16_t VInversion; // in mV Q2 933 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 934 QuadraticInt_t qAvfsGb; 935 QuadraticInt_t qAvfsGb2; 936} AvfsFuseOverride_t; 937 938typedef struct { 939 // SECTION: Version 940 941 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 942 943 // SECTION: Feature Control 944 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 945 946 // SECTION: Miscellaneous Configuration 947 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 948 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 949 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 950 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 951 952 // SECTION: Infrastructure Limits 953 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 954 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 955 956 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 957 958 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 959 //relative index 0 960 uint8_t EnableLegacyPptLimit; 961 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 962 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 963 964 uint8_t PaddingPpt[1]; 965 966 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 967 968 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 969 970 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 971 972 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 973 974 uint16_t PaddingInfra; 975 976 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 977 uint32_t FitControllerFailureRateLimit; //in IEEE float 978 //Expected GFX Duty Cycle at Vmax. 979 uint32_t FitControllerGfxDutyCycle; // in IEEE float 980 //Expected SOC Duty Cycle at Vmax. 981 uint32_t FitControllerSocDutyCycle; // in IEEE float 982 983 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 984 uint32_t FitControllerSocOffset; //in IEEE float 985 986 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 987 988 // SECTION: Throttler settings 989 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 990 991 // SECTION: FW DSTATE Settings 992 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 993 994 // SECTION: Voltage Control Parameters 995 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 996 997 uint16_t UlvVoltageOffsetU; // In mV(Q2). ULV offset used in either U_ULV(part of FW_DSTATE) 998 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 999 1000 // Voltage Limits 1001 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1002 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1003 1004 //Vmin Optimizations 1005 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1006 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1007 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1008 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1009 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1010 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1011 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1012 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1013 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1014 1015 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1016 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1017 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1018 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1019 //Scalar coefficient of the PSM aging degradation function 1020 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1021 //Exponential coefficient of the PSM aging degradation function 1022 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1023 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1024 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1025 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1026 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1027 1028 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1029 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1030 1031 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1032 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1033 1034 QuadraticInt_t Vmin_droop; 1035 uint32_t SpareVmin[9]; 1036 1037 1038 //SECTION: DPM Configuration 1 1039 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1040 1041 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1042 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1043 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1044 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1046 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1047 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1048 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1049 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1050 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1051 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1052 1053 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1054 1055 // SECTION: DPM Configuration 2 1056 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 1057 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 1058 1059 uint8_t GfxclkSpare[2]; 1060 uint16_t GfxclkFreqCap; 1061 1062 //GFX Idle Power Settings 1063 uint16_t GfxclkFgfxoffEntry; // in Mhz 1064 uint16_t GfxclkFgfxoffExitImu; // in Mhz 1065 uint16_t GfxclkFgfxoffExitRlc; // in Mhz 1066 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1067 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1068 uint8_t GfxIdlePadding; 1069 1070 uint8_t SmsRepairWRCKClkDivEn; 1071 uint8_t SmsRepairWRCKClkDivVal; 1072 uint8_t GfxOffEntryEarlyMGCGEn; 1073 uint8_t GfxOffEntryForceCGCGEn; 1074 uint8_t GfxOffEntryForceCGCGDelayEn; 1075 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1076 1077 uint16_t GfxclkFreqGfxUlv; // in MHz 1078 uint8_t GfxIdlePadding2[2]; 1079 1080 uint32_t GfxOffEntryHysteresis; 1081 uint32_t GfxoffSpare[15]; 1082 1083 // GFX GPO 1084 uint32_t DfllBtcMasterScalerM; 1085 int32_t DfllBtcMasterScalerB; 1086 uint32_t DfllBtcSlaveScalerM; 1087 int32_t DfllBtcSlaveScalerB; 1088 1089 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1090 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1091 1092 uint32_t DfllL2FrequencyBoostM; //Unitless (float) 1093 uint32_t DfllL2FrequencyBoostB; //In MHz (integer) 1094 uint32_t GfxGpoSpare[8]; 1095 1096 // GFX DCS 1097 1098 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1099 uint16_t PaddingDcs; 1100 1101 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1102 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1103 1104 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1105 1106 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1107 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1108 1109 uint8_t FoptEnabled; 1110 uint8_t DcsSpare2[3]; 1111 uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation 1112 uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation 1113 1114 uint32_t DcsSpare[11]; 1115 1116 // UCLK section 1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz 1118 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1119 uint8_t PaddingMem[3]; 1120 1121 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 1122 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1123 1124 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1125 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1126 1127 //FCLK Section 1128 1129 uint8_t FclkDpmUPstates[NUM_FCLK_DPM_LEVELS]; // U P-state ID associated with each FCLK DPM state. 1130 uint16_t FclkDpmVddU[NUM_FCLK_DPM_LEVELS]; // mV(Q2) Vset U voltage associated with each FCLK DPM state. 1131 uint16_t FclkDpmUSpeed[NUM_FCLK_DPM_LEVELS]; //U speed associated with each FCLK DPM state 1132 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1133 uint16_t PaddingFclk; 1134 1135 // Link DPM Settings 1136 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 1137 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1138 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1139 1140 // SECTION: Fan Control 1141 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1142 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1143 1144 uint16_t FanGain[TEMP_COUNT]; 1145 uint16_t FanGainPadding; 1146 1147 uint16_t FanPwmMin; 1148 uint16_t AcousticTargetRpmThreshold; 1149 uint16_t AcousticLimitRpmThreshold; 1150 uint16_t FanMaximumRpm; 1151 uint16_t MGpuAcousticLimitRpmThreshold; 1152 uint16_t FanTargetGfxclk; 1153 uint32_t TempInputSelectMask; 1154 uint8_t FanZeroRpmEnable; 1155 uint8_t FanTachEdgePerRev; 1156 uint16_t FanTargetTemperature[TEMP_COUNT]; 1157 1158 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1159 int16_t FuzzyFan_ErrorSetDelta; 1160 int16_t FuzzyFan_ErrorRateSetDelta; 1161 int16_t FuzzyFan_PwmSetDelta; 1162 uint16_t FuzzyFan_Reserved; 1163 1164 uint16_t FwCtfLimit[TEMP_COUNT]; 1165 1166 uint16_t IntakeTempEnableRPM; 1167 int16_t IntakeTempOffsetTemp; 1168 uint16_t IntakeTempReleaseTemp; 1169 uint16_t IntakeTempHighIntakeAcousticLimit; 1170 uint16_t IntakeTempAcouticLimitReleaseRate; 1171 1172 int16_t FanAbnormalTempLimitOffset; 1173 uint16_t FanStalledTriggerRpm; 1174 uint16_t FanAbnormalTriggerRpmCoeff; 1175 uint16_t FanAbnormalDetectionEnable; 1176 1177 uint8_t FanIntakeSensorSupport; 1178 uint8_t FanIntakePadding[3]; 1179 uint32_t FanSpare[13]; 1180 1181 // SECTION: VDD_GFX AVFS 1182 1183 uint8_t OverrideGfxAvfsFuses; 1184 uint8_t GfxAvfsPadding[3]; 1185 1186 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1187 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1188 1189 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1190 1191 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1192 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1193 1194 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1195 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1196 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1197 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1198 1199 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1200 1201 uint32_t dGbV_dT_vmin; 1202 uint32_t dGbV_dT_vmax; 1203 1204 //Unused: PMFW-9370 1205 uint32_t V2F_vmin_range_low; 1206 uint32_t V2F_vmin_range_high; 1207 uint32_t V2F_vmax_range_low; 1208 uint32_t V2F_vmax_range_high; 1209 1210 AvfsDcBtcParams_t DcBtcGfxParams; 1211 1212 uint32_t GfxAvfsSpare[32]; 1213 1214 //SECTION: VDD_SOC AVFS 1215 1216 uint8_t OverrideSocAvfsFuses; 1217 uint8_t MinSocAvfsRevision; 1218 uint8_t SocAvfsPadding[2]; 1219 1220 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1221 1222 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1223 1224 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1225 1226 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1227 1228 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1229 1230 uint32_t SocAvfsSpare[32]; 1231 1232 //SECTION: Boot clock and voltage values 1233 BootValues_t BootValues; 1234 1235 //SECTION: Driver Reported Clocks 1236 DriverReportedClocks_t DriverReportedClocks; 1237 1238 //SECTION: Message Limits 1239 MsgLimits_t MsgLimits; 1240 1241 //SECTION: OverDrive Limits 1242 OverDriveLimits_t OverDriveLimitsMin; 1243 OverDriveLimits_t OverDriveLimitsBasicMax; 1244 uint32_t reserved[22]; 1245 1246 // SECTION: Advanced Options 1247 uint32_t DebugOverrides; 1248 1249 // Section: Total Board Power idle vs active coefficients 1250 uint8_t TotalBoardPowerSupport; 1251 uint8_t TotalBoardPowerPadding[3]; 1252 1253 int16_t TotalIdleBoardPowerM; 1254 int16_t TotalIdleBoardPowerB; 1255 int16_t TotalBoardPowerM; 1256 int16_t TotalBoardPowerB; 1257 1258 //PMFW-11158 1259 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1260 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1261 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1262 1263 uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix 1264 uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron 1265 uint16_t TemperatureFwCtfLimit_Hynix; 1266 uint16_t TemperatureFwCtfLimit_Micron; 1267 1268 // SECTION: Sku Reserved 1269 uint32_t Spare[41]; 1270 1271 // Padding for MMHUB - do not modify this 1272 uint32_t MmHubPadding[8]; 1273 1274} SkuTable_t; 1275 1276typedef struct { 1277 // SECTION: Version 1278 uint32_t Version; //should be unique to each board type 1279 1280 1281 // SECTION: I2C Control 1282 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1283 1284 // SECTION: SVI2 Board Parameters 1285 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1286 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1287 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1288 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1289 1290 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1291 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1292 uint8_t VmempUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1293 uint8_t VddioUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1294 1295 //SECTION SVI3 Board Parameters 1296 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1297 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1298 1299 uint8_t PaddingPsi[SVI_PLANE_COUNT]; 1300 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1301 1302 // SECTION: Voltage Regulator Settings 1303 SviTelemetryScale_t SviTelemetryScale[SVI_PLANE_COUNT]; 1304 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 1305 1306 uint8_t DownSlewRateVr[SVI_PLANE_COUNT]; 1307 1308 // SECTION: GPIO Settings 1309 1310 uint8_t LedOffGpio; 1311 uint8_t FanOffGpio; 1312 uint8_t GfxVrPowerStageOffGpio; 1313 1314 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1315 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1316 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1317 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1318 1319 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1320 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1321 1322 // LED Display Settings 1323 uint8_t LedPin0; // GPIO number for LedPin[0] 1324 uint8_t LedPin1; // GPIO number for LedPin[1] 1325 uint8_t LedPin2; // GPIO number for LedPin[2] 1326 uint8_t LedEnableMask; 1327 1328 uint8_t LedPcie; // GPIO number for PCIE results 1329 uint8_t LedError; // GPIO number for Error Cases 1330 1331 // SECTION: Clock Spread Spectrum 1332 1333 // UCLK Spread Spectrum 1334 uint8_t UclkTrainingModeSpreadPercent; 1335 uint8_t UclkSpreadPadding; 1336 uint16_t UclkSpreadFreq; // kHz 1337 1338 // UCLK Spread Spectrum 1339 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1340 1341 uint8_t GfxclkSpreadEnable; 1342 1343 // FCLK Spread Spectrum 1344 uint8_t FclkSpreadPercent; // Q4.4 1345 uint16_t FclkSpreadFreq; // kHz 1346 1347 // Section: Memory Config 1348 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1349 uint8_t PaddingMem1[7]; 1350 1351 // SECTION: UMC feature flags 1352 uint8_t HsrEnabled; 1353 uint8_t VddqOffEnabled; 1354 uint8_t PaddingUmcFlags[2]; 1355 1356 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1357 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1358 1359 uint8_t FuseWritePowerMuxPresent; 1360 uint8_t FuseWritePadding[3]; 1361 1362 // SECTION: Board Reserved 1363 uint32_t BoardSpare[63]; 1364 1365 // SECTION: Structure Padding 1366 1367 // Padding for MMHUB - do not modify this 1368 uint32_t MmHubPadding[8]; 1369} BoardTable_t; 1370 1371#pragma pack(push, 1) 1372typedef struct { 1373 SkuTable_t SkuTable; 1374 BoardTable_t BoardTable; 1375} PPTable_t; 1376#pragma pack(pop) 1377 1378typedef struct { 1379 // Time constant parameters for clock averages in ms 1380 uint16_t GfxclkAverageLpfTau; 1381 uint16_t FclkAverageLpfTau; 1382 uint16_t UclkAverageLpfTau; 1383 uint16_t GfxActivityLpfTau; 1384 uint16_t UclkActivityLpfTau; 1385 uint16_t SocketPowerLpfTau; 1386 uint16_t VcnClkAverageLpfTau; 1387 uint16_t VcnUsageAverageLpfTau; 1388} DriverSmuConfig_t; 1389 1390typedef struct { 1391 DriverSmuConfig_t DriverSmuConfig; 1392 1393 uint32_t Spare[8]; 1394 // Padding - ignore 1395 uint32_t MmHubPadding[8]; // SMU internal use 1396} DriverSmuConfigExternal_t; 1397 1398 1399typedef struct { 1400 1401 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1402 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1403 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1404 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1405 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1406 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1407 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1408 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1409 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1410 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1411 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1412 1413 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1414 1415 uint16_t Padding; 1416 1417 uint32_t Spare[32]; 1418 1419 // Padding - ignore 1420 uint32_t MmHubPadding[8]; // SMU internal use 1421 1422} DriverInfoTable_t; 1423 1424typedef struct { 1425 uint32_t CurrClock[PPCLK_COUNT]; 1426 1427 uint16_t AverageGfxclkFrequencyTarget; 1428 uint16_t AverageGfxclkFrequencyPreDs; 1429 uint16_t AverageGfxclkFrequencyPostDs; 1430 uint16_t AverageFclkFrequencyPreDs; 1431 uint16_t AverageFclkFrequencyPostDs; 1432 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1433 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1434 uint16_t AverageVclk0Frequency ; 1435 uint16_t AverageDclk0Frequency ; 1436 uint16_t AverageVclk1Frequency ; 1437 uint16_t AverageDclk1Frequency ; 1438 uint16_t PCIeBusy; 1439 uint16_t dGPU_W_MAX; 1440 uint16_t padding; 1441 1442 uint32_t MetricsCounter; 1443 1444 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1445 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1446 1447 uint16_t AverageGfxActivity ; 1448 uint16_t AverageUclkActivity ; 1449 uint16_t Vcn0ActivityPercentage ; 1450 uint16_t Vcn1ActivityPercentage ; 1451 1452 uint32_t EnergyAccumulator; 1453 uint16_t AverageSocketPower; 1454 uint16_t AverageTotalBoardPower; 1455 1456 uint16_t AvgTemperature[TEMP_COUNT]; 1457 uint16_t AvgTemperatureFanIntake; 1458 1459 uint8_t PcieRate ; 1460 uint8_t PcieWidth ; 1461 1462 uint8_t AvgFanPwm; 1463 uint8_t Padding[1]; 1464 uint16_t AvgFanRpm; 1465 1466 1467 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1468 uint8_t VmaxThrottlingPercentage; 1469 uint8_t Padding1[3]; 1470 1471 //metrics for D3hot entry/exit and driver ARM msgs 1472 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1473 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1474 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1475 1476 uint16_t ApuSTAPMSmartShiftLimit; 1477 uint16_t ApuSTAPMLimit; 1478 uint16_t AvgApuSocketPower; 1479 1480 uint16_t AverageUclkActivity_MAX; 1481 1482 uint32_t PublicSerialNumberLower; 1483 uint32_t PublicSerialNumberUpper; 1484 1485} SmuMetrics_t; 1486 1487typedef struct { 1488 SmuMetrics_t SmuMetrics; 1489 uint32_t Spare[29]; 1490 1491 // Padding - ignore 1492 uint32_t MmHubPadding[8]; // SMU internal use 1493} SmuMetricsExternal_t; 1494 1495typedef struct { 1496 uint8_t WmSetting; 1497 uint8_t Flags; 1498 uint8_t Padding[2]; 1499 1500} WatermarkRowGeneric_t; 1501 1502#define NUM_WM_RANGES 4 1503 1504typedef enum { 1505 WATERMARKS_CLOCK_RANGE = 0, 1506 WATERMARKS_DUMMY_PSTATE, 1507 WATERMARKS_MALL, 1508 WATERMARKS_COUNT, 1509} WATERMARKS_FLAGS_e; 1510 1511typedef struct { 1512 // Watermarks 1513 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1514} Watermarks_t; 1515 1516typedef struct { 1517 Watermarks_t Watermarks; 1518 uint32_t Spare[16]; 1519 1520 uint32_t MmHubPadding[8]; // SMU internal use 1521} WatermarksExternal_t; 1522 1523typedef struct { 1524 uint16_t avgPsmCount[214]; 1525 uint16_t minPsmCount[214]; 1526 float avgPsmVoltage[214]; 1527 float minPsmVoltage[214]; 1528} AvfsDebugTable_t; 1529 1530typedef struct { 1531 AvfsDebugTable_t AvfsDebugTable; 1532 1533 uint32_t MmHubPadding[8]; // SMU internal use 1534} AvfsDebugTableExternal_t; 1535 1536 1537typedef struct { 1538 uint8_t Gfx_ActiveHystLimit; 1539 uint8_t Gfx_IdleHystLimit; 1540 uint8_t Gfx_FPS; 1541 uint8_t Gfx_MinActiveFreqType; 1542 uint8_t Gfx_BoosterFreqType; 1543 uint8_t PaddingGfx; 1544 uint16_t Gfx_MinActiveFreq; // MHz 1545 uint16_t Gfx_BoosterFreq; // MHz 1546 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1547 uint32_t Gfx_PD_Data_limit_a; // Q16 1548 uint32_t Gfx_PD_Data_limit_b; // Q16 1549 uint32_t Gfx_PD_Data_limit_c; // Q16 1550 uint32_t Gfx_PD_Data_error_coeff; // Q16 1551 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1552 1553 uint8_t Fclk_ActiveHystLimit; 1554 uint8_t Fclk_IdleHystLimit; 1555 uint8_t Fclk_FPS; 1556 uint8_t Fclk_MinActiveFreqType; 1557 uint8_t Fclk_BoosterFreqType; 1558 uint8_t PaddingFclk; 1559 uint16_t Fclk_MinActiveFreq; // MHz 1560 uint16_t Fclk_BoosterFreq; // MHz 1561 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1562 uint32_t Fclk_PD_Data_limit_a; // Q16 1563 uint32_t Fclk_PD_Data_limit_b; // Q16 1564 uint32_t Fclk_PD_Data_limit_c; // Q16 1565 uint32_t Fclk_PD_Data_error_coeff; // Q16 1566 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1567 1568 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1569 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1570 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1571 uint16_t Mem_Fps; 1572 uint8_t padding[2]; 1573 1574} DpmActivityMonitorCoeffInt_t; 1575 1576 1577typedef struct { 1578 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1579 uint32_t MmHubPadding[8]; // SMU internal use 1580} DpmActivityMonitorCoeffIntExternal_t; 1581 1582 1583 1584// Workload bits 1585#define WORKLOAD_PPLIB_DEFAULT_BIT 0 1586#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1587#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1588#define WORKLOAD_PPLIB_VIDEO_BIT 3 1589#define WORKLOAD_PPLIB_VR_BIT 4 1590#define WORKLOAD_PPLIB_COMPUTE_BIT 5 1591#define WORKLOAD_PPLIB_CUSTOM_BIT 6 1592#define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1593#define WORKLOAD_PPLIB_COUNT 8 1594 1595 1596// These defines are used with the following messages: 1597// SMC_MSG_TransferTableDram2Smu 1598// SMC_MSG_TransferTableSmu2Dram 1599 1600// Table transfer status 1601#define TABLE_TRANSFER_OK 0x0 1602#define TABLE_TRANSFER_FAILED 0xFF 1603#define TABLE_TRANSFER_PENDING 0xAB 1604 1605// Table types 1606#define TABLE_PPTABLE 0 1607#define TABLE_COMBO_PPTABLE 1 1608#define TABLE_WATERMARKS 2 1609#define TABLE_AVFS_PSM_DEBUG 3 1610#define TABLE_PMSTATUSLOG 4 1611#define TABLE_SMU_METRICS 5 1612#define TABLE_DRIVER_SMU_CONFIG 6 1613#define TABLE_ACTIVITY_MONITOR_COEFF 7 1614#define TABLE_OVERDRIVE 8 1615#define TABLE_I2C_COMMANDS 9 1616#define TABLE_DRIVER_INFO 10 1617#define TABLE_ECCINFO 11 1618#define TABLE_WIFIBAND 12 1619#define TABLE_COUNT 13 1620 1621//IH Interupt ID 1622#define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1623#define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1624#define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1625#define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1626#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1627#define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1628#define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1629#define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1630#define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1631 1632#endif 1633