Lines Matching refs:uint32_t
50 static void kgd_gfx_v9_lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
51 uint32_t queue, uint32_t vmid, uint32_t inst)
57 static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst)
63 void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
64 uint32_t queue_id, uint32_t inst)
66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
73 uint32_t pipe_id, uint32_t queue_id)
81 void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst)
86 void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
87 uint32_t sh_mem_config,
88 uint32_t sh_mem_ape1_base,
89 uint32_t sh_mem_ape1_limit,
90 uint32_t sh_mem_bases, uint32_t inst)
102 unsigned int vmid, uint32_t inst)
111 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
160 int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
161 uint32_t inst)
163 uint32_t mec;
164 uint32_t pipe;
180 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
184 uint32_t sdma_engine_reg_base = 0;
185 uint32_t sdma_rlc_reg_offset;
223 uint32_t pipe_id, uint32_t queue_id,
224 uint32_t __user *wptr, uint32_t wptr_shift,
225 uint32_t wptr_mask, struct mm_struct *mm,
226 uint32_t inst)
229 uint32_t *mqd_hqd;
230 uint32_t reg, hqd_base, data;
267 uint32_t queue_size =
286 (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id));
302 uint32_t pipe_id, uint32_t queue_id,
303 uint32_t doorbell_off, uint32_t inst)
307 uint32_t mec, pipe;
354 uint32_t pipe_id, uint32_t queue_id,
355 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
357 uint32_t i = 0, reg;
385 uint32_t __user *wptr, struct mm_struct *mm)
388 uint32_t sdma_rlc_reg_offset;
390 uint32_t data;
454 uint32_t engine_id, uint32_t queue_id,
455 uint32_t (**dump)[2], uint32_t *n_regs)
457 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
459 uint32_t i = 0, reg;
485 uint64_t queue_address, uint32_t pipe_id,
486 uint32_t queue_id, uint32_t inst)
488 uint32_t act;
490 uint32_t low, high;
509 uint32_t sdma_rlc_reg_offset;
510 uint32_t sdma_rlc_rb_cntl;
526 unsigned int utimeout, uint32_t pipe_id,
527 uint32_t queue_id, uint32_t inst)
531 uint32_t temp;
580 uint32_t sdma_rlc_reg_offset;
581 uint32_t temp;
618 uint32_t value;
628 uint32_t gfx_index_val,
629 uint32_t sq_cmd, uint32_t inst)
631 uint32_t data = 0;
672 uint32_t vmid,
676 uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
701 uint32_t kgd_gfx_v9_enable_debug_trap(struct amdgpu_device *adev,
703 uint32_t vmid)
724 uint32_t kgd_gfx_v9_disable_debug_trap(struct amdgpu_device *adev,
726 uint32_t vmid)
742 uint32_t trap_override,
743 uint32_t *trap_mask_supported)
759 uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct amdgpu_device *adev,
760 uint32_t vmid,
761 uint32_t trap_override,
762 uint32_t trap_mask_bits,
763 uint32_t trap_mask_request,
764 uint32_t *trap_mask_prev,
765 uint32_t kfd_dbg_cntl_prev)
767 uint32_t data, wave_cntl_prev;
793 uint32_t kgd_gfx_v9_set_wave_launch_mode(struct amdgpu_device *adev,
795 uint32_t vmid)
797 uint32_t data = 0;
818 uint32_t kgd_gfx_v9_set_address_watch(struct amdgpu_device *adev,
820 uint32_t watch_address_mask,
821 uint32_t watch_id,
822 uint32_t watch_mode,
823 uint32_t debug_vmid,
824 uint32_t inst)
826 uint32_t watch_address_high;
827 uint32_t watch_address_low;
828 uint32_t watch_address_cntl;
879 uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev,
880 uint32_t watch_id)
882 uint32_t watch_address_cntl;
905 uint32_t *wait_times,
906 uint32_t inst)
914 uint32_t vmid, uint64_t page_table_base)
953 int *wave_cnt, int *vmid, uint32_t inst)
1025 int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst)
1101 uint32_t wait_times,
1102 uint32_t grace_period,
1103 uint32_t *reg_offset,
1104 uint32_t *reg_data)
1124 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst)