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5f2c1192 |
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23-Jan-2022 |
Roy Chan <roy.chan@amd.com> |
drm/amd/display: Support synchronized indirect reg access [Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to trace. [How] Using cgs service, which provide a sync indirect reg access api. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Roy Chan <roy.chan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c1e34175 |
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17-Dec-2019 |
Noah Abradjian <noah.abradjian@amd.com> |
drm/amd/display: Indirect reg read macro with shift and mask [Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2200eb9e |
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28-Oct-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards [Why] Support for DMUB only depends on support for DC. It doesn't use floating point so we don't need to guard it by any specific DCN revision. [How] Drop the guards and cleanup the newlines around each one. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3a1627b0 |
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25-Oct-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DMUB support to DC DC will use DMUB for command submission and flow control during initialization. Register offloading as well as submitting some BIOS commands are part of the DC internal interface but are guarded behind debug options. It won't be functional in amdgpu_dm yet since we don't pass the DMUB service to DC for use. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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30eb85ff |
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15-Feb-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Combine field toggle macro and sequence write macro. [Why] field toggle write is actual field sequence write with the same field name. [How] Use REG_UPDATE_SEQ_2 for both sequence write and toggle. Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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148cccf2 |
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13-Feb-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Refactor reg_set and reg_update. [Why] Current reg update and reg set use same functions and only delta is update reads reg value and call update function. [How] Refactor reg update and reg set functions. 1.Implement different functions for reg update and reg set. 2.Wrap same process to a help function, both reg update and reg set will call it. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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16aecfd4 |
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16-Jun-2018 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: generic indirect register access add generic indirect register access following our register access pattern this will make it easier to review code and programming sequence, with all the complexity hidden in macro Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0a93dc7f |
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29-Mar-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: add rq/dlg/ttu to dtn log Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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daf6b57d |
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11-Jul-2017 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: add line number to reg_wait timeout print Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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184debdb |
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05-Jul-2017 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: refactor dcn10 hw_sequencer to new reg access style Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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50db413d |
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23-Apr-2017 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: clarify delay param for REG_WAIT Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cb9a5a90 |
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15-Dec-2016 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: define reg helpers to update registers with 8 and 9 fields Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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98d2cc2b |
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12-Dec-2016 |
Andrew Wong <andrew.wong1@amd.com> |
drm/amd/display: Change locking of registers when flipping frames. - Introduce GRPH_UPDATE_LOCK around programming surface flip. - Remove the now unused graphic surface lock. - Add macros to get and set four registers - both immediate and H Retrace should not be enabled at the same time Signed-off-by: Andrew Wong <andrew.wong1@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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22f050be |
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30-Nov-2016 |
Roman Li <Roman.Li@amd.com> |
drm/amd/display: fix REG_SET_5 macro Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4562236b |
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12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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