Lines Matching refs:uint32_t
376 uint32_t Spare[8];
377 uint32_t MmHubPadding[8]; // SMU internal use
387 uint32_t eccPadding;
416 uint32_t a; // store in IEEE float format in this variable
417 uint32_t b; // store in IEEE float format in this variable
418 uint32_t c; // store in IEEE float format in this variable
422 uint32_t m; // store in IEEE float format in this variable
423 uint32_t b; // store in IEEE float format in this variable
427 uint32_t a; // store in IEEE float format in this variable
428 uint32_t b; // store in IEEE float format in this variable
429 uint32_t c; // store in IEEE float format in this variable
507 uint32_t Padding3[3];
696 uint32_t FeatureCtrlMask;
701 uint32_t Reserved;
725 uint32_t Spare[13];
726 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
735 uint32_t FeatureCtrlMask;
762 uint32_t Spare[13];
854 uint32_t InitVcoFreqPll0;
855 uint32_t InitVcoFreqPll1;
856 uint32_t InitVcoFreqPll2;
857 uint32_t InitVcoFreqPll3;
858 uint32_t InitVcoFreqPll4;
859 uint32_t InitVcoFreqPll5;
860 uint32_t InitVcoFreqPll6;
869 uint32_t Spare[8];
900 uint32_t Spare[11];
912 uint32_t Reserved[4];
941 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)
944 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
977 uint32_t FitControllerFailureRateLimit; //in IEEE float
979 uint32_t FitControllerGfxDutyCycle; // in IEEE float
981 uint32_t FitControllerSocDutyCycle; // in IEEE float
984 uint32_t FitControllerSocOffset; //in IEEE float
986 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value
989 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping
992 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping
1020 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM
1022 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM
1024 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN
1026 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN
1035 uint32_t SpareVmin[9];
1053 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
1080 uint32_t GfxOffEntryHysteresis;
1081 uint32_t GfxoffSpare[15];
1084 uint32_t DfllBtcMasterScalerM;
1086 uint32_t DfllBtcSlaveScalerM;
1089 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg
1090 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg
1092 uint32_t DfllL2FrequencyBoostM; //Unitless (float)
1093 uint32_t DfllL2FrequencyBoostB; //In MHz (integer)
1094 uint32_t GfxGpoSpare[8];
1104 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1111 uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation
1112 uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation
1114 uint32_t DcsSpare[11];
1153 uint32_t TempInputSelectMask;
1179 uint32_t FanSpare[13];
1186 uint32_t L2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding
1187 uint32_t SeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];
1189 uint32_t CommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];
1191 uint32_t L2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1192 uint32_t SeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1194 uint32_t Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];
1195 uint32_t Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];
1196 uint32_t Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];
1197 uint32_t Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];
1199 uint32_t Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];
1201 uint32_t dGbV_dT_vmin;
1202 uint32_t dGbV_dT_vmax;
1205 uint32_t V2F_vmin_range_low;
1206 uint32_t V2F_vmin_range_high;
1207 uint32_t V2F_vmax_range_low;
1208 uint32_t V2F_vmax_range_high;
1212 uint32_t GfxAvfsSpare[32];
1230 uint32_t SocAvfsSpare[32];
1244 uint32_t reserved[22];
1247 uint32_t DebugOverrides;
1269 uint32_t Spare[41];
1272 uint32_t MmHubPadding[8];
1278 uint32_t Version; //should be unique to each board type
1304 uint32_t VoltageTelemetryRatio[SVI_PLANE_COUNT]; // This is used for VDDIO Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
1356 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued
1357 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS
1363 uint32_t BoardSpare[63];
1368 uint32_t MmHubPadding[8];
1393 uint32_t Spare[8];
1395 uint32_t MmHubPadding[8]; // SMU internal use
1417 uint32_t Spare[32];
1420 uint32_t MmHubPadding[8]; // SMU internal use
1425 uint32_t CurrClock[PPCLK_COUNT];
1442 uint32_t MetricsCounter;
1452 uint32_t EnergyAccumulator;
1472 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
1473 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
1474 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
1482 uint32_t PublicSerialNumberLower;
1483 uint32_t PublicSerialNumberUpper;
1489 uint32_t Spare[29];
1492 uint32_t MmHubPadding[8]; // SMU internal use
1518 uint32_t Spare[16];
1520 uint32_t MmHubPadding[8]; // SMU internal use
1533 uint32_t MmHubPadding[8]; // SMU internal use
1547 uint32_t Gfx_PD_Data_limit_a; // Q16
1548 uint32_t Gfx_PD_Data_limit_b; // Q16
1549 uint32_t Gfx_PD_Data_limit_c; // Q16
1550 uint32_t Gfx_PD_Data_error_coeff; // Q16
1551 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
1562 uint32_t Fclk_PD_Data_limit_a; // Q16
1563 uint32_t Fclk_PD_Data_limit_b; // Q16
1564 uint32_t Fclk_PD_Data_limit_c; // Q16
1565 uint32_t Fclk_PD_Data_error_coeff; // Q16
1566 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16
1568 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1579 uint32_t MmHubPadding[8]; // SMU internal use