#
285830 |
|
23-Jul-2015 |
gjb |
- Copy stable/10@285827 to releng/10.2 in preparation for 10.2-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.2. - Update default pkg(8) configuration to use the quarterly branch.[1]
Discussed with: re, portmgr [1] Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
284900 |
|
28-Jun-2015 |
neel |
MFC r282209: Emulate the 'bit test' instruction.
MFC r282259: Re-implement RTC current time calculation to eliminate the possibility of losing time.
MFC r282281: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.
MFC r282284: When an instruction cannot be decoded just return to userspace so bhyve(8) can dump the instruction bytes.
MFC r282287: Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.
MFC r282296: Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are enabled.
MFC r282301: Relax limits when transitioning a vector from the IRR to the ISR and also when extinguishing it from the ISR in response to an EOI.
MFC r282335: Advertise an additional memory BAR in the "dummy" device emulation.
MFC r282336: Emulate machine check related MSRs to allow guest OSes like Windows to boot.
MFC r282351: Don't advertise the Intel SMX capability to the guest.
MFC r282407: Emulate the 'CMP r/m8, imm8' instruction.
MFC r282519: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE.
MFC r282520: Emulate guest writes to EFER_MSR properly.
MFC r282558: Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup().
MFC r282571: Check 'td_owepreempt' and yield the vcpu thread if it is set.
MFC r282595: Allow byte reads of AHCI registers.
MFC r282784: Handling indirect descriptors is a capability of the host and not one that needs to be negotiated. Use the host capabilities field and not the negotiated field when verifying that indirect descriptors are supported.
MFC r282788: Allow configuration of the sector size advertised to the guest.
MFC r282865: Set the subvendor field in config space to the vendor ID. This is required by the Windows virtio drivers to correctly match a device.
MFC r282922: Bump the size of the blockif scatter-gather list to 67.
MFC r283075: Fix off-by-one in array index bounds check. bhyveload would allow you to create 33 entries on an array that only has 32 slots
MFC r283168: Temporarily revert r282922 which bumped the max descriptors.
MFC r283255: Emulate the "CMP r/m, reg" instruction (opcode 39H).
MFC r283256: Add an option "--get-vmcs-exit-inst-length" to display the instruction length of the instruction that caused the VM-exit.
MFC r283264: Change the header type of the emulated host-bridge from type 1 to type 0.
MFC r283293: Don't rely on the 'VM-exit instruction length' field in the VMCS to always have an accurate length on an EPT violation.
MFC r283299: Remove bogus verification of instruction length after instruction decode.
MFC r283308: Exceptions don't deliver an error code in real mode.
MFC r283657: Fix non-deterministic delays when accessing a vcpu that was in "running" or "sleeping" state.
MFC r283973: Use tunable 'hw.vmm.svm.features' to disable specific SVM features even though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids' to limit the number of ASIDs used by the hypervisor.
MFC r284046: Fix regression in 'verify_gla()' with the RIP-relative addressing mode.
MFC r284174: Support guest writes to the TSC by enabling the "use TSC offsetting" execution control.
|
#
276386 |
|
30-Dec-2014 |
neel |
MFC 261321 Rename the AMD MSR_PERFCTR[0-3] so the Pentium Pro MSR_PERFCTR[0-1] aren't redefined.
MFC r273214 Fix build to not bogusly always rebuild vmm.ko.
MFC r273338 Add support for AMD's nested page tables in pmap.c: - Provide the correct bit mask for various bit fields in a PTE (e.g. valid bit) for a pmap of type PT_RVI. - Add a function 'pmap_type_guest(pmap)' that returns TRUE if the pmap is of type PT_EPT or PT_RVI.
Add CPU_SET_ATOMIC_ACQ(num, cpuset): This is used when activating a vcpu in the nested pmap. Using the 'acquire' variant guarantees that the load of the 'pm_eptgen' will happen only after the vcpu is activated in 'pm_active'.
Add defines for various AMD-specific MSRs.
Discussed with: kib (r261321)
|
#
276349 |
|
28-Dec-2014 |
neel |
MFC r270326 Fix a recursive lock acquisition in vi_reset_dev().
MFC r270434 Return the spurious interrupt vector (IRQ7 or IRQ15) if the atpic cannot find any unmasked pin with an interrupt asserted.
MFC r270436 Fix a bug in the emulation of CPUID leaf 0x4.
MFC r270437 Add "hw.vmm.topology.threads_per_core" and "hw.vmm.topology.cores_per_package" tunables to modify the default cpu topology advertised by bhyve.
MFC r270855 Set the 'inst_length' to '0' early on before any error conditions are detected in the emulation of the task switch. If any exceptions are triggered then the guest %rip should point to instruction that caused the task switch as opposed to the one after it.
MFC r270857 The "SUB" instruction used in getcc() actually does 'x -= y' so use the proper constraint for 'x'. The "+r" constraint indicates that 'x' is an input and output register operand.
While here generate code for different variants of getcc() using a macro GETCC(sz) where 'sz' indicates the operand size.
Update the status bits in %rflags when emulating AND and OR opcodes.
MFC r271439 Initialize 'bc_rdonly' to the right value.
MFC r271451 Optimize the common case of injecting an interrupt into a vcpu after a HLT by explicitly moving it out of the interrupt shadow.
MFC r271888 Restructure the MSR handling so it is entirely handled by processor-specific code.
MFC r271890 MSR_KGSBASE is no longer saved and restored from the guest MSR save area. This behavior was changed in r271888 so update the comment block to reflect this.
MFC r271891 Add some more KTR events to help debugging.
MFC r272197 mmap(2) requires either MAP_PRIVATE or MAP_SHARED for non-anonymous mappings.
MFC r272395 Get rid of code that dealt with the hardware not being able to save/restore the PAT MSR on guest exit/entry. This workaround was done for a beta release of VMware Fusion 5 but is no longer needed in later versions.
All Intel CPUs since Nehalem have supported saving and restoring MSR_PAT in the VM exit and entry controls.
MFC r272670 Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT'.
MFC r272710 Implement the FLUSH operation in the virtio-block emulation.
MFC r272838 iasl(8) expects integer fields in data tables to be specified as hexadecimal values. Therefore the bit width of the "PM Timer Block" was actually being interpreted as 50-bits instead of the expected 32-bit.
This eliminates an error message emitted by a Linux 3.17 guest during boot: "Invalid length for FADT/PmTimerBlock: 50, using default 32"
MFC r272839 Support Intel-specific MSRs that are accessed when booting up a linux in bhyve: - MSR_PLATFORM_INFO - MSR_TURBO_RATIO_LIMITx - MSR_RAPL_POWER_UNIT
MFC r273108 Emulate "POP r/m". This is needed to boot OpenBSD/i386 MP kernel in bhyve.
MFC r273212 Support stopping and restarting the AHCI command list via toggling PxCMD.ST from '1' to '0' and back. This allows the driver a chance to recover if for instance a timeout occurred due to activity on the host.
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#
276134 |
|
23-Dec-2014 |
kib |
MFC r271208: Add a define for index of IA32_XSS MSR.
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#
276132 |
|
23-Dec-2014 |
kib |
MFC r271197: Add more bits for the XSAVE features from CPUID 0xd, sub-function 1 %eax report. Print the XSAVE features 0xd/1 in the boot banner.
|
#
270159 |
|
19-Aug-2014 |
grehan |
MFC r267921, r267934, r267949, r267959, r267966, r268202, r268276, r268427, r268428, r268521, r268638, r268639, r268701, r268777, r268889, r268922, r269008, r269042, r269043, r269080, r269094, r269108, r269109, r269281, r269317, r269700, r269896, r269962, r269989.
Catch bhyve up to CURRENT.
Lightly tested with FreeBSD i386/amd64, Linux i386/amd64, and OpenBSD/amd64. Still resolving an issue with OpenBSD/i386.
Many thanks to jhb@ for all the hard work on the prior MFCs !
r267921 - support the "mov r/m8, imm8" instruction r267934 - document options r267949 - set DMI vers/date to fixed values r267959 - doc: sort cmd flags r267966 - EPT misconf post-mortem info r268202 - use correct flag for event index r268276 - 64-bit virtio capability api r268427 - invalidate guest TLB when cr3 is updated, needed for TSS r268428 - identify vcpu's operating mode r268521 - use correct offset in guest logical-to-linear translation r268638 - chs value r268639 - chs fake values r268701 - instr emul operand/address size override prefix support r268777 - emulation for legacy x86 task switching r268889 - nested exception support r268922 - fix INVARIANTS build r269008 - emulate instructions found in the OpenBSD/i386 5.5 kernel r269042 - fix fault injection r269043 - Reduce VMEXIT_RESTARTs in task_switch.c r269080 - fix issues in PUSH emulation r269094 - simplify return values from the inout handlers r269108 - don't return -1 from the push emulation handler r269109 - avoid permanent sleep in vm_handle_hlt() r269281 - list VT-x features in base kernel dmesg r269317 - Mark AHCI fatal errors as not completed r269700 - Support PCI extended config space in bhyve r269896 - Minor cleanup r269962 - use max guest memory when creating IOMMU domain r269989 - fix interrupt mode names
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#
267418 |
|
12-Jun-2014 |
jhb |
MFC 266263,266551,266552: - Add definitions for more structured extended features as well as XSAVE Extended Features for AVX512 and MPX (Memory Protection Extensions). - Don't permit users to request a subset of the AVX512 or MPX xsave masks.
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#
258159 |
|
15-Nov-2013 |
kib |
MFC r257856: Add bits for the AMD features from CPUID function 0x80000001 ECX, described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf.
Approved by: re (gjb)
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#
256281 |
|
10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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#
253747 |
|
28-Jul-2013 |
avg |
x86: detect mwait capabilities and extensions, when present
Reviewed by: kib (earlier amd64-only version) MFC after: 2 weeks
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#
249608 |
|
18-Apr-2013 |
rpaulo |
Move the previously added CPUID7 macros to CPUID_STDEXT.
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#
249602 |
|
18-Apr-2013 |
rpaulo |
Add the most current CPUID7_* definitions.
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#
249351 |
|
11-Apr-2013 |
neel |
Make the code to check if VMX is enabled more readable by using macros instead of magic numbers.
Discussed with: Chris Torek
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#
245055 |
|
05-Jan-2013 |
neel |
Add macros required to enable VMX operation on Intel processors.
Obtained from: NetApp
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#
242432 |
|
01-Nov-2012 |
kib |
Provide the reading and display of the Standard Extended Features, introduced with the IvyBridge CPUs. Provide the definitions for new bits in CR3 and CR4 registers.
Tested by: avg, Michael Moll <kvedulv@kvedulv.de> MFC after: 2 weeks
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#
238450 |
|
14-Jul-2012 |
kib |
Add support for the XSAVEOPT instruction use. Our XSAVE/XRSTOR usage mostly meets the guidelines set by the Intel SDM: 1. We use XRSTOR and XSAVE from the same CPL using the same linear address for the store area 2. Contrary to the recommendations, we cannot zero the FPU save area for a new thread, since fork semantic requires the copy of the previous state. This advice seemingly contradicts to the advice from the item 6. 3. We do use XSAVEOPT in the context switch code only, and the area for XSAVEOPT already always contains the data saved by XSAVE. 4. We do not modify the save area between XRSTOR, when the area is loaded into FPU context, and XSAVE. We always spit the fpu context into save area and start emulation when directly writing into FPU context. 5. We do not use segmented addressing to access save area, or rather, always address it using %ds basing. 6. XSAVEOPT can be only executed in the area which was previously loaded with XRSTOR, since context switch code checks for FPU use by outgoing thread before saving, and thread which stopped emulation forcibly get context loaded with XRSTOR. 7. The PCB cannot be paged out while FPU emulation is turned off, since stack of the executing thread is never swapped out.
The context switch code is patched to issue XSAVEOPT instead of XSAVE if supported. This approach eliminates one conditional in the context switch code, which would be needed otherwise.
For user-visible machine context to have proper data, fpugetregs() checks for unsaved extension blocks and manually copies pristine FPU state into them, according to the description provided by CPUID leaf 0xd.
MFC after: 1 month
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#
234364 |
|
17-Apr-2012 |
grehan |
Add x2apic MSR definitions
Reviewed by: jhb Obtained from: bhyve via Neel via NetApp
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#
234059 |
|
09-Apr-2012 |
jhb |
Recognize the RDRAND instruction feature.
Submitted by: Michael Fuckner michael fuckner net MFC after: 3 days
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#
233207 |
|
19-Mar-2012 |
tijl |
Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replace amd64/i386/pc98 specialreg.h with stubs.
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#
230261 |
|
17-Jan-2012 |
kib |
Add definitions related to XCR0.
MFC after: 1 week
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#
222043 |
|
17-May-2011 |
jkim |
Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel AVX instructions. The SSE5 bit was recycled as XOP extended instruction bit, CVT16 was deprecated in favor of F16C (half-precision float conversion instructions for AVX), and the remaining FMA4 (4-operand FMA instructions) gained a separate CPUID bit. Replace non-existent references with today's CPUID specifications.
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#
221527 |
|
06-May-2011 |
avg |
prepare code that does topology detection for amd cpus for bulldozer
This also introduces a new detection path for family 10h and newer pre-bulldozer cpus, pre-10h hardware should not be affected.
Tested by: Gary Jennejohn <gljennjohn@googlemail.com> (with pre-10h hardware) MFC after: 2 weeks
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#
221188 |
|
28-Apr-2011 |
jkim |
Define "Hypervisor Present" bit. This bit is used by several hypervisors to identify CPUs running under emulation. Currently QEMU-KVM, Xen-HVM, VMware, and MS Hyper-V are known to set this bit.
MFC after: 3 days
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#
220578 |
|
12-Apr-2011 |
jkim |
Add definitions for CPUID instruction 6, ECX information.
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#
215748 |
|
23-Nov-2010 |
avg |
specialreg.h: add definitions for some useful bits found in CPUID.6 EAX and ECX
CPUID.6 is defined as Thermal and Power Management Leaf by both Intel and AMD.
Reviewed by: jhb MFC after: 7 days
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#
215524 |
|
19-Nov-2010 |
avg |
specialreg.h: add definitions for MPERF/APERF pair of MSRs
These MSRs can be used to determine actual (average) performance as compared to a maximum defined performance. Availability of these MSRs is indicated by bit0 in CPUID.6.ECX on both Intel and AMD processors.
MFC after: 5 days
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#
215523 |
|
19-Nov-2010 |
avg |
specialreg.h: add AMD-specific "Hardware Configuration Register" MSR
It seems that this MSR has been available in a range of AMD processors families for quite a while now.
Note1: not all AMD MSRs that are found in amd64 specialreg.h are also in the i386 version. Note2: perhaps some additional name component is needed to distinguish AMD-specific MSRs.
MFC after: 5 days
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#
215522 |
|
19-Nov-2010 |
avg |
specialreg.h: add definition for AMD Core Performance Boost bit
This bit indicates availability of the feature.
MFC after: 4 days
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#
213452 |
|
05-Oct-2010 |
kib |
Display PCID capability of CPU and add CPUID define for it.
MFC after: 1 week
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#
210624 |
|
29-Jul-2010 |
delphij |
Improve cputemp(4) driver wrt newer Intel processors, especially Xeon 5500/5600 series:
- Utilize IA32_TEMPERATURE_TARGET, a.k.a. Tj(target) in place of Tj(max) when a sane value is available, as documented in Intel whitepaper "CPU Monitoring With DTS/PECI"; (By sane value we mean 70C - 100C for now); - Print the probe results when booting verbose; - Replace cpu_mask with cpu_stepping; - Use CPUID_* macros instead of rolling our own.
Approved by: rpaulo MFC after: 1 month
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#
210577 |
|
28-Jul-2010 |
jhb |
The corrected error count field is dependent on CMCI, not TES.
MFC after: 1 week
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#
208507 |
|
24-May-2010 |
jhb |
Add support for corrected machine check interrupts. CMCI is a new local APIC interrupt that fires when a threshold of corrected machine check events is reached. CMCI also includes a count of events when reporting corrected errors in the bank's status register. Note that individual banks may or may not support CMCI. If they do, each bank includes its own threshold register that determines when the interrupt fires. Currently the code uses a very simple strategy where it doubles the threshold on each interrupt until it succeeds in throttling the interrupt to occur only once a minute (this interval can be tuned via sysctl). The threshold is also adjusted on each hourly poll which will lower the threshold once events stop occurring.
Tested by: Sailaja Bangaru sbappana at yahoo com MFC after: 1 month
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#
207676 |
|
05-May-2010 |
kib |
Add definitions for Intel AESNI CPUID bits and print the capabilities on boot.
Hardware provided by: Sentex Communications MFC after: 1 week
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#
205573 |
|
24-Mar-2010 |
alc |
Adapt r204907 and r205402, the amd64 implementation of the workaround for AMD Family 10h Erratum 383, to i386.
Enable machine check exceptions by default, just like r204913 for amd64.
Enable superpage promotion only if the processor actually supports large pages, i.e., PG_PS.
MFC after: 2 weeks
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#
205448 |
|
22-Mar-2010 |
jhb |
Remove unneeded type specifiers from 64-bit constants. The compiler infers their natural type from the constants' values.
Submitted by: bde MFC after: 3 days
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#
205214 |
|
16-Mar-2010 |
jhb |
- Extend the machine check record structure to include several fields useful for parsing model-specific and other fields in machine check events including the global machine check capabilities and status registers, CPU identification, and the FreeBSD CPU ID. - Report these added fields in the console log of a machine check so that a record structure can be reconstituted from the console messages. - Parse new architectural errors including memory controller errors.
MFC after: 1 week
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#
205210 |
|
16-Mar-2010 |
jhb |
Use unsigned long long constants for fields in 64-bit machine check registers instead of unsigned long constants.
MFC after: 3 days
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#
199968 |
|
30-Nov-2009 |
avg |
x86 cpu features: add MOVBE reporting and flag
The check is glimpsed from Linux and OpenSolaris. MOVBE instruction is found in Intel Atom processors.
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#
197070 |
|
10-Sep-2009 |
jkim |
Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them.
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#
194295 |
|
16-Jun-2009 |
jhb |
Move (read|write)_cyrix_reg() inlines from specialreg.h to cpufunc.h. specialreg.h now consists solely of register-related macros.
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#
192050 |
|
13-May-2009 |
jhb |
Implement simple machine check support for amd64 and i386. - For CPUs that only support MCE (the machine check exception) but not MCA (i.e. Pentium), all this does is print out the value of the machine check registers and then panic when a machine check exception occurs. - For CPUs that support MCA (the machine check architecture), the support is a bit more involved. - First, there is limited support for decoding the CPU-independent MCA error codes in the kernel, and the kernel uses this to output a short description of any machine check events that occur. - When a machine check exception occurs, all of the MCx banks on the current CPU are scanned and any events are reported to the console before panic'ing. - To catch events for correctable errors, a periodic timer kicks off a task which scans the MCx banks on all CPUs. The frequency of these checks is controlled via the "hw.mca.interval" sysctl. - Userland can request an immediate scan of the MCx banks by writing a non-zero value to "hw.mca.force_scan". - If any correctable events are encountered, the appropriate details are stored in a 'struct mca_record' (defined in <machine/mca.h>). The "hw.mca.count" is a count of such records and each record may be queried via the "hw.mca.records" tree by specifying the record index (0 .. count - 1) as the next name in the MIB similar to using PIDs with the kern.proc.* sysctls. The idea is to export machine check events to userland for more detailed processing. - The periodic timer and hw.mca sysctls are only present if the CPU supports MCA.
Discussed with: emaste (briefly) MFC after: 1 month
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#
191648 |
|
29-Apr-2009 |
jeff |
- Add support for cpuid leaf 0xb. This allows us to determine the topology of nehalem/corei7 based systems. - Remove the cpu_cores/cpu_logical detection from identcpu. - Describe the layout of the system in cpu_mp_announce().
Sponsored by: Nokia
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#
186009 |
|
12-Dec-2008 |
jkim |
Add more CPUID bits from AMD CPUID Specification Rev. 2.28.
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#
185341 |
|
26-Nov-2008 |
jkim |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by: jhb, peter (early amd64 version)
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#
184146 |
|
22-Oct-2008 |
jkim |
Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher even if BIOS does not advertise it.
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#
184101 |
|
21-Oct-2008 |
jkim |
Detect Advanced Power Management Information for AMD CPUs.
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#
183128 |
|
17-Sep-2008 |
jhb |
MFamd64: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB large pages.
MFC after: 1 month
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#
181430 |
|
08-Aug-2008 |
stas |
- Add cpuctl(4) pseudo-device driver to provide access to some low-level features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpucontrol(8) utility, that provides userland access to the features of cpuctl(4). - Add subsequent manpages.
The cpuctl(4) device operates as follows. The pseudo-device node cpuctlX is created for each cpu present in the systems. The pseudo-device minor number corresponds to the cpu number in the system. The cpuctl(4) pseudo- device allows a number of ioctl to be preformed, namely RDMSR/WRMSR/CPUID and UPDATE. The first pair alows the caller to read/write machine-specific registers from the correspondent CPU. cpuid data could be retrieved using the CPUID call, and microcode updates are applied via UPDATE.
The permissions are inforced based on the pseudo-device file permissions. RDMSR/CPUID will be allowed when the caller has read access to the device node, while WRMSR/UPDATE will be granted only when the node is opened for writing. There're also a number of priv(9) checks.
The cpucontrol(8) utility is intened to provide userland access to the cpuctl(4) device features. The utility also allows one to apply cpu microcode updates.
Currently only Intel and AMD cpus are supported and were tested.
Approved by: kib Reviewed by: rpaulo, cokane, Peter Jeremy MFC after: 1 month
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#
177125 |
|
12-Mar-2008 |
jhb |
The variable MTRR registers actually have variable-sized PhysBase and PhysMask fields based on the number of physical address bits supported by the current CPU. The old code assumed 36 bits on i386 and 40 bits on amd64. In truth, all Intel CPUs up until recently used 36 bits (a newer Intel CPU uses 38 bits) and all the Opteron CPUs used 40 bits.
In at least one case (the new Intel CPU) having the size of the mask field wrong resulted in writing questionable values into the MTRR registers on the application processors (BSP as well if you modify the MTRRs via memcontrol or running X, etc.). The result of the questionable physmask was that all of memory was apparently treated as uncached rather than write-back resulting in a very significant performance hit.
Fix this by constructing a run-time mask for the PhysBase and PhysMask fields based on the number of physical address bits supported by the CPU. All 64-bit capable CPUs provide a count of PA bits supported via the 0x80000008 extended CPUID feature, so use that if it is available. If that feature is not available, then assume 36 PA bits.
While I'm here, expand the (now-unused) macros for the PhysBase and PhysMask fields to the current largest possible value (52 PA bits).
MFC after: 1 week PR: i386/120516 Reported by: Nokia
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#
177069 |
|
11-Mar-2008 |
jhb |
Add constants for the various fields in MTRR registers.
MFC after: 1 week Verified by: md5(1)
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#
171854 |
|
15-Aug-2007 |
des |
Add a driver for the on-die digital thermal sensor found on Intel Core and newer CPUs (including Core 2 and Core / Core 2 based Xeons). The driver attaches to each cpu device and creates a sysctl node in that device's sysctl context (dev.cpu.N.temperature). When invoked, the handler binds to the appropriate CPU to ensure a correct reading.
Submitted by: Rui Paulo <rpaulo@fnop.net> Sponsored by: Google Summer of Code 2007 Tested by: des, marcus, Constantine A. Murenin, Ian FREISLICH Approved by: re (kensmith) MFC after: 3 weeks
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#
170150 |
|
31-May-2007 |
des |
Add CPUID2_PDCM
Requested by: jkim MFC after: 3 days
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#
168439 |
|
06-Apr-2007 |
ru |
Add the PG_NX support for i386/PAE.
Reviewed by: alc
|
#
167744 |
|
20-Mar-2007 |
jkim |
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name in comment.
|
#
167493 |
|
12-Mar-2007 |
jkim |
Add another CPUID for AMD CPUs and fix style(9) while I am here.
|
#
165918 |
|
09-Jan-2007 |
jkim |
Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.
|
#
160329 |
|
13-Jul-2006 |
jkim |
Sync specialreg.h changes between amd64 and i386 with few fixes.
|
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160305 |
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12-Jul-2006 |
mr |
fix typo in identcpu.c and add one define to specialreg.h.
MFC after: 1 week
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160298 |
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12-Jul-2006 |
mr |
First step to identify and initialize the newer VIA C7 CPU as found in a VIA EPIA EN-15000 board.
Obtained from: large parts from OpenBSD
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160286 |
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12-Jul-2006 |
jkim |
Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.
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159768 |
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19-Jun-2006 |
davidxu |
Style fix, use low-case.
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159763 |
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19-Jun-2006 |
davidxu |
Clear bit 22 in MSR IA32_MISC_ENABLE, according to Intel document, when the bit 22 is set to 1, CPUID with EAX=0 returns a maximum value in EAX[7..0] of 3, when set to 0(default), CPUID with EAX=0 returns the number corresponding to the maximum standard function supported. On my machine, BIOS sets the bit to 1 to make it to be compatible with old OS, this causes dual-core Pentium-D (two physical cores) to be identified as hyperthreading (two logical cores) by function mp_topology().
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158238 |
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01-May-2006 |
jhb |
Add various constants for the PAT MSR and the PAT PTE and PDE flags. Initialize the PAT MSR during boot to map PAT type 2 to Write-Combining (WC) instead of Uncached (UC-).
MFC after: 1 month
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151348 |
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14-Oct-2005 |
jkim |
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use.
Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2.
Approved by: anholt (mentor)
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128019 |
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07-Apr-2004 |
imp |
Remove advertising clause from University of California Regent's license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson.
Approved by: core, peter, alc, rwatson
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124685 |
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18-Jan-2004 |
sobomax |
Add new CPU_ENABLE_TCC option, from NOTES:
CPU_ENABLE_TCC enables Thermal Control Circuitry (TCC) found in some Pentium(tm) 4 and (possibly) later CPUs. When enabled and detected, TCC allows to restrict power consumption by using machdep.cpuperf* sysctls. This operates independently of SpeedStep and is useful on systems where other mechanisms such as apm(4) or acpi(4) don't work.
Given the fact that many, even modern, notebooks don't work properly with Intel ACPI, this is indeed very useful option for notebook owners.
Obtained from: OpenBSD MFC after: 2 weeks
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118954 |
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15-Aug-2003 |
jhb |
- Add macros describing some new MSR's in the Pentium 4 and some older MSR's in the original Pentium. - Add macros describing the bit fields in the APICBASE MSR.
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114376 |
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01-May-2003 |
peter |
<b30> is 'IA64' - ie: you're running on an ia64 in 32 bit mode.
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109691 |
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22-Jan-2003 |
jhb |
Bah, add in a missing space char I noticed when MFC'ing this.
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108909 |
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08-Jan-2003 |
jhb |
- Fix the name of the hyperthreading cpuid feature flag to be HTT instead of HHT. - Document fields returned in %ebx by a cpuid with %eax of 1.
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98650 |
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22-Jun-2002 |
mp |
Add additional cpuid feature flags and put into a canonical format.
MFC after: 1 week
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79609 |
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12-Jul-2001 |
peter |
Activate SSE/SIMD. This is the extra context switching support that we are required to do if we let user processes use the extra 128 bit registers etc.
This is the base part of the diff I got from: http://www.issei.org/issei/FreeBSD/sse.html I believe this is by: Mr. SUZUKI Issei <issei@issei.org> SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp> Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see http://kobe1995.net/~kaz/FreeBSD/SSE.en.html
I have fixed a couple of style(9) deviations. I have some followup commits to fix a couple of non-style things.
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51127 |
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10-Sep-1999 |
peter |
Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during context switching and also enables SIMD since this enables saving the extra CPU context that isn't saved with normal FPU regs. The other enables the SIMD instructions to use exception 16 (FPU) error reporting. Note, this doesn't turn on SIMD, just defines the bits.
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50477 |
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28-Aug-1999 |
peter |
$Id$ -> $FreeBSD$
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45406 |
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07-Apr-1999 |
msmith |
Add defines for the P6 model-specific registers.
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40003 |
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06-Oct-1998 |
kato |
- Implement enabling write allocate on AMD K5/K6/K6-2 cpus. The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>. - Fix stylistic bug in identcpu.c. - Update copyright in initcpu.c - Fix typo in LINT.
PR: 6269 and 6270
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34031 |
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04-Mar-1998 |
kato |
Defined CCR6 and CCR7 (configuration registers of M2 CPU.)
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27591 |
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21-Jul-1997 |
fsmp |
Enabled the FPU emilaute bit define: CR0_EM
Reviewed by: Bruce Evans <bde@zeta.org.au>
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24112 |
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22-Mar-1997 |
kato |
Improved CPU identification and initialization routines. This supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD) Nx586 CPU, and initialize special registers of Cyrix CPU and msr of IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in write-through mode. This can be disabled by kernel configuration options.
Reviewed by: Bruce Evans <bde@freebsd.org> and Jordan K. Hubbard <jkh@freebsd.org>
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22975 |
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22-Feb-1997 |
peter |
Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not ready for it yet.
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21673 |
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14-Jan-1997 |
jkh |
Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
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19621 |
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11-Nov-1996 |
dyson |
Support the PG_G flag on Pentium-Pro processors. This pretty much eliminates the unnecessary unmapping of the kernel during context switches and during invtlb...
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16100 |
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03-Jun-1996 |
sos |
Added missing CR0_NW define for Cyrix 486DLC support. It's still not stable on my hardware, but its better... *sigh*
Obtained from: NetBSD
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13765 |
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30-Jan-1996 |
mpp |
Fix a bunch of spelling errors in the comment fields of a bunch of system include files.
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8876 |
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30-May-1995 |
rgrimes |
Remove trailing whitespace.
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5594 |
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14-Jan-1995 |
bde |
Enable define of CR0_AM to prepare for implementing alignment checking.
Uniformize idempotency ifdef.
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2497 |
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04-Sep-1994 |
dg |
Improved some comments.
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2495 |
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04-Sep-1994 |
pst |
Detect if we're running on a Cyrix 486DLC and enable automatic cache negation whenever we access memory between 640k and 1M.
Original code from NetBSD 1.0-BETA. The exact origins are unclear but Theo de Raadt, Charles, and Michael V. may have contributed to it.
Submitted by: pst
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719 |
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07-Nov-1993 |
wollman |
Made all header files idempotent and moved incorrect common data from headers into a related source file. Added cons.h as first step towards moving i386/i386/cons.h to machine/cons.h where it belongs.
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621 |
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16-Oct-1993 |
rgrimes |
Removed all patch kit headers, sccsid and rcsid strings, put $Id$ in, some minor cleanup. Added $Id$ to files that did not have any version info, etc
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5 |
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12-Jun-1993 |
rgrimes |
This commit was generated by cvs2svn to compensate for changes in r4, which included commits to RCS files with non-trunk default branches.
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4 |
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12-Jun-1993 |
rgrimes |
Initial import, 0.1 + pk 0.2.4-B1
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