specialreg.h revision 183128
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/i386/include/specialreg.h 183128 2008-09-17 20:45:18Z jhb $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55/* 56 * Bits in PPro special registers 57 */ 58#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60#define CR4_TSD 0x00000004 /* Time stamp disable */ 61#define CR4_DE 0x00000008 /* Debugging extensions */ 62#define CR4_PSE 0x00000010 /* Page size extensions */ 63#define CR4_PAE 0x00000020 /* Physical address extension */ 64#define CR4_MCE 0x00000040 /* Machine check enable */ 65#define CR4_PGE 0x00000080 /* Page global enable */ 66#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70/* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74 75/* 76 * CPUID instruction features register 77 */ 78#define CPUID_FPU 0x00000001 79#define CPUID_VME 0x00000002 80#define CPUID_DE 0x00000004 81#define CPUID_PSE 0x00000008 82#define CPUID_TSC 0x00000010 83#define CPUID_MSR 0x00000020 84#define CPUID_PAE 0x00000040 85#define CPUID_MCE 0x00000080 86#define CPUID_CX8 0x00000100 87#define CPUID_APIC 0x00000200 88#define CPUID_B10 0x00000400 89#define CPUID_SEP 0x00000800 90#define CPUID_MTRR 0x00001000 91#define CPUID_PGE 0x00002000 92#define CPUID_MCA 0x00004000 93#define CPUID_CMOV 0x00008000 94#define CPUID_PAT 0x00010000 95#define CPUID_PSE36 0x00020000 96#define CPUID_PSN 0x00040000 97#define CPUID_CLFSH 0x00080000 98#define CPUID_B20 0x00100000 99#define CPUID_DS 0x00200000 100#define CPUID_ACPI 0x00400000 101#define CPUID_MMX 0x00800000 102#define CPUID_FXSR 0x01000000 103#define CPUID_SSE 0x02000000 104#define CPUID_XMM 0x02000000 105#define CPUID_SSE2 0x04000000 106#define CPUID_SS 0x08000000 107#define CPUID_HTT 0x10000000 108#define CPUID_TM 0x20000000 109#define CPUID_IA64 0x40000000 110#define CPUID_PBE 0x80000000 111 112#define CPUID2_SSE3 0x00000001 113#define CPUID2_DTES64 0x00000004 114#define CPUID2_MON 0x00000008 115#define CPUID2_DS_CPL 0x00000010 116#define CPUID2_VMX 0x00000020 117#define CPUID2_SMX 0x00000040 118#define CPUID2_EST 0x00000080 119#define CPUID2_TM2 0x00000100 120#define CPUID2_SSSE3 0x00000200 121#define CPUID2_CNXTID 0x00000400 122#define CPUID2_CX16 0x00002000 123#define CPUID2_XTPR 0x00004000 124#define CPUID2_PDCM 0x00008000 125#define CPUID2_DCA 0x00040000 126#define CPUID2_SSE41 0x00080000 127#define CPUID2_SSE42 0x00100000 128#define CPUID2_X2APIC 0x00200000 129#define CPUID2_POPCNT 0x00800000 130 131/* 132 * Important bits in the AMD extended cpuid flags 133 */ 134#define AMDID_SYSCALL 0x00000800 135#define AMDID_MP 0x00080000 136#define AMDID_NX 0x00100000 137#define AMDID_EXT_MMX 0x00400000 138#define AMDID_FFXSR 0x01000000 139#define AMDID_PAGE1GB 0x04000000 140#define AMDID_RDTSCP 0x08000000 141#define AMDID_LM 0x20000000 142#define AMDID_EXT_3DNOW 0x40000000 143#define AMDID_3DNOW 0x80000000 144 145#define AMDID2_LAHF 0x00000001 146#define AMDID2_CMP 0x00000002 147#define AMDID2_SVM 0x00000004 148#define AMDID2_EXT_APIC 0x00000008 149#define AMDID2_CR8 0x00000010 150#define AMDID2_PREFETCH 0x00000100 151 152/* 153 * CPUID instruction 1 ebx info 154 */ 155#define CPUID_BRAND_INDEX 0x000000ff 156#define CPUID_CLFUSH_SIZE 0x0000ff00 157#define CPUID_HTT_CORES 0x00ff0000 158#define CPUID_LOCAL_APIC_ID 0xff000000 159 160/* 161 * AMD extended function 8000_0008h ecx info 162 */ 163#define AMDID_CMP_CORES 0x000000ff 164 165/* 166 * CPUID manufacturers identifiers 167 */ 168#define INTEL_VENDOR_ID "GenuineIntel" 169#define AMD_VENDOR_ID "AuthenticAMD" 170 171/* 172 * Model-specific registers for the i386 family 173 */ 174#define MSR_P5_MC_ADDR 0x000 175#define MSR_P5_MC_TYPE 0x001 176#define MSR_TSC 0x010 177#define MSR_P5_CESR 0x011 178#define MSR_P5_CTR0 0x012 179#define MSR_P5_CTR1 0x013 180#define MSR_IA32_PLATFORM_ID 0x017 181#define MSR_APICBASE 0x01b 182#define MSR_EBL_CR_POWERON 0x02a 183#define MSR_TEST_CTL 0x033 184#define MSR_BIOS_UPDT_TRIG 0x079 185#define MSR_BBL_CR_D0 0x088 186#define MSR_BBL_CR_D1 0x089 187#define MSR_BBL_CR_D2 0x08a 188#define MSR_BIOS_SIGN 0x08b 189#define MSR_PERFCTR0 0x0c1 190#define MSR_PERFCTR1 0x0c2 191#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 192#define MSR_MTRRcap 0x0fe 193#define MSR_BBL_CR_ADDR 0x116 194#define MSR_BBL_CR_DECC 0x118 195#define MSR_BBL_CR_CTL 0x119 196#define MSR_BBL_CR_TRIG 0x11a 197#define MSR_BBL_CR_BUSY 0x11b 198#define MSR_BBL_CR_CTL3 0x11e 199#define MSR_SYSENTER_CS_MSR 0x174 200#define MSR_SYSENTER_ESP_MSR 0x175 201#define MSR_SYSENTER_EIP_MSR 0x176 202#define MSR_MCG_CAP 0x179 203#define MSR_MCG_STATUS 0x17a 204#define MSR_MCG_CTL 0x17b 205#define MSR_EVNTSEL0 0x186 206#define MSR_EVNTSEL1 0x187 207#define MSR_THERM_CONTROL 0x19a 208#define MSR_THERM_INTERRUPT 0x19b 209#define MSR_THERM_STATUS 0x19c 210#define MSR_IA32_MISC_ENABLE 0x1a0 211#define MSR_DEBUGCTLMSR 0x1d9 212#define MSR_LASTBRANCHFROMIP 0x1db 213#define MSR_LASTBRANCHTOIP 0x1dc 214#define MSR_LASTINTFROMIP 0x1dd 215#define MSR_LASTINTTOIP 0x1de 216#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 217#define MSR_MTRRVarBase 0x200 218#define MSR_MTRR64kBase 0x250 219#define MSR_MTRR16kBase 0x258 220#define MSR_MTRR4kBase 0x268 221#define MSR_PAT 0x277 222#define MSR_MTRRdefType 0x2ff 223#define MSR_MC0_CTL 0x400 224#define MSR_MC0_STATUS 0x401 225#define MSR_MC0_ADDR 0x402 226#define MSR_MC0_MISC 0x403 227#define MSR_MC1_CTL 0x404 228#define MSR_MC1_STATUS 0x405 229#define MSR_MC1_ADDR 0x406 230#define MSR_MC1_MISC 0x407 231#define MSR_MC2_CTL 0x408 232#define MSR_MC2_STATUS 0x409 233#define MSR_MC2_ADDR 0x40a 234#define MSR_MC2_MISC 0x40b 235#define MSR_MC3_CTL 0x40c 236#define MSR_MC3_STATUS 0x40d 237#define MSR_MC3_ADDR 0x40e 238#define MSR_MC3_MISC 0x40f 239#define MSR_MC4_CTL 0x410 240#define MSR_MC4_STATUS 0x411 241#define MSR_MC4_ADDR 0x412 242#define MSR_MC4_MISC 0x413 243 244/* 245 * Constants related to MSR's. 246 */ 247#define APICBASE_RESERVED 0x000006ff 248#define APICBASE_BSP 0x00000100 249#define APICBASE_ENABLED 0x00000800 250#define APICBASE_ADDRESS 0xfffff000 251 252/* 253 * PAT modes. 254 */ 255#define PAT_UNCACHEABLE 0x00 256#define PAT_WRITE_COMBINING 0x01 257#define PAT_WRITE_THROUGH 0x04 258#define PAT_WRITE_PROTECTED 0x05 259#define PAT_WRITE_BACK 0x06 260#define PAT_UNCACHED 0x07 261#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 262#define PAT_MASK(i) PAT_VALUE(i, 0xff) 263 264/* 265 * Constants related to MTRRs 266 */ 267#define MTRR_UNCACHEABLE 0x00 268#define MTRR_WRITE_COMBINING 0x01 269#define MTRR_WRITE_THROUGH 0x04 270#define MTRR_WRITE_PROTECTED 0x05 271#define MTRR_WRITE_BACK 0x06 272#define MTRR_N64K 8 /* numbers of fixed-size entries */ 273#define MTRR_N16K 16 274#define MTRR_N4K 64 275#define MTRR_CAP_WC 0x0000000000000400ULL 276#define MTRR_CAP_FIXED 0x0000000000000100ULL 277#define MTRR_CAP_VCNT 0x00000000000000ffULL 278#define MTRR_DEF_ENABLE 0x0000000000000800ULL 279#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL 280#define MTRR_DEF_TYPE 0x00000000000000ffULL 281#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL 282#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL 283#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL 284#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL 285 286/* 287 * Cyrix configuration registers, accessible as IO ports. 288 */ 289#define CCR0 0xc0 /* Configuration control register 0 */ 290#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 291 non-cacheable */ 292#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 293#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 294#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 295#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 296#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 297 state */ 298#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 299 assoc */ 300#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 301 302#define CCR1 0xc1 /* Configuration control register 1 */ 303#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 304#define CCR1_SMI 0x02 /* Enables SMM pins */ 305#define CCR1_SMAC 0x04 /* System management memory access */ 306#define CCR1_MMAC 0x08 /* Main memory access */ 307#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 308#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 309 310#define CCR2 0xc2 311#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 312#define CCR2_SADS 0x02 /* Slow ADS */ 313#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 314#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 315#define CCR2_WT1 0x10 /* WT region 1 */ 316#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 317#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 318 hold state. */ 319#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 320#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 321 322#define CCR3 0xc3 323#define CCR3_SMILOCK 0x01 /* SMM register lock */ 324#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 325#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 326#define CCR3_SMMMODE 0x08 /* SMM Mode */ 327#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 328#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 329#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 330#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 331 332#define CCR4 0xe8 333#define CCR4_IOMASK 0x07 334#define CCR4_MEM 0x08 /* Enables momory bypassing */ 335#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 336#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 337#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 338 339#define CCR5 0xe9 340#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 341#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 342#define CCR5_LBR1 0x10 /* Local bus region 1 */ 343#define CCR5_ARREN 0x20 /* Enables ARR region */ 344 345#define CCR6 0xea 346 347#define CCR7 0xeb 348 349/* Performance Control Register (5x86 only). */ 350#define PCR0 0x20 351#define PCR0_RSTK 0x01 /* Enables return stack */ 352#define PCR0_BTB 0x02 /* Enables branch target buffer */ 353#define PCR0_LOOP 0x04 /* Enables loop */ 354#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 355 serialize pipe. */ 356#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 357#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 358#define PCR0_LSSER 0x80 /* Disable reorder */ 359 360/* Device Identification Registers */ 361#define DIR0 0xfe 362#define DIR1 0xff 363 364/* 365 * The following four 3-byte registers control the non-cacheable regions. 366 * These registers must be written as three separate bytes. 367 * 368 * NCRx+0: A31-A24 of starting address 369 * NCRx+1: A23-A16 of starting address 370 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 371 * 372 * The non-cacheable region's starting address must be aligned to the 373 * size indicated by the NCR_SIZE_xx field. 374 */ 375#define NCR1 0xc4 376#define NCR2 0xc7 377#define NCR3 0xca 378#define NCR4 0xcd 379 380#define NCR_SIZE_0K 0 381#define NCR_SIZE_4K 1 382#define NCR_SIZE_8K 2 383#define NCR_SIZE_16K 3 384#define NCR_SIZE_32K 4 385#define NCR_SIZE_64K 5 386#define NCR_SIZE_128K 6 387#define NCR_SIZE_256K 7 388#define NCR_SIZE_512K 8 389#define NCR_SIZE_1M 9 390#define NCR_SIZE_2M 10 391#define NCR_SIZE_4M 11 392#define NCR_SIZE_8M 12 393#define NCR_SIZE_16M 13 394#define NCR_SIZE_32M 14 395#define NCR_SIZE_4G 15 396 397/* 398 * The address region registers are used to specify the location and 399 * size for the eight address regions. 400 * 401 * ARRx + 0: A31-A24 of start address 402 * ARRx + 1: A23-A16 of start address 403 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 404 */ 405#define ARR0 0xc4 406#define ARR1 0xc7 407#define ARR2 0xca 408#define ARR3 0xcd 409#define ARR4 0xd0 410#define ARR5 0xd3 411#define ARR6 0xd6 412#define ARR7 0xd9 413 414#define ARR_SIZE_0K 0 415#define ARR_SIZE_4K 1 416#define ARR_SIZE_8K 2 417#define ARR_SIZE_16K 3 418#define ARR_SIZE_32K 4 419#define ARR_SIZE_64K 5 420#define ARR_SIZE_128K 6 421#define ARR_SIZE_256K 7 422#define ARR_SIZE_512K 8 423#define ARR_SIZE_1M 9 424#define ARR_SIZE_2M 10 425#define ARR_SIZE_4M 11 426#define ARR_SIZE_8M 12 427#define ARR_SIZE_16M 13 428#define ARR_SIZE_32M 14 429#define ARR_SIZE_4G 15 430 431/* 432 * The region control registers specify the attributes associated with 433 * the ARRx addres regions. 434 */ 435#define RCR0 0xdc 436#define RCR1 0xdd 437#define RCR2 0xde 438#define RCR3 0xdf 439#define RCR4 0xe0 440#define RCR5 0xe1 441#define RCR6 0xe2 442#define RCR7 0xe3 443 444#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 445#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 446#define RCR_WWO 0x02 /* Weak write ordering. */ 447#define RCR_WL 0x04 /* Weak locking. */ 448#define RCR_WG 0x08 /* Write gathering. */ 449#define RCR_WT 0x10 /* Write-through. */ 450#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 451 452/* AMD Write Allocate Top-Of-Memory and Control Register */ 453#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 454#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 455#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 456 457/* AMD64 MSR's */ 458#define MSR_EFER 0xc0000080 /* extended features */ 459#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 460 461/* VIA ACE crypto featureset: for via_feature_rng */ 462#define VIA_HAS_RNG 1 /* cpu has RNG */ 463 464/* VIA ACE crypto featureset: for via_feature_xcrypt */ 465#define VIA_HAS_AES 1 /* cpu has AES */ 466#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 467#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 468#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 469 470/* Centaur Extended Feature flags */ 471#define VIA_CPUID_HAS_RNG 0x000004 472#define VIA_CPUID_DO_RNG 0x000008 473#define VIA_CPUID_HAS_ACE 0x000040 474#define VIA_CPUID_DO_ACE 0x000080 475#define VIA_CPUID_HAS_ACE2 0x000100 476#define VIA_CPUID_DO_ACE2 0x000200 477#define VIA_CPUID_HAS_PHE 0x000400 478#define VIA_CPUID_DO_PHE 0x000800 479#define VIA_CPUID_HAS_PMM 0x001000 480#define VIA_CPUID_DO_PMM 0x002000 481 482/* VIA ACE xcrypt-* instruction context control options */ 483#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 484#define VIA_CRYPT_CWLO_ALG_M 0x00000070 485#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 486#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 487#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 488#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 489#define VIA_CRYPT_CWLO_NORMAL 0x00000000 490#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 491#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 492#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 493#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 494#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 495#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 496 497#ifndef LOCORE 498static __inline u_char 499read_cyrix_reg(u_char reg) 500{ 501 outb(0x22, reg); 502 return inb(0x23); 503} 504 505static __inline void 506write_cyrix_reg(u_char reg, u_char data) 507{ 508 outb(0x22, reg); 509 outb(0x23, data); 510} 511#endif 512 513#endif /* !_MACHINE_SPECIALREG_H_ */ 514