specialreg.h revision 151348
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/i386/include/specialreg.h 151348 2005-10-14 22:52:01Z jkim $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 41#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#ifdef notused 44#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 45#endif 46#define CR0_PG 0x80000000 /* PaGing enable */ 47 48/* 49 * Bits in 486 special registers: 50 */ 51#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 52#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 53 all modes) */ 54#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 55#define CR0_NW 0x20000000 /* Not Write-through */ 56#define CR0_CD 0x40000000 /* Cache Disable */ 57 58/* 59 * Bits in PPro special registers 60 */ 61#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 62#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 63#define CR4_TSD 0x00000004 /* Time stamp disable */ 64#define CR4_DE 0x00000008 /* Debugging extensions */ 65#define CR4_PSE 0x00000010 /* Page size extensions */ 66#define CR4_PAE 0x00000020 /* Physical address extension */ 67#define CR4_MCE 0x00000040 /* Machine check enable */ 68#define CR4_PGE 0x00000080 /* Page global enable */ 69#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 70#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 71#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 72 73/* 74 * CPUID instruction features register 75 */ 76#define CPUID_FPU 0x00000001 77#define CPUID_VME 0x00000002 78#define CPUID_DE 0x00000004 79#define CPUID_PSE 0x00000008 80#define CPUID_TSC 0x00000010 81#define CPUID_MSR 0x00000020 82#define CPUID_PAE 0x00000040 83#define CPUID_MCE 0x00000080 84#define CPUID_CX8 0x00000100 85#define CPUID_APIC 0x00000200 86#define CPUID_B10 0x00000400 87#define CPUID_SEP 0x00000800 88#define CPUID_MTRR 0x00001000 89#define CPUID_PGE 0x00002000 90#define CPUID_MCA 0x00004000 91#define CPUID_CMOV 0x00008000 92#define CPUID_PAT 0x00010000 93#define CPUID_PSE36 0x00020000 94#define CPUID_PSN 0x00040000 95#define CPUID_CLFSH 0x00080000 96#define CPUID_B20 0x00100000 97#define CPUID_DS 0x00200000 98#define CPUID_ACPI 0x00400000 99#define CPUID_MMX 0x00800000 100#define CPUID_FXSR 0x01000000 101#define CPUID_SSE 0x02000000 102#define CPUID_XMM 0x02000000 103#define CPUID_SSE2 0x04000000 104#define CPUID_SS 0x08000000 105#define CPUID_HTT 0x10000000 106#define CPUID_TM 0x20000000 107#define CPUID_IA64 0x40000000 108#define CPUID_PBE 0x80000000 109 110/* 111 * Important bits in the AMD extended cpuid flags 112 */ 113#define AMDID_SYSCALL 0x00000800 114#define AMDID_MP 0x00080000 115#define AMDID_NX 0x00100000 116#define AMDID_EXT_MMX 0x00400000 117#define AMDID_FFXSR 0x01000000 118#define AMDID_RDTSCP 0x08000000 119#define AMDID_LM 0x20000000 120#define AMDID_EXT_3DNOW 0x40000000 121#define AMDID_3DNOW 0x80000000 122 123#define AMDID2_LAHF 0x00000001 124#define AMDID2_CMP 0x00000002 125#define AMDID2_CR8 0x00000010 126 127/* 128 * CPUID instruction 1 ebx info 129 */ 130#define CPUID_BRAND_INDEX 0x000000ff 131#define CPUID_CLFUSH_SIZE 0x0000ff00 132#define CPUID_HTT_CORES 0x00ff0000 133#define CPUID_LOCAL_APIC_ID 0xff000000 134 135/* 136 * AMD extended function 8000_0008h ecx info 137 */ 138#define AMDID_CMP_CORES 0x000000ff 139 140/* 141 * Model-specific registers for the i386 family 142 */ 143#define MSR_P5_MC_ADDR 0x000 144#define MSR_P5_MC_TYPE 0x001 145#define MSR_TSC 0x010 146#define MSR_P5_CESR 0x011 147#define MSR_P5_CTR0 0x012 148#define MSR_P5_CTR1 0x013 149#define MSR_IA32_PLATFORM_ID 0x017 150#define MSR_APICBASE 0x01b 151#define MSR_EBL_CR_POWERON 0x02a 152#define MSR_TEST_CTL 0x033 153#define MSR_BIOS_UPDT_TRIG 0x079 154#define MSR_BBL_CR_D0 0x088 155#define MSR_BBL_CR_D1 0x089 156#define MSR_BBL_CR_D2 0x08a 157#define MSR_BIOS_SIGN 0x08b 158#define MSR_PERFCTR0 0x0c1 159#define MSR_PERFCTR1 0x0c2 160#define MSR_MTRRcap 0x0fe 161#define MSR_BBL_CR_ADDR 0x116 162#define MSR_BBL_CR_DECC 0x118 163#define MSR_BBL_CR_CTL 0x119 164#define MSR_BBL_CR_TRIG 0x11a 165#define MSR_BBL_CR_BUSY 0x11b 166#define MSR_BBL_CR_CTL3 0x11e 167#define MSR_SYSENTER_CS_MSR 0x174 168#define MSR_SYSENTER_ESP_MSR 0x175 169#define MSR_SYSENTER_EIP_MSR 0x176 170#define MSR_MCG_CAP 0x179 171#define MSR_MCG_STATUS 0x17a 172#define MSR_MCG_CTL 0x17b 173#define MSR_EVNTSEL0 0x186 174#define MSR_EVNTSEL1 0x187 175#define MSR_THERM_CONTROL 0x19a 176#define MSR_THERM_INTERRUPT 0x19b 177#define MSR_THERM_STATUS 0x19c 178#define MSR_DEBUGCTLMSR 0x1d9 179#define MSR_LASTBRANCHFROMIP 0x1db 180#define MSR_LASTBRANCHTOIP 0x1dc 181#define MSR_LASTINTFROMIP 0x1dd 182#define MSR_LASTINTTOIP 0x1de 183#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 184#define MSR_MTRRVarBase 0x200 185#define MSR_MTRR64kBase 0x250 186#define MSR_MTRR16kBase 0x258 187#define MSR_MTRR4kBase 0x268 188#define MSR_MTRRdefType 0x2ff 189#define MSR_MC0_CTL 0x400 190#define MSR_MC0_STATUS 0x401 191#define MSR_MC0_ADDR 0x402 192#define MSR_MC0_MISC 0x403 193#define MSR_MC1_CTL 0x404 194#define MSR_MC1_STATUS 0x405 195#define MSR_MC1_ADDR 0x406 196#define MSR_MC1_MISC 0x407 197#define MSR_MC2_CTL 0x408 198#define MSR_MC2_STATUS 0x409 199#define MSR_MC2_ADDR 0x40a 200#define MSR_MC2_MISC 0x40b 201#define MSR_MC4_CTL 0x40c 202#define MSR_MC4_STATUS 0x40d 203#define MSR_MC4_ADDR 0x40e 204#define MSR_MC4_MISC 0x40f 205#define MSR_MC3_CTL 0x410 206#define MSR_MC3_STATUS 0x411 207#define MSR_MC3_ADDR 0x412 208#define MSR_MC3_MISC 0x413 209 210/* 211 * Constants related to MSR's. 212 */ 213#define APICBASE_RESERVED 0x000006ff 214#define APICBASE_BSP 0x00000100 215#define APICBASE_ENABLED 0x00000800 216#define APICBASE_ADDRESS 0xfffff000 217 218/* 219 * Constants related to MTRRs 220 */ 221#define MTRR_N64K 8 /* numbers of fixed-size entries */ 222#define MTRR_N16K 16 223#define MTRR_N4K 64 224 225/* 226 * Cyrix configuration registers, accessible as IO ports. 227 */ 228#define CCR0 0xc0 /* Configuration control register 0 */ 229#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 230 non-cacheable */ 231#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 232#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 233#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 234#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 235#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 236 state */ 237#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 238 assoc */ 239#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 240 241#define CCR1 0xc1 /* Configuration control register 1 */ 242#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 243#define CCR1_SMI 0x02 /* Enables SMM pins */ 244#define CCR1_SMAC 0x04 /* System management memory access */ 245#define CCR1_MMAC 0x08 /* Main memory access */ 246#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 247#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 248 249#define CCR2 0xc2 250#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 251#define CCR2_SADS 0x02 /* Slow ADS */ 252#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 253#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 254#define CCR2_WT1 0x10 /* WT region 1 */ 255#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 256#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 257 hold state. */ 258#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 259#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 260 261#define CCR3 0xc3 262#define CCR3_SMILOCK 0x01 /* SMM register lock */ 263#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 264#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 265#define CCR3_SMMMODE 0x08 /* SMM Mode */ 266#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 267#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 268#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 269#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 270 271#define CCR4 0xe8 272#define CCR4_IOMASK 0x07 273#define CCR4_MEM 0x08 /* Enables momory bypassing */ 274#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 275#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 276#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 277 278#define CCR5 0xe9 279#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 280#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 281#define CCR5_LBR1 0x10 /* Local bus region 1 */ 282#define CCR5_ARREN 0x20 /* Enables ARR region */ 283 284#define CCR6 0xea 285 286#define CCR7 0xeb 287 288/* Performance Control Register (5x86 only). */ 289#define PCR0 0x20 290#define PCR0_RSTK 0x01 /* Enables return stack */ 291#define PCR0_BTB 0x02 /* Enables branch target buffer */ 292#define PCR0_LOOP 0x04 /* Enables loop */ 293#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 294 serialize pipe. */ 295#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 296#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 297#define PCR0_LSSER 0x80 /* Disable reorder */ 298 299/* Device Identification Registers */ 300#define DIR0 0xfe 301#define DIR1 0xff 302 303/* 304 * The following four 3-byte registers control the non-cacheable regions. 305 * These registers must be written as three separate bytes. 306 * 307 * NCRx+0: A31-A24 of starting address 308 * NCRx+1: A23-A16 of starting address 309 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 310 * 311 * The non-cacheable region's starting address must be aligned to the 312 * size indicated by the NCR_SIZE_xx field. 313 */ 314#define NCR1 0xc4 315#define NCR2 0xc7 316#define NCR3 0xca 317#define NCR4 0xcd 318 319#define NCR_SIZE_0K 0 320#define NCR_SIZE_4K 1 321#define NCR_SIZE_8K 2 322#define NCR_SIZE_16K 3 323#define NCR_SIZE_32K 4 324#define NCR_SIZE_64K 5 325#define NCR_SIZE_128K 6 326#define NCR_SIZE_256K 7 327#define NCR_SIZE_512K 8 328#define NCR_SIZE_1M 9 329#define NCR_SIZE_2M 10 330#define NCR_SIZE_4M 11 331#define NCR_SIZE_8M 12 332#define NCR_SIZE_16M 13 333#define NCR_SIZE_32M 14 334#define NCR_SIZE_4G 15 335 336/* 337 * The address region registers are used to specify the location and 338 * size for the eight address regions. 339 * 340 * ARRx + 0: A31-A24 of start address 341 * ARRx + 1: A23-A16 of start address 342 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 343 */ 344#define ARR0 0xc4 345#define ARR1 0xc7 346#define ARR2 0xca 347#define ARR3 0xcd 348#define ARR4 0xd0 349#define ARR5 0xd3 350#define ARR6 0xd6 351#define ARR7 0xd9 352 353#define ARR_SIZE_0K 0 354#define ARR_SIZE_4K 1 355#define ARR_SIZE_8K 2 356#define ARR_SIZE_16K 3 357#define ARR_SIZE_32K 4 358#define ARR_SIZE_64K 5 359#define ARR_SIZE_128K 6 360#define ARR_SIZE_256K 7 361#define ARR_SIZE_512K 8 362#define ARR_SIZE_1M 9 363#define ARR_SIZE_2M 10 364#define ARR_SIZE_4M 11 365#define ARR_SIZE_8M 12 366#define ARR_SIZE_16M 13 367#define ARR_SIZE_32M 14 368#define ARR_SIZE_4G 15 369 370/* 371 * The region control registers specify the attributes associated with 372 * the ARRx addres regions. 373 */ 374#define RCR0 0xdc 375#define RCR1 0xdd 376#define RCR2 0xde 377#define RCR3 0xdf 378#define RCR4 0xe0 379#define RCR5 0xe1 380#define RCR6 0xe2 381#define RCR7 0xe3 382 383#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 384#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 385#define RCR_WWO 0x02 /* Weak write ordering. */ 386#define RCR_WL 0x04 /* Weak locking. */ 387#define RCR_WG 0x08 /* Write gathering. */ 388#define RCR_WT 0x10 /* Write-through. */ 389#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 390 391/* AMD Write Allocate Top-Of-Memory and Control Register */ 392#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 393#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 394#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 395 396 397#ifndef LOCORE 398static __inline u_char 399read_cyrix_reg(u_char reg) 400{ 401 outb(0x22, reg); 402 return inb(0x23); 403} 404 405static __inline void 406write_cyrix_reg(u_char reg, u_char data) 407{ 408 outb(0x22, reg); 409 outb(0x23, data); 410} 411#endif 412 413#endif /* !_MACHINE_SPECIALREG_H_ */ 414