specialreg.h revision 124685
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 * $FreeBSD: head/sys/i386/include/specialreg.h 124685 2004-01-18 21:18:00Z sobomax $ 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ 43#define CR0_PE 0x00000001 /* Protected mode Enable */ 44#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 45#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 46#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 47#ifdef notused 48#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 49#endif 50#define CR0_PG 0x80000000 /* PaGing enable */ 51 52/* 53 * Bits in 486 special registers: 54 */ 55#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 56#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 57 all modes) */ 58#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 59#define CR0_NW 0x20000000 /* Not Write-through */ 60#define CR0_CD 0x40000000 /* Cache Disable */ 61 62/* 63 * Bits in PPro special registers 64 */ 65#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 66#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 67#define CR4_TSD 0x00000004 /* Time stamp disable */ 68#define CR4_DE 0x00000008 /* Debugging extensions */ 69#define CR4_PSE 0x00000010 /* Page size extensions */ 70#define CR4_PAE 0x00000020 /* Physical address extension */ 71#define CR4_MCE 0x00000040 /* Machine check enable */ 72#define CR4_PGE 0x00000080 /* Page global enable */ 73#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 74#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 75#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 76 77/* 78 * CPUID instruction features register 79 */ 80#define CPUID_FPU 0x00000001 81#define CPUID_VME 0x00000002 82#define CPUID_DE 0x00000004 83#define CPUID_PSE 0x00000008 84#define CPUID_TSC 0x00000010 85#define CPUID_MSR 0x00000020 86#define CPUID_PAE 0x00000040 87#define CPUID_MCE 0x00000080 88#define CPUID_CX8 0x00000100 89#define CPUID_APIC 0x00000200 90#define CPUID_B10 0x00000400 91#define CPUID_SEP 0x00000800 92#define CPUID_MTRR 0x00001000 93#define CPUID_PGE 0x00002000 94#define CPUID_MCA 0x00004000 95#define CPUID_CMOV 0x00008000 96#define CPUID_PAT 0x00010000 97#define CPUID_PSE36 0x00020000 98#define CPUID_PSN 0x00040000 99#define CPUID_CLFSH 0x00080000 100#define CPUID_B20 0x00100000 101#define CPUID_DS 0x00200000 102#define CPUID_ACPI 0x00400000 103#define CPUID_MMX 0x00800000 104#define CPUID_FXSR 0x01000000 105#define CPUID_SSE 0x02000000 106#define CPUID_XMM 0x02000000 107#define CPUID_SSE2 0x04000000 108#define CPUID_SS 0x08000000 109#define CPUID_HTT 0x10000000 110#define CPUID_TM 0x20000000 111#define CPUID_IA64 0x40000000 112#define CPUID_PBE 0x80000000 113 114/* 115 * CPUID instruction 1 ebx info 116 */ 117#define CPUID_BRAND_INDEX 0x000000ff 118#define CPUID_CLFUSH_SIZE 0x0000ff00 119#define CPUID_HTT_CORES 0x00ff0000 120#define CPUID_LOCAL_APIC_ID 0xff000000 121 122/* 123 * Model-specific registers for the i386 family 124 */ 125#define MSR_P5_MC_ADDR 0x000 126#define MSR_P5_MC_TYPE 0x001 127#define MSR_TSC 0x010 128#define MSR_P5_CESR 0x011 129#define MSR_P5_CTR0 0x012 130#define MSR_P5_CTR1 0x013 131#define MSR_IA32_PLATFORM_ID 0x017 132#define MSR_APICBASE 0x01b 133#define MSR_EBL_CR_POWERON 0x02a 134#define MSR_TEST_CTL 0x033 135#define MSR_BIOS_UPDT_TRIG 0x079 136#define MSR_BBL_CR_D0 0x088 137#define MSR_BBL_CR_D1 0x089 138#define MSR_BBL_CR_D2 0x08a 139#define MSR_BIOS_SIGN 0x08b 140#define MSR_PERFCTR0 0x0c1 141#define MSR_PERFCTR1 0x0c2 142#define MSR_MTRRcap 0x0fe 143#define MSR_BBL_CR_ADDR 0x116 144#define MSR_BBL_CR_DECC 0x118 145#define MSR_BBL_CR_CTL 0x119 146#define MSR_BBL_CR_TRIG 0x11a 147#define MSR_BBL_CR_BUSY 0x11b 148#define MSR_BBL_CR_CTL3 0x11e 149#define MSR_SYSENTER_CS_MSR 0x174 150#define MSR_SYSENTER_ESP_MSR 0x175 151#define MSR_SYSENTER_EIP_MSR 0x176 152#define MSR_MCG_CAP 0x179 153#define MSR_MCG_STATUS 0x17a 154#define MSR_MCG_CTL 0x17b 155#define MSR_EVNTSEL0 0x186 156#define MSR_EVNTSEL1 0x187 157#define MSR_THERM_CONTROL 0x19a 158#define MSR_THERM_INTERRUPT 0x19b 159#define MSR_THERM_STATUS 0x19c 160#define MSR_DEBUGCTLMSR 0x1d9 161#define MSR_LASTBRANCHFROMIP 0x1db 162#define MSR_LASTBRANCHTOIP 0x1dc 163#define MSR_LASTINTFROMIP 0x1dd 164#define MSR_LASTINTTOIP 0x1de 165#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 166#define MSR_MTRRVarBase 0x200 167#define MSR_MTRR64kBase 0x250 168#define MSR_MTRR16kBase 0x258 169#define MSR_MTRR4kBase 0x268 170#define MSR_MTRRdefType 0x2ff 171#define MSR_MC0_CTL 0x400 172#define MSR_MC0_STATUS 0x401 173#define MSR_MC0_ADDR 0x402 174#define MSR_MC0_MISC 0x403 175#define MSR_MC1_CTL 0x404 176#define MSR_MC1_STATUS 0x405 177#define MSR_MC1_ADDR 0x406 178#define MSR_MC1_MISC 0x407 179#define MSR_MC2_CTL 0x408 180#define MSR_MC2_STATUS 0x409 181#define MSR_MC2_ADDR 0x40a 182#define MSR_MC2_MISC 0x40b 183#define MSR_MC4_CTL 0x40c 184#define MSR_MC4_STATUS 0x40d 185#define MSR_MC4_ADDR 0x40e 186#define MSR_MC4_MISC 0x40f 187#define MSR_MC3_CTL 0x410 188#define MSR_MC3_STATUS 0x411 189#define MSR_MC3_ADDR 0x412 190#define MSR_MC3_MISC 0x413 191 192/* 193 * Constants related to MSR's. 194 */ 195#define APICBASE_RESERVED 0x000006ff 196#define APICBASE_BSP 0x00000100 197#define APICBASE_ENABLED 0x00000800 198#define APICBASE_ADDRESS 0xfffff000 199 200/* 201 * Constants related to MTRRs 202 */ 203#define MTRR_N64K 8 /* numbers of fixed-size entries */ 204#define MTRR_N16K 16 205#define MTRR_N4K 64 206 207/* 208 * Cyrix configuration registers, accessible as IO ports. 209 */ 210#define CCR0 0xc0 /* Configuration control register 0 */ 211#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 212 non-cacheable */ 213#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 214#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 215#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 216#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 217#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 218 state */ 219#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 220 assoc */ 221#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 222 223#define CCR1 0xc1 /* Configuration control register 1 */ 224#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 225#define CCR1_SMI 0x02 /* Enables SMM pins */ 226#define CCR1_SMAC 0x04 /* System management memory access */ 227#define CCR1_MMAC 0x08 /* Main memory access */ 228#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 229#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 230 231#define CCR2 0xc2 232#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 233#define CCR2_SADS 0x02 /* Slow ADS */ 234#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 235#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 236#define CCR2_WT1 0x10 /* WT region 1 */ 237#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 238#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 239 hold state. */ 240#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 241#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 242 243#define CCR3 0xc3 244#define CCR3_SMILOCK 0x01 /* SMM register lock */ 245#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 246#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 247#define CCR3_SMMMODE 0x08 /* SMM Mode */ 248#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 249#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 250#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 251#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 252 253#define CCR4 0xe8 254#define CCR4_IOMASK 0x07 255#define CCR4_MEM 0x08 /* Enables momory bypassing */ 256#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 257#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 258#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 259 260#define CCR5 0xe9 261#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 262#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 263#define CCR5_LBR1 0x10 /* Local bus region 1 */ 264#define CCR5_ARREN 0x20 /* Enables ARR region */ 265 266#define CCR6 0xea 267 268#define CCR7 0xeb 269 270/* Performance Control Register (5x86 only). */ 271#define PCR0 0x20 272#define PCR0_RSTK 0x01 /* Enables return stack */ 273#define PCR0_BTB 0x02 /* Enables branch target buffer */ 274#define PCR0_LOOP 0x04 /* Enables loop */ 275#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 276 serialize pipe. */ 277#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 278#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 279#define PCR0_LSSER 0x80 /* Disable reorder */ 280 281/* Device Identification Registers */ 282#define DIR0 0xfe 283#define DIR1 0xff 284 285/* 286 * The following four 3-byte registers control the non-cacheable regions. 287 * These registers must be written as three separate bytes. 288 * 289 * NCRx+0: A31-A24 of starting address 290 * NCRx+1: A23-A16 of starting address 291 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 292 * 293 * The non-cacheable region's starting address must be aligned to the 294 * size indicated by the NCR_SIZE_xx field. 295 */ 296#define NCR1 0xc4 297#define NCR2 0xc7 298#define NCR3 0xca 299#define NCR4 0xcd 300 301#define NCR_SIZE_0K 0 302#define NCR_SIZE_4K 1 303#define NCR_SIZE_8K 2 304#define NCR_SIZE_16K 3 305#define NCR_SIZE_32K 4 306#define NCR_SIZE_64K 5 307#define NCR_SIZE_128K 6 308#define NCR_SIZE_256K 7 309#define NCR_SIZE_512K 8 310#define NCR_SIZE_1M 9 311#define NCR_SIZE_2M 10 312#define NCR_SIZE_4M 11 313#define NCR_SIZE_8M 12 314#define NCR_SIZE_16M 13 315#define NCR_SIZE_32M 14 316#define NCR_SIZE_4G 15 317 318/* 319 * The address region registers are used to specify the location and 320 * size for the eight address regions. 321 * 322 * ARRx + 0: A31-A24 of start address 323 * ARRx + 1: A23-A16 of start address 324 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 325 */ 326#define ARR0 0xc4 327#define ARR1 0xc7 328#define ARR2 0xca 329#define ARR3 0xcd 330#define ARR4 0xd0 331#define ARR5 0xd3 332#define ARR6 0xd6 333#define ARR7 0xd9 334 335#define ARR_SIZE_0K 0 336#define ARR_SIZE_4K 1 337#define ARR_SIZE_8K 2 338#define ARR_SIZE_16K 3 339#define ARR_SIZE_32K 4 340#define ARR_SIZE_64K 5 341#define ARR_SIZE_128K 6 342#define ARR_SIZE_256K 7 343#define ARR_SIZE_512K 8 344#define ARR_SIZE_1M 9 345#define ARR_SIZE_2M 10 346#define ARR_SIZE_4M 11 347#define ARR_SIZE_8M 12 348#define ARR_SIZE_16M 13 349#define ARR_SIZE_32M 14 350#define ARR_SIZE_4G 15 351 352/* 353 * The region control registers specify the attributes associated with 354 * the ARRx addres regions. 355 */ 356#define RCR0 0xdc 357#define RCR1 0xdd 358#define RCR2 0xde 359#define RCR3 0xdf 360#define RCR4 0xe0 361#define RCR5 0xe1 362#define RCR6 0xe2 363#define RCR7 0xe3 364 365#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 366#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 367#define RCR_WWO 0x02 /* Weak write ordering. */ 368#define RCR_WL 0x04 /* Weak locking. */ 369#define RCR_WG 0x08 /* Write gathering. */ 370#define RCR_WT 0x10 /* Write-through. */ 371#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 372 373/* AMD Write Allocate Top-Of-Memory and Control Register */ 374#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 375#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 376#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 377 378 379#ifndef LOCORE 380static __inline u_char 381read_cyrix_reg(u_char reg) 382{ 383 outb(0x22, reg); 384 return inb(0x23); 385} 386 387static __inline void 388write_cyrix_reg(u_char reg, u_char data) 389{ 390 outb(0x22, reg); 391 outb(0x23, data); 392} 393#endif 394 395#endif /* !_MACHINE_SPECIALREG_H_ */ 396