specialreg.h revision 234364
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/x86/include/specialreg.h 234364 2012-04-17 00:54:38Z grehan $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55/* 56 * Bits in PPro special registers 57 */ 58#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60#define CR4_TSD 0x00000004 /* Time stamp disable */ 61#define CR4_DE 0x00000008 /* Debugging extensions */ 62#define CR4_PSE 0x00000010 /* Page size extensions */ 63#define CR4_PAE 0x00000020 /* Physical address extension */ 64#define CR4_MCE 0x00000040 /* Machine check enable */ 65#define CR4_PGE 0x00000080 /* Page global enable */ 66#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 70 71/* 72 * Bits in AMD64 special registers. EFER is 64 bits wide. 73 */ 74#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 75#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 76#define EFER_LMA 0x000000400 /* Long mode active (R) */ 77#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 78 79/* 80 * Intel Extended Features registers 81 */ 82#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 83 84#define XFEATURE_ENABLED_X87 0x00000001 85#define XFEATURE_ENABLED_SSE 0x00000002 86#define XFEATURE_ENABLED_AVX 0x00000004 87 88#define XFEATURE_AVX \ 89 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 90 91/* 92 * CPUID instruction features register 93 */ 94#define CPUID_FPU 0x00000001 95#define CPUID_VME 0x00000002 96#define CPUID_DE 0x00000004 97#define CPUID_PSE 0x00000008 98#define CPUID_TSC 0x00000010 99#define CPUID_MSR 0x00000020 100#define CPUID_PAE 0x00000040 101#define CPUID_MCE 0x00000080 102#define CPUID_CX8 0x00000100 103#define CPUID_APIC 0x00000200 104#define CPUID_B10 0x00000400 105#define CPUID_SEP 0x00000800 106#define CPUID_MTRR 0x00001000 107#define CPUID_PGE 0x00002000 108#define CPUID_MCA 0x00004000 109#define CPUID_CMOV 0x00008000 110#define CPUID_PAT 0x00010000 111#define CPUID_PSE36 0x00020000 112#define CPUID_PSN 0x00040000 113#define CPUID_CLFSH 0x00080000 114#define CPUID_B20 0x00100000 115#define CPUID_DS 0x00200000 116#define CPUID_ACPI 0x00400000 117#define CPUID_MMX 0x00800000 118#define CPUID_FXSR 0x01000000 119#define CPUID_SSE 0x02000000 120#define CPUID_XMM 0x02000000 121#define CPUID_SSE2 0x04000000 122#define CPUID_SS 0x08000000 123#define CPUID_HTT 0x10000000 124#define CPUID_TM 0x20000000 125#define CPUID_IA64 0x40000000 126#define CPUID_PBE 0x80000000 127 128#define CPUID2_SSE3 0x00000001 129#define CPUID2_PCLMULQDQ 0x00000002 130#define CPUID2_DTES64 0x00000004 131#define CPUID2_MON 0x00000008 132#define CPUID2_DS_CPL 0x00000010 133#define CPUID2_VMX 0x00000020 134#define CPUID2_SMX 0x00000040 135#define CPUID2_EST 0x00000080 136#define CPUID2_TM2 0x00000100 137#define CPUID2_SSSE3 0x00000200 138#define CPUID2_CNXTID 0x00000400 139#define CPUID2_FMA 0x00001000 140#define CPUID2_CX16 0x00002000 141#define CPUID2_XTPR 0x00004000 142#define CPUID2_PDCM 0x00008000 143#define CPUID2_PCID 0x00020000 144#define CPUID2_DCA 0x00040000 145#define CPUID2_SSE41 0x00080000 146#define CPUID2_SSE42 0x00100000 147#define CPUID2_X2APIC 0x00200000 148#define CPUID2_MOVBE 0x00400000 149#define CPUID2_POPCNT 0x00800000 150#define CPUID2_TSCDLT 0x01000000 151#define CPUID2_AESNI 0x02000000 152#define CPUID2_XSAVE 0x04000000 153#define CPUID2_OSXSAVE 0x08000000 154#define CPUID2_AVX 0x10000000 155#define CPUID2_F16C 0x20000000 156#define CPUID2_RDRAND 0x40000000 157#define CPUID2_HV 0x80000000 158 159/* 160 * Important bits in the Thermal and Power Management flags 161 * CPUID.6 EAX and ECX. 162 */ 163#define CPUTPM1_SENSOR 0x00000001 164#define CPUTPM1_TURBO 0x00000002 165#define CPUTPM1_ARAT 0x00000004 166#define CPUTPM2_EFFREQ 0x00000001 167 168/* 169 * Important bits in the AMD extended cpuid flags 170 */ 171#define AMDID_SYSCALL 0x00000800 172#define AMDID_MP 0x00080000 173#define AMDID_NX 0x00100000 174#define AMDID_EXT_MMX 0x00400000 175#define AMDID_FFXSR 0x01000000 176#define AMDID_PAGE1GB 0x04000000 177#define AMDID_RDTSCP 0x08000000 178#define AMDID_LM 0x20000000 179#define AMDID_EXT_3DNOW 0x40000000 180#define AMDID_3DNOW 0x80000000 181 182#define AMDID2_LAHF 0x00000001 183#define AMDID2_CMP 0x00000002 184#define AMDID2_SVM 0x00000004 185#define AMDID2_EXT_APIC 0x00000008 186#define AMDID2_CR8 0x00000010 187#define AMDID2_ABM 0x00000020 188#define AMDID2_SSE4A 0x00000040 189#define AMDID2_MAS 0x00000080 190#define AMDID2_PREFETCH 0x00000100 191#define AMDID2_OSVW 0x00000200 192#define AMDID2_IBS 0x00000400 193#define AMDID2_XOP 0x00000800 194#define AMDID2_SKINIT 0x00001000 195#define AMDID2_WDT 0x00002000 196#define AMDID2_LWP 0x00008000 197#define AMDID2_FMA4 0x00010000 198#define AMDID2_NODE_ID 0x00080000 199#define AMDID2_TBM 0x00200000 200#define AMDID2_TOPOLOGY 0x00400000 201 202/* 203 * CPUID instruction 1 eax info 204 */ 205#define CPUID_STEPPING 0x0000000f 206#define CPUID_MODEL 0x000000f0 207#define CPUID_FAMILY 0x00000f00 208#define CPUID_EXT_MODEL 0x000f0000 209#define CPUID_EXT_FAMILY 0x0ff00000 210#ifdef __i386__ 211#define CPUID_TO_MODEL(id) \ 212 ((((id) & CPUID_MODEL) >> 4) | \ 213 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 214 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 215#define CPUID_TO_FAMILY(id) \ 216 ((((id) & CPUID_FAMILY) >> 8) + \ 217 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 218 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 219#else 220#define CPUID_TO_MODEL(id) \ 221 ((((id) & CPUID_MODEL) >> 4) | \ 222 (((id) & CPUID_EXT_MODEL) >> 12)) 223#define CPUID_TO_FAMILY(id) \ 224 ((((id) & CPUID_FAMILY) >> 8) + \ 225 (((id) & CPUID_EXT_FAMILY) >> 20)) 226#endif 227 228/* 229 * CPUID instruction 1 ebx info 230 */ 231#define CPUID_BRAND_INDEX 0x000000ff 232#define CPUID_CLFUSH_SIZE 0x0000ff00 233#define CPUID_HTT_CORES 0x00ff0000 234#define CPUID_LOCAL_APIC_ID 0xff000000 235 236/* 237 * CPUID instruction 6 ecx info 238 */ 239#define CPUID_PERF_STAT 0x00000001 240#define CPUID_PERF_BIAS 0x00000008 241 242/* 243 * CPUID instruction 0xb ebx info. 244 */ 245#define CPUID_TYPE_INVAL 0 246#define CPUID_TYPE_SMT 1 247#define CPUID_TYPE_CORE 2 248 249/* 250 * AMD extended function 8000_0007h edx info 251 */ 252#define AMDPM_TS 0x00000001 253#define AMDPM_FID 0x00000002 254#define AMDPM_VID 0x00000004 255#define AMDPM_TTP 0x00000008 256#define AMDPM_TM 0x00000010 257#define AMDPM_STC 0x00000020 258#define AMDPM_100MHZ_STEPS 0x00000040 259#define AMDPM_HW_PSTATE 0x00000080 260#define AMDPM_TSC_INVARIANT 0x00000100 261#define AMDPM_CPB 0x00000200 262 263/* 264 * AMD extended function 8000_0008h ecx info 265 */ 266#define AMDID_CMP_CORES 0x000000ff 267#define AMDID_COREID_SIZE 0x0000f000 268#define AMDID_COREID_SIZE_SHIFT 12 269 270/* 271 * CPUID manufacturers identifiers 272 */ 273#define AMD_VENDOR_ID "AuthenticAMD" 274#define CENTAUR_VENDOR_ID "CentaurHauls" 275#define CYRIX_VENDOR_ID "CyrixInstead" 276#define INTEL_VENDOR_ID "GenuineIntel" 277#define NEXGEN_VENDOR_ID "NexGenDriven" 278#define NSC_VENDOR_ID "Geode by NSC" 279#define RISE_VENDOR_ID "RiseRiseRise" 280#define SIS_VENDOR_ID "SiS SiS SiS " 281#define TRANSMETA_VENDOR_ID "GenuineTMx86" 282#define UMC_VENDOR_ID "UMC UMC UMC " 283 284/* 285 * Model-specific registers for the i386 family 286 */ 287#define MSR_P5_MC_ADDR 0x000 288#define MSR_P5_MC_TYPE 0x001 289#define MSR_TSC 0x010 290#define MSR_P5_CESR 0x011 291#define MSR_P5_CTR0 0x012 292#define MSR_P5_CTR1 0x013 293#define MSR_IA32_PLATFORM_ID 0x017 294#define MSR_APICBASE 0x01b 295#define MSR_EBL_CR_POWERON 0x02a 296#define MSR_TEST_CTL 0x033 297#define MSR_BIOS_UPDT_TRIG 0x079 298#define MSR_BBL_CR_D0 0x088 299#define MSR_BBL_CR_D1 0x089 300#define MSR_BBL_CR_D2 0x08a 301#define MSR_BIOS_SIGN 0x08b 302#define MSR_PERFCTR0 0x0c1 303#define MSR_PERFCTR1 0x0c2 304#define MSR_MPERF 0x0e7 305#define MSR_APERF 0x0e8 306#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 307#define MSR_MTRRcap 0x0fe 308#define MSR_BBL_CR_ADDR 0x116 309#define MSR_BBL_CR_DECC 0x118 310#define MSR_BBL_CR_CTL 0x119 311#define MSR_BBL_CR_TRIG 0x11a 312#define MSR_BBL_CR_BUSY 0x11b 313#define MSR_BBL_CR_CTL3 0x11e 314#define MSR_SYSENTER_CS_MSR 0x174 315#define MSR_SYSENTER_ESP_MSR 0x175 316#define MSR_SYSENTER_EIP_MSR 0x176 317#define MSR_MCG_CAP 0x179 318#define MSR_MCG_STATUS 0x17a 319#define MSR_MCG_CTL 0x17b 320#define MSR_EVNTSEL0 0x186 321#define MSR_EVNTSEL1 0x187 322#define MSR_THERM_CONTROL 0x19a 323#define MSR_THERM_INTERRUPT 0x19b 324#define MSR_THERM_STATUS 0x19c 325#define MSR_IA32_MISC_ENABLE 0x1a0 326#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 327#define MSR_DEBUGCTLMSR 0x1d9 328#define MSR_LASTBRANCHFROMIP 0x1db 329#define MSR_LASTBRANCHTOIP 0x1dc 330#define MSR_LASTINTFROMIP 0x1dd 331#define MSR_LASTINTTOIP 0x1de 332#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 333#define MSR_MTRRVarBase 0x200 334#define MSR_MTRR64kBase 0x250 335#define MSR_MTRR16kBase 0x258 336#define MSR_MTRR4kBase 0x268 337#define MSR_PAT 0x277 338#define MSR_MC0_CTL2 0x280 339#define MSR_MTRRdefType 0x2ff 340#define MSR_MC0_CTL 0x400 341#define MSR_MC0_STATUS 0x401 342#define MSR_MC0_ADDR 0x402 343#define MSR_MC0_MISC 0x403 344#define MSR_MC1_CTL 0x404 345#define MSR_MC1_STATUS 0x405 346#define MSR_MC1_ADDR 0x406 347#define MSR_MC1_MISC 0x407 348#define MSR_MC2_CTL 0x408 349#define MSR_MC2_STATUS 0x409 350#define MSR_MC2_ADDR 0x40a 351#define MSR_MC2_MISC 0x40b 352#define MSR_MC3_CTL 0x40c 353#define MSR_MC3_STATUS 0x40d 354#define MSR_MC3_ADDR 0x40e 355#define MSR_MC3_MISC 0x40f 356#define MSR_MC4_CTL 0x410 357#define MSR_MC4_STATUS 0x411 358#define MSR_MC4_ADDR 0x412 359#define MSR_MC4_MISC 0x413 360 361/* 362 * X2APIC MSRs 363 */ 364#define MSR_APIC_ID 0x802 365#define MSR_APIC_VERSION 0x803 366#define MSR_APIC_TPR 0x808 367#define MSR_APIC_EOI 0x80b 368#define MSR_APIC_LDR 0x80d 369#define MSR_APIC_SVR 0x80f 370#define MSR_APIC_ISR0 0x810 371#define MSR_APIC_ISR1 0x811 372#define MSR_APIC_ISR2 0x812 373#define MSR_APIC_ISR3 0x813 374#define MSR_APIC_ISR4 0x814 375#define MSR_APIC_ISR5 0x815 376#define MSR_APIC_ISR6 0x816 377#define MSR_APIC_ISR7 0x817 378#define MSR_APIC_TMR0 0x818 379#define MSR_APIC_IRR0 0x820 380#define MSR_APIC_ESR 0x828 381#define MSR_APIC_LVT_CMCI 0x82F 382#define MSR_APIC_ICR 0x830 383#define MSR_APIC_LVT_TIMER 0x832 384#define MSR_APIC_LVT_THERMAL 0x833 385#define MSR_APIC_LVT_PCINT 0x834 386#define MSR_APIC_LVT_LINT0 0x835 387#define MSR_APIC_LVT_LINT1 0x836 388#define MSR_APIC_LVT_ERROR 0x837 389#define MSR_APIC_ICR_TIMER 0x838 390#define MSR_APIC_CCR_TIMER 0x839 391#define MSR_APIC_DCR_TIMER 0x83e 392#define MSR_APIC_SELF_IPI 0x83f 393 394/* 395 * Constants related to MSR's. 396 */ 397#define APICBASE_RESERVED 0x000002ff 398#define APICBASE_BSP 0x00000100 399#define APICBASE_X2APIC 0x00000400 400#define APICBASE_ENABLED 0x00000800 401#define APICBASE_ADDRESS 0xfffff000 402 403/* 404 * PAT modes. 405 */ 406#define PAT_UNCACHEABLE 0x00 407#define PAT_WRITE_COMBINING 0x01 408#define PAT_WRITE_THROUGH 0x04 409#define PAT_WRITE_PROTECTED 0x05 410#define PAT_WRITE_BACK 0x06 411#define PAT_UNCACHED 0x07 412#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 413#define PAT_MASK(i) PAT_VALUE(i, 0xff) 414 415/* 416 * Constants related to MTRRs 417 */ 418#define MTRR_UNCACHEABLE 0x00 419#define MTRR_WRITE_COMBINING 0x01 420#define MTRR_WRITE_THROUGH 0x04 421#define MTRR_WRITE_PROTECTED 0x05 422#define MTRR_WRITE_BACK 0x06 423#define MTRR_N64K 8 /* numbers of fixed-size entries */ 424#define MTRR_N16K 16 425#define MTRR_N4K 64 426#define MTRR_CAP_WC 0x0000000000000400 427#define MTRR_CAP_FIXED 0x0000000000000100 428#define MTRR_CAP_VCNT 0x00000000000000ff 429#define MTRR_DEF_ENABLE 0x0000000000000800 430#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 431#define MTRR_DEF_TYPE 0x00000000000000ff 432#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 433#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 434#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 435#define MTRR_PHYSMASK_VALID 0x0000000000000800 436 437/* 438 * Cyrix configuration registers, accessible as IO ports. 439 */ 440#define CCR0 0xc0 /* Configuration control register 0 */ 441#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 442 non-cacheable */ 443#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 444#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 445#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 446#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 447#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 448 state */ 449#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 450 assoc */ 451#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 452 453#define CCR1 0xc1 /* Configuration control register 1 */ 454#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 455#define CCR1_SMI 0x02 /* Enables SMM pins */ 456#define CCR1_SMAC 0x04 /* System management memory access */ 457#define CCR1_MMAC 0x08 /* Main memory access */ 458#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 459#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 460 461#define CCR2 0xc2 462#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 463#define CCR2_SADS 0x02 /* Slow ADS */ 464#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 465#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 466#define CCR2_WT1 0x10 /* WT region 1 */ 467#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 468#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 469 hold state. */ 470#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 471#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 472 473#define CCR3 0xc3 474#define CCR3_SMILOCK 0x01 /* SMM register lock */ 475#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 476#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 477#define CCR3_SMMMODE 0x08 /* SMM Mode */ 478#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 479#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 480#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 481#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 482 483#define CCR4 0xe8 484#define CCR4_IOMASK 0x07 485#define CCR4_MEM 0x08 /* Enables momory bypassing */ 486#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 487#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 488#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 489 490#define CCR5 0xe9 491#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 492#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 493#define CCR5_LBR1 0x10 /* Local bus region 1 */ 494#define CCR5_ARREN 0x20 /* Enables ARR region */ 495 496#define CCR6 0xea 497 498#define CCR7 0xeb 499 500/* Performance Control Register (5x86 only). */ 501#define PCR0 0x20 502#define PCR0_RSTK 0x01 /* Enables return stack */ 503#define PCR0_BTB 0x02 /* Enables branch target buffer */ 504#define PCR0_LOOP 0x04 /* Enables loop */ 505#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 506 serialize pipe. */ 507#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 508#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 509#define PCR0_LSSER 0x80 /* Disable reorder */ 510 511/* Device Identification Registers */ 512#define DIR0 0xfe 513#define DIR1 0xff 514 515/* 516 * Machine Check register constants. 517 */ 518#define MCG_CAP_COUNT 0x000000ff 519#define MCG_CAP_CTL_P 0x00000100 520#define MCG_CAP_EXT_P 0x00000200 521#define MCG_CAP_CMCI_P 0x00000400 522#define MCG_CAP_TES_P 0x00000800 523#define MCG_CAP_EXT_CNT 0x00ff0000 524#define MCG_CAP_SER_P 0x01000000 525#define MCG_STATUS_RIPV 0x00000001 526#define MCG_STATUS_EIPV 0x00000002 527#define MCG_STATUS_MCIP 0x00000004 528#define MCG_CTL_ENABLE 0xffffffffffffffff 529#define MCG_CTL_DISABLE 0x0000000000000000 530#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 531#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 532#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 533#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 534#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 535#define MC_STATUS_MCA_ERROR 0x000000000000ffff 536#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 537#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 538#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 539#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 540#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 541#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 542#define MC_STATUS_PCC 0x0200000000000000 543#define MC_STATUS_ADDRV 0x0400000000000000 544#define MC_STATUS_MISCV 0x0800000000000000 545#define MC_STATUS_EN 0x1000000000000000 546#define MC_STATUS_UC 0x2000000000000000 547#define MC_STATUS_OVER 0x4000000000000000 548#define MC_STATUS_VAL 0x8000000000000000 549#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 550#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 551#define MC_CTL2_THRESHOLD 0x0000000000007fff 552#define MC_CTL2_CMCI_EN 0x0000000040000000 553 554/* 555 * The following four 3-byte registers control the non-cacheable regions. 556 * These registers must be written as three separate bytes. 557 * 558 * NCRx+0: A31-A24 of starting address 559 * NCRx+1: A23-A16 of starting address 560 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 561 * 562 * The non-cacheable region's starting address must be aligned to the 563 * size indicated by the NCR_SIZE_xx field. 564 */ 565#define NCR1 0xc4 566#define NCR2 0xc7 567#define NCR3 0xca 568#define NCR4 0xcd 569 570#define NCR_SIZE_0K 0 571#define NCR_SIZE_4K 1 572#define NCR_SIZE_8K 2 573#define NCR_SIZE_16K 3 574#define NCR_SIZE_32K 4 575#define NCR_SIZE_64K 5 576#define NCR_SIZE_128K 6 577#define NCR_SIZE_256K 7 578#define NCR_SIZE_512K 8 579#define NCR_SIZE_1M 9 580#define NCR_SIZE_2M 10 581#define NCR_SIZE_4M 11 582#define NCR_SIZE_8M 12 583#define NCR_SIZE_16M 13 584#define NCR_SIZE_32M 14 585#define NCR_SIZE_4G 15 586 587/* 588 * The address region registers are used to specify the location and 589 * size for the eight address regions. 590 * 591 * ARRx + 0: A31-A24 of start address 592 * ARRx + 1: A23-A16 of start address 593 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 594 */ 595#define ARR0 0xc4 596#define ARR1 0xc7 597#define ARR2 0xca 598#define ARR3 0xcd 599#define ARR4 0xd0 600#define ARR5 0xd3 601#define ARR6 0xd6 602#define ARR7 0xd9 603 604#define ARR_SIZE_0K 0 605#define ARR_SIZE_4K 1 606#define ARR_SIZE_8K 2 607#define ARR_SIZE_16K 3 608#define ARR_SIZE_32K 4 609#define ARR_SIZE_64K 5 610#define ARR_SIZE_128K 6 611#define ARR_SIZE_256K 7 612#define ARR_SIZE_512K 8 613#define ARR_SIZE_1M 9 614#define ARR_SIZE_2M 10 615#define ARR_SIZE_4M 11 616#define ARR_SIZE_8M 12 617#define ARR_SIZE_16M 13 618#define ARR_SIZE_32M 14 619#define ARR_SIZE_4G 15 620 621/* 622 * The region control registers specify the attributes associated with 623 * the ARRx addres regions. 624 */ 625#define RCR0 0xdc 626#define RCR1 0xdd 627#define RCR2 0xde 628#define RCR3 0xdf 629#define RCR4 0xe0 630#define RCR5 0xe1 631#define RCR6 0xe2 632#define RCR7 0xe3 633 634#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 635#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 636#define RCR_WWO 0x02 /* Weak write ordering. */ 637#define RCR_WL 0x04 /* Weak locking. */ 638#define RCR_WG 0x08 /* Write gathering. */ 639#define RCR_WT 0x10 /* Write-through. */ 640#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 641 642/* AMD Write Allocate Top-Of-Memory and Control Register */ 643#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 644#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 645#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 646 647/* AMD64 MSR's */ 648#define MSR_EFER 0xc0000080 /* extended features */ 649#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 650#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 651#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 652#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 653#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 654#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 655#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 656#define MSR_PERFEVSEL0 0xc0010000 657#define MSR_PERFEVSEL1 0xc0010001 658#define MSR_PERFEVSEL2 0xc0010002 659#define MSR_PERFEVSEL3 0xc0010003 660#undef MSR_PERFCTR0 661#undef MSR_PERFCTR1 662#define MSR_PERFCTR0 0xc0010004 663#define MSR_PERFCTR1 0xc0010005 664#define MSR_PERFCTR2 0xc0010006 665#define MSR_PERFCTR3 0xc0010007 666#define MSR_SYSCFG 0xc0010010 667#define MSR_HWCR 0xc0010015 668#define MSR_IORRBASE0 0xc0010016 669#define MSR_IORRMASK0 0xc0010017 670#define MSR_IORRBASE1 0xc0010018 671#define MSR_IORRMASK1 0xc0010019 672#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 673#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 674#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 675#define MSR_MC0_CTL_MASK 0xc0010044 676 677/* VIA ACE crypto featureset: for via_feature_rng */ 678#define VIA_HAS_RNG 1 /* cpu has RNG */ 679 680/* VIA ACE crypto featureset: for via_feature_xcrypt */ 681#define VIA_HAS_AES 1 /* cpu has AES */ 682#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 683#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 684#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 685 686/* Centaur Extended Feature flags */ 687#define VIA_CPUID_HAS_RNG 0x000004 688#define VIA_CPUID_DO_RNG 0x000008 689#define VIA_CPUID_HAS_ACE 0x000040 690#define VIA_CPUID_DO_ACE 0x000080 691#define VIA_CPUID_HAS_ACE2 0x000100 692#define VIA_CPUID_DO_ACE2 0x000200 693#define VIA_CPUID_HAS_PHE 0x000400 694#define VIA_CPUID_DO_PHE 0x000800 695#define VIA_CPUID_HAS_PMM 0x001000 696#define VIA_CPUID_DO_PMM 0x002000 697 698/* VIA ACE xcrypt-* instruction context control options */ 699#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 700#define VIA_CRYPT_CWLO_ALG_M 0x00000070 701#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 702#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 703#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 704#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 705#define VIA_CRYPT_CWLO_NORMAL 0x00000000 706#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 707#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 708#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 709#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 710#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 711#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 712 713#endif /* !_MACHINE_SPECIALREG_H_ */ 714