specialreg.h revision 171854
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/i386/include/specialreg.h 171854 2007-08-15 19:26:03Z des $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55/* 56 * Bits in PPro special registers 57 */ 58#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60#define CR4_TSD 0x00000004 /* Time stamp disable */ 61#define CR4_DE 0x00000008 /* Debugging extensions */ 62#define CR4_PSE 0x00000010 /* Page size extensions */ 63#define CR4_PAE 0x00000020 /* Physical address extension */ 64#define CR4_MCE 0x00000040 /* Machine check enable */ 65#define CR4_PGE 0x00000080 /* Page global enable */ 66#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70/* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74 75/* 76 * CPUID instruction features register 77 */ 78#define CPUID_FPU 0x00000001 79#define CPUID_VME 0x00000002 80#define CPUID_DE 0x00000004 81#define CPUID_PSE 0x00000008 82#define CPUID_TSC 0x00000010 83#define CPUID_MSR 0x00000020 84#define CPUID_PAE 0x00000040 85#define CPUID_MCE 0x00000080 86#define CPUID_CX8 0x00000100 87#define CPUID_APIC 0x00000200 88#define CPUID_B10 0x00000400 89#define CPUID_SEP 0x00000800 90#define CPUID_MTRR 0x00001000 91#define CPUID_PGE 0x00002000 92#define CPUID_MCA 0x00004000 93#define CPUID_CMOV 0x00008000 94#define CPUID_PAT 0x00010000 95#define CPUID_PSE36 0x00020000 96#define CPUID_PSN 0x00040000 97#define CPUID_CLFSH 0x00080000 98#define CPUID_B20 0x00100000 99#define CPUID_DS 0x00200000 100#define CPUID_ACPI 0x00400000 101#define CPUID_MMX 0x00800000 102#define CPUID_FXSR 0x01000000 103#define CPUID_SSE 0x02000000 104#define CPUID_XMM 0x02000000 105#define CPUID_SSE2 0x04000000 106#define CPUID_SS 0x08000000 107#define CPUID_HTT 0x10000000 108#define CPUID_TM 0x20000000 109#define CPUID_IA64 0x40000000 110#define CPUID_PBE 0x80000000 111 112#define CPUID2_SSE3 0x00000001 113#define CPUID2_MON 0x00000008 114#define CPUID2_DS_CPL 0x00000010 115#define CPUID2_VMX 0x00000020 116#define CPUID2_SMX 0x00000040 117#define CPUID2_EST 0x00000080 118#define CPUID2_TM2 0x00000100 119#define CPUID2_SSSE3 0x00000200 120#define CPUID2_CNXTID 0x00000400 121#define CPUID2_CX16 0x00002000 122#define CPUID2_XTPR 0x00004000 123#define CPUID2_PDCM 0x00008000 124#define CPUID2_DCA 0x00040000 125 126/* 127 * Important bits in the AMD extended cpuid flags 128 */ 129#define AMDID_SYSCALL 0x00000800 130#define AMDID_MP 0x00080000 131#define AMDID_NX 0x00100000 132#define AMDID_EXT_MMX 0x00400000 133#define AMDID_FFXSR 0x01000000 134#define AMDID_RDTSCP 0x08000000 135#define AMDID_LM 0x20000000 136#define AMDID_EXT_3DNOW 0x40000000 137#define AMDID_3DNOW 0x80000000 138 139#define AMDID2_LAHF 0x00000001 140#define AMDID2_CMP 0x00000002 141#define AMDID2_SVM 0x00000004 142#define AMDID2_EXT_APIC 0x00000008 143#define AMDID2_CR8 0x00000010 144#define AMDID2_PREFETCH 0x00000100 145 146/* 147 * CPUID instruction 1 ebx info 148 */ 149#define CPUID_BRAND_INDEX 0x000000ff 150#define CPUID_CLFUSH_SIZE 0x0000ff00 151#define CPUID_HTT_CORES 0x00ff0000 152#define CPUID_LOCAL_APIC_ID 0xff000000 153 154/* 155 * AMD extended function 8000_0008h ecx info 156 */ 157#define AMDID_CMP_CORES 0x000000ff 158 159/* 160 * Model-specific registers for the i386 family 161 */ 162#define MSR_P5_MC_ADDR 0x000 163#define MSR_P5_MC_TYPE 0x001 164#define MSR_TSC 0x010 165#define MSR_P5_CESR 0x011 166#define MSR_P5_CTR0 0x012 167#define MSR_P5_CTR1 0x013 168#define MSR_IA32_PLATFORM_ID 0x017 169#define MSR_APICBASE 0x01b 170#define MSR_EBL_CR_POWERON 0x02a 171#define MSR_TEST_CTL 0x033 172#define MSR_BIOS_UPDT_TRIG 0x079 173#define MSR_BBL_CR_D0 0x088 174#define MSR_BBL_CR_D1 0x089 175#define MSR_BBL_CR_D2 0x08a 176#define MSR_BIOS_SIGN 0x08b 177#define MSR_PERFCTR0 0x0c1 178#define MSR_PERFCTR1 0x0c2 179#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 180#define MSR_MTRRcap 0x0fe 181#define MSR_BBL_CR_ADDR 0x116 182#define MSR_BBL_CR_DECC 0x118 183#define MSR_BBL_CR_CTL 0x119 184#define MSR_BBL_CR_TRIG 0x11a 185#define MSR_BBL_CR_BUSY 0x11b 186#define MSR_BBL_CR_CTL3 0x11e 187#define MSR_SYSENTER_CS_MSR 0x174 188#define MSR_SYSENTER_ESP_MSR 0x175 189#define MSR_SYSENTER_EIP_MSR 0x176 190#define MSR_MCG_CAP 0x179 191#define MSR_MCG_STATUS 0x17a 192#define MSR_MCG_CTL 0x17b 193#define MSR_EVNTSEL0 0x186 194#define MSR_EVNTSEL1 0x187 195#define MSR_THERM_CONTROL 0x19a 196#define MSR_THERM_INTERRUPT 0x19b 197#define MSR_THERM_STATUS 0x19c 198#define MSR_IA32_MISC_ENABLE 0x1a0 199#define MSR_DEBUGCTLMSR 0x1d9 200#define MSR_LASTBRANCHFROMIP 0x1db 201#define MSR_LASTBRANCHTOIP 0x1dc 202#define MSR_LASTINTFROMIP 0x1dd 203#define MSR_LASTINTTOIP 0x1de 204#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 205#define MSR_MTRRVarBase 0x200 206#define MSR_MTRR64kBase 0x250 207#define MSR_MTRR16kBase 0x258 208#define MSR_MTRR4kBase 0x268 209#define MSR_PAT 0x277 210#define MSR_MTRRdefType 0x2ff 211#define MSR_MC0_CTL 0x400 212#define MSR_MC0_STATUS 0x401 213#define MSR_MC0_ADDR 0x402 214#define MSR_MC0_MISC 0x403 215#define MSR_MC1_CTL 0x404 216#define MSR_MC1_STATUS 0x405 217#define MSR_MC1_ADDR 0x406 218#define MSR_MC1_MISC 0x407 219#define MSR_MC2_CTL 0x408 220#define MSR_MC2_STATUS 0x409 221#define MSR_MC2_ADDR 0x40a 222#define MSR_MC2_MISC 0x40b 223#define MSR_MC3_CTL 0x40c 224#define MSR_MC3_STATUS 0x40d 225#define MSR_MC3_ADDR 0x40e 226#define MSR_MC3_MISC 0x40f 227#define MSR_MC4_CTL 0x410 228#define MSR_MC4_STATUS 0x411 229#define MSR_MC4_ADDR 0x412 230#define MSR_MC4_MISC 0x413 231 232/* 233 * Constants related to MSR's. 234 */ 235#define APICBASE_RESERVED 0x000006ff 236#define APICBASE_BSP 0x00000100 237#define APICBASE_ENABLED 0x00000800 238#define APICBASE_ADDRESS 0xfffff000 239 240/* 241 * PAT modes. 242 */ 243#define PAT_UNCACHEABLE 0x00 244#define PAT_WRITE_COMBINING 0x01 245#define PAT_WRITE_THROUGH 0x04 246#define PAT_WRITE_PROTECTED 0x05 247#define PAT_WRITE_BACK 0x06 248#define PAT_UNCACHED 0x07 249#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 250#define PAT_MASK(i) PAT_VALUE(i, 0xff) 251 252/* 253 * Constants related to MTRRs 254 */ 255#define MTRR_N64K 8 /* numbers of fixed-size entries */ 256#define MTRR_N16K 16 257#define MTRR_N4K 64 258 259/* 260 * Cyrix configuration registers, accessible as IO ports. 261 */ 262#define CCR0 0xc0 /* Configuration control register 0 */ 263#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 264 non-cacheable */ 265#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 266#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 267#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 268#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 269#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 270 state */ 271#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 272 assoc */ 273#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 274 275#define CCR1 0xc1 /* Configuration control register 1 */ 276#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 277#define CCR1_SMI 0x02 /* Enables SMM pins */ 278#define CCR1_SMAC 0x04 /* System management memory access */ 279#define CCR1_MMAC 0x08 /* Main memory access */ 280#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 281#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 282 283#define CCR2 0xc2 284#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 285#define CCR2_SADS 0x02 /* Slow ADS */ 286#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 287#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 288#define CCR2_WT1 0x10 /* WT region 1 */ 289#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 290#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 291 hold state. */ 292#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 293#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 294 295#define CCR3 0xc3 296#define CCR3_SMILOCK 0x01 /* SMM register lock */ 297#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 298#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 299#define CCR3_SMMMODE 0x08 /* SMM Mode */ 300#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 301#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 302#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 303#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 304 305#define CCR4 0xe8 306#define CCR4_IOMASK 0x07 307#define CCR4_MEM 0x08 /* Enables momory bypassing */ 308#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 309#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 310#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 311 312#define CCR5 0xe9 313#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 314#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 315#define CCR5_LBR1 0x10 /* Local bus region 1 */ 316#define CCR5_ARREN 0x20 /* Enables ARR region */ 317 318#define CCR6 0xea 319 320#define CCR7 0xeb 321 322/* Performance Control Register (5x86 only). */ 323#define PCR0 0x20 324#define PCR0_RSTK 0x01 /* Enables return stack */ 325#define PCR0_BTB 0x02 /* Enables branch target buffer */ 326#define PCR0_LOOP 0x04 /* Enables loop */ 327#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 328 serialize pipe. */ 329#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 330#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 331#define PCR0_LSSER 0x80 /* Disable reorder */ 332 333/* Device Identification Registers */ 334#define DIR0 0xfe 335#define DIR1 0xff 336 337/* 338 * The following four 3-byte registers control the non-cacheable regions. 339 * These registers must be written as three separate bytes. 340 * 341 * NCRx+0: A31-A24 of starting address 342 * NCRx+1: A23-A16 of starting address 343 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 344 * 345 * The non-cacheable region's starting address must be aligned to the 346 * size indicated by the NCR_SIZE_xx field. 347 */ 348#define NCR1 0xc4 349#define NCR2 0xc7 350#define NCR3 0xca 351#define NCR4 0xcd 352 353#define NCR_SIZE_0K 0 354#define NCR_SIZE_4K 1 355#define NCR_SIZE_8K 2 356#define NCR_SIZE_16K 3 357#define NCR_SIZE_32K 4 358#define NCR_SIZE_64K 5 359#define NCR_SIZE_128K 6 360#define NCR_SIZE_256K 7 361#define NCR_SIZE_512K 8 362#define NCR_SIZE_1M 9 363#define NCR_SIZE_2M 10 364#define NCR_SIZE_4M 11 365#define NCR_SIZE_8M 12 366#define NCR_SIZE_16M 13 367#define NCR_SIZE_32M 14 368#define NCR_SIZE_4G 15 369 370/* 371 * The address region registers are used to specify the location and 372 * size for the eight address regions. 373 * 374 * ARRx + 0: A31-A24 of start address 375 * ARRx + 1: A23-A16 of start address 376 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 377 */ 378#define ARR0 0xc4 379#define ARR1 0xc7 380#define ARR2 0xca 381#define ARR3 0xcd 382#define ARR4 0xd0 383#define ARR5 0xd3 384#define ARR6 0xd6 385#define ARR7 0xd9 386 387#define ARR_SIZE_0K 0 388#define ARR_SIZE_4K 1 389#define ARR_SIZE_8K 2 390#define ARR_SIZE_16K 3 391#define ARR_SIZE_32K 4 392#define ARR_SIZE_64K 5 393#define ARR_SIZE_128K 6 394#define ARR_SIZE_256K 7 395#define ARR_SIZE_512K 8 396#define ARR_SIZE_1M 9 397#define ARR_SIZE_2M 10 398#define ARR_SIZE_4M 11 399#define ARR_SIZE_8M 12 400#define ARR_SIZE_16M 13 401#define ARR_SIZE_32M 14 402#define ARR_SIZE_4G 15 403 404/* 405 * The region control registers specify the attributes associated with 406 * the ARRx addres regions. 407 */ 408#define RCR0 0xdc 409#define RCR1 0xdd 410#define RCR2 0xde 411#define RCR3 0xdf 412#define RCR4 0xe0 413#define RCR5 0xe1 414#define RCR6 0xe2 415#define RCR7 0xe3 416 417#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 418#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 419#define RCR_WWO 0x02 /* Weak write ordering. */ 420#define RCR_WL 0x04 /* Weak locking. */ 421#define RCR_WG 0x08 /* Write gathering. */ 422#define RCR_WT 0x10 /* Write-through. */ 423#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 424 425/* AMD Write Allocate Top-Of-Memory and Control Register */ 426#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 427#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 428#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 429 430/* AMD64 MSR's */ 431#define MSR_EFER 0xc0000080 /* extended features */ 432 433/* VIA ACE crypto featureset: for via_feature_rng */ 434#define VIA_HAS_RNG 1 /* cpu has RNG */ 435 436/* VIA ACE crypto featureset: for via_feature_xcrypt */ 437#define VIA_HAS_AES 1 /* cpu has AES */ 438#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 439#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 440#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 441 442/* Centaur Extended Feature flags */ 443#define VIA_CPUID_HAS_RNG 0x000004 444#define VIA_CPUID_DO_RNG 0x000008 445#define VIA_CPUID_HAS_ACE 0x000040 446#define VIA_CPUID_DO_ACE 0x000080 447#define VIA_CPUID_HAS_ACE2 0x000100 448#define VIA_CPUID_DO_ACE2 0x000200 449#define VIA_CPUID_HAS_PHE 0x000400 450#define VIA_CPUID_DO_PHE 0x000800 451#define VIA_CPUID_HAS_PMM 0x001000 452#define VIA_CPUID_DO_PMM 0x002000 453 454/* VIA ACE xcrypt-* instruction context control options */ 455#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 456#define VIA_CRYPT_CWLO_ALG_M 0x00000070 457#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 458#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 459#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 460#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 461#define VIA_CRYPT_CWLO_NORMAL 0x00000000 462#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 463#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 464#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 465#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 466#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 467#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 468 469#ifndef LOCORE 470static __inline u_char 471read_cyrix_reg(u_char reg) 472{ 473 outb(0x22, reg); 474 return inb(0x23); 475} 476 477static __inline void 478write_cyrix_reg(u_char reg, u_char data) 479{ 480 outb(0x22, reg); 481 outb(0x23, data); 482} 483#endif 484 485#endif /* !_MACHINE_SPECIALREG_H_ */ 486