specialreg.h revision 21673
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 * $FreeBSD: head/sys/i386/include/specialreg.h 21673 1997-01-14 07:20:47Z jkh $ 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ 38#define _MACHINE_SPECIALREG_H_ 39 40/* 41 * Bits in 386 special registers: 42 */ 43#define CR0_PE 0x00000001 /* Protected mode Enable */ 44#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 45#ifdef notused 46#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 47#endif 48#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 49#ifdef notused 50#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 51#endif 52#define CR0_PG 0x80000000 /* PaGing enable */ 53 54/* 55 * Bits in 486 special registers: 56 */ 57#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 58#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ 59#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 60#define CR0_NW 0x20000000 /* Not Write-through */ 61#define CR0_CD 0x40000000 /* Cache Disable */ 62 63/* 64 * Bits in PPro special registers 65 */ 66#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 67#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 68#define CR4_TSD 0x00000004 /* Time stamp disable */ 69#define CR4_DE 0x00000008 /* Debugging extensions */ 70#define CR4_PSE 0x00000010 /* Page size extensions */ 71#define CR4_PAE 0x00000020 /* Physical address extension */ 72#define CR4_MCE 0x00000040 /* Machine check enable */ 73#define CR4_PGE 0x00000080 /* Page global enable */ 74#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 75 76/* 77 * CPUID instruction features register 78 */ 79#define CPUID_FPU 0x0001 80#define CPUID_VME 0x0002 81#define CPUID_DE 0x0004 82#define CPUID_PSE 0x0008 83#define CPUID_TSC 0x0010 84#define CPUID_MSR 0x0020 85#define CPUID_PAE 0x0040 86#define CPUID_MCE 0x0080 87#define CPUID_CX8 0x0100 88#define CPUID_APIC 0x0200 89#define CPUID_B10 0x0400 90#define CPUID_B11 0x0800 91#define CPUID_MTRR 0x1000 92#define CPUID_PGE 0x2000 93#define CPUID_MCA 0x4000 94#define CPUID_CMOV 0x8000 95 96/* 97 * Cyrix 486 DLC special registers, accessible as IO ports. 98 */ 99#define CCR0 0xc0 /* configuration control register 0 */ 100#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 101 non-cacheable */ 102#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 103#define CCR0_A20M 0x04 /* enables A20M# input pin */ 104#define CCR0_KEN 0x08 /* enables KEN# input pin */ 105#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 106#define CCR0_BARB 0x20 /* flushes internal cache when entering hold 107 state */ 108#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 109#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 110 111#define CCR1 0xc1 /* configuration control register 1 */ 112#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 113/* the remaining 7 bits of this register are reserved */ 114 115/* 116 * the following four 3-byte registers control the non-cacheable regions. 117 * These registers must be written as three separate bytes. 118 * 119 * NCRx+0: A31-A24 of starting address 120 * NCRx+1: A23-A16 of starting address 121 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 122 * 123 * The non-cacheable region's starting address must be aligned to the 124 * size indicated by the NCR_SIZE_xx field. 125 */ 126#define NCR1 0xc4 127#define NCR2 0xc7 128#define NCR3 0xca 129#define NCR4 0xcd 130 131#define NCR_SIZE_0K 0 132#define NCR_SIZE_4K 1 133#define NCR_SIZE_8K 2 134#define NCR_SIZE_16K 3 135#define NCR_SIZE_32K 4 136#define NCR_SIZE_64K 5 137#define NCR_SIZE_128K 6 138#define NCR_SIZE_256K 7 139#define NCR_SIZE_512K 8 140#define NCR_SIZE_1M 9 141#define NCR_SIZE_2M 10 142#define NCR_SIZE_4M 11 143#define NCR_SIZE_8M 12 144#define NCR_SIZE_16M 13 145#define NCR_SIZE_32M 14 146#define NCR_SIZE_4G 15 147 148#endif /* !_MACHINE_SPECIALREG_H_ */ 149