specialreg.h revision 167744
1281348Scy/*- 2281348Scy * Copyright (c) 1991 The Regents of the University of California. 3281348Scy * All rights reserved. 4281348Scy * 5281348Scy * Redistribution and use in source and binary forms, with or without 6281348Scy * modification, are permitted provided that the following conditions 7281348Scy * are met: 8281348Scy * 1. Redistributions of source code must retain the above copyright 9281348Scy * notice, this list of conditions and the following disclaimer. 10281348Scy * 2. Redistributions in binary form must reproduce the above copyright 11281348Scy * notice, this list of conditions and the following disclaimer in the 12281348Scy * documentation and/or other materials provided with the distribution. 13281348Scy * 4. Neither the name of the University nor the names of its contributors 14281348Scy * may be used to endorse or promote products derived from this software 15281348Scy * without specific prior written permission. 16281348Scy * 17281348Scy * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18281348Scy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19281348Scy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20281348Scy * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21281348Scy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22281348Scy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23281348Scy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24281348Scy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25281348Scy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26281348Scy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27281348Scy * SUCH DAMAGE. 28281348Scy * 29281348Scy * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30281348Scy * $FreeBSD: head/sys/i386/include/specialreg.h 167744 2007-03-20 20:22:45Z jkim $ 31281348Scy */ 32281348Scy 33281348Scy#ifndef _MACHINE_SPECIALREG_H_ 34281348Scy#define _MACHINE_SPECIALREG_H_ 35281348Scy 36281348Scy/* 37281348Scy * Bits in 386 special registers: 38281348Scy */ 39281348Scy#define CR0_PE 0x00000001 /* Protected mode Enable */ 40281348Scy#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41281348Scy#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42281348Scy#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43281348Scy#define CR0_PG 0x80000000 /* PaGing enable */ 44281348Scy 45281348Scy/* 46281348Scy * Bits in 486 special registers: 47281348Scy */ 48281348Scy#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49281348Scy#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50281348Scy all modes) */ 51281348Scy#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52281348Scy#define CR0_NW 0x20000000 /* Not Write-through */ 53281348Scy#define CR0_CD 0x40000000 /* Cache Disable */ 54281348Scy 55281348Scy/* 56281348Scy * Bits in PPro special registers 57281348Scy */ 58281348Scy#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59281348Scy#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60281348Scy#define CR4_TSD 0x00000004 /* Time stamp disable */ 61281348Scy#define CR4_DE 0x00000008 /* Debugging extensions */ 62281348Scy#define CR4_PSE 0x00000010 /* Page size extensions */ 63281348Scy#define CR4_PAE 0x00000020 /* Physical address extension */ 64281348Scy#define CR4_MCE 0x00000040 /* Machine check enable */ 65281348Scy#define CR4_PGE 0x00000080 /* Page global enable */ 66281348Scy#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67281348Scy#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68281348Scy#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69281348Scy 70281348Scy/* 71281348Scy * CPUID instruction features register 72281348Scy */ 73281348Scy#define CPUID_FPU 0x00000001 74281348Scy#define CPUID_VME 0x00000002 75281348Scy#define CPUID_DE 0x00000004 76281348Scy#define CPUID_PSE 0x00000008 77281348Scy#define CPUID_TSC 0x00000010 78281348Scy#define CPUID_MSR 0x00000020 79281348Scy#define CPUID_PAE 0x00000040 80281348Scy#define CPUID_MCE 0x00000080 81281348Scy#define CPUID_CX8 0x00000100 82281348Scy#define CPUID_APIC 0x00000200 83281348Scy#define CPUID_B10 0x00000400 84281348Scy#define CPUID_SEP 0x00000800 85281348Scy#define CPUID_MTRR 0x00001000 86281348Scy#define CPUID_PGE 0x00002000 87281348Scy#define CPUID_MCA 0x00004000 88281348Scy#define CPUID_CMOV 0x00008000 89281348Scy#define CPUID_PAT 0x00010000 90281348Scy#define CPUID_PSE36 0x00020000 91281348Scy#define CPUID_PSN 0x00040000 92281348Scy#define CPUID_CLFSH 0x00080000 93281348Scy#define CPUID_B20 0x00100000 94281348Scy#define CPUID_DS 0x00200000 95281348Scy#define CPUID_ACPI 0x00400000 96281348Scy#define CPUID_MMX 0x00800000 97281348Scy#define CPUID_FXSR 0x01000000 98281348Scy#define CPUID_SSE 0x02000000 99281348Scy#define CPUID_XMM 0x02000000 100281348Scy#define CPUID_SSE2 0x04000000 101281348Scy#define CPUID_SS 0x08000000 102281348Scy#define CPUID_HTT 0x10000000 103281348Scy#define CPUID_TM 0x20000000 104281348Scy#define CPUID_IA64 0x40000000 105281348Scy#define CPUID_PBE 0x80000000 106281348Scy 107281348Scy#define CPUID2_SSE3 0x00000001 108281348Scy#define CPUID2_MON 0x00000008 109281348Scy#define CPUID2_DS_CPL 0x00000010 110281348Scy#define CPUID2_VMX 0x00000020 111281348Scy#define CPUID2_SMX 0x00000040 112281348Scy#define CPUID2_EST 0x00000080 113281348Scy#define CPUID2_TM2 0x00000100 114281348Scy#define CPUID2_SSSE3 0x00000200 115281348Scy#define CPUID2_CNXTID 0x00000400 116281348Scy#define CPUID2_CX16 0x00002000 117281348Scy#define CPUID2_XTPR 0x00004000 118281348Scy#define CPUID2_DCA 0x00040000 119281348Scy 120281348Scy/* 121281348Scy * Important bits in the AMD extended cpuid flags 122281348Scy */ 123281348Scy#define AMDID_SYSCALL 0x00000800 124281348Scy#define AMDID_MP 0x00080000 125281348Scy#define AMDID_NX 0x00100000 126281348Scy#define AMDID_EXT_MMX 0x00400000 127281348Scy#define AMDID_FFXSR 0x01000000 128281348Scy#define AMDID_RDTSCP 0x08000000 129281348Scy#define AMDID_LM 0x20000000 130281348Scy#define AMDID_EXT_3DNOW 0x40000000 131281348Scy#define AMDID_3DNOW 0x80000000 132281348Scy 133281348Scy#define AMDID2_LAHF 0x00000001 134281348Scy#define AMDID2_CMP 0x00000002 135281348Scy#define AMDID2_SVM 0x00000004 136281348Scy#define AMDID2_EXT_APIC 0x00000008 137281348Scy#define AMDID2_CR8 0x00000010 138281348Scy#define AMDID2_PREFETCH 0x00000100 139281348Scy 140281348Scy/* 141281348Scy * CPUID instruction 1 ebx info 142281348Scy */ 143281348Scy#define CPUID_BRAND_INDEX 0x000000ff 144281348Scy#define CPUID_CLFUSH_SIZE 0x0000ff00 145281348Scy#define CPUID_HTT_CORES 0x00ff0000 146281348Scy#define CPUID_LOCAL_APIC_ID 0xff000000 147281348Scy 148281348Scy/* 149281348Scy * AMD extended function 8000_0008h ecx info 150281348Scy */ 151281348Scy#define AMDID_CMP_CORES 0x000000ff 152281348Scy 153281348Scy/* 154281348Scy * Model-specific registers for the i386 family 155281348Scy */ 156281348Scy#define MSR_P5_MC_ADDR 0x000 157281348Scy#define MSR_P5_MC_TYPE 0x001 158281348Scy#define MSR_TSC 0x010 159281348Scy#define MSR_P5_CESR 0x011 160281348Scy#define MSR_P5_CTR0 0x012 161281348Scy#define MSR_P5_CTR1 0x013 162281348Scy#define MSR_IA32_PLATFORM_ID 0x017 163281348Scy#define MSR_APICBASE 0x01b 164#define MSR_EBL_CR_POWERON 0x02a 165#define MSR_TEST_CTL 0x033 166#define MSR_BIOS_UPDT_TRIG 0x079 167#define MSR_BBL_CR_D0 0x088 168#define MSR_BBL_CR_D1 0x089 169#define MSR_BBL_CR_D2 0x08a 170#define MSR_BIOS_SIGN 0x08b 171#define MSR_PERFCTR0 0x0c1 172#define MSR_PERFCTR1 0x0c2 173#define MSR_MTRRcap 0x0fe 174#define MSR_BBL_CR_ADDR 0x116 175#define MSR_BBL_CR_DECC 0x118 176#define MSR_BBL_CR_CTL 0x119 177#define MSR_BBL_CR_TRIG 0x11a 178#define MSR_BBL_CR_BUSY 0x11b 179#define MSR_BBL_CR_CTL3 0x11e 180#define MSR_SYSENTER_CS_MSR 0x174 181#define MSR_SYSENTER_ESP_MSR 0x175 182#define MSR_SYSENTER_EIP_MSR 0x176 183#define MSR_MCG_CAP 0x179 184#define MSR_MCG_STATUS 0x17a 185#define MSR_MCG_CTL 0x17b 186#define MSR_EVNTSEL0 0x186 187#define MSR_EVNTSEL1 0x187 188#define MSR_THERM_CONTROL 0x19a 189#define MSR_THERM_INTERRUPT 0x19b 190#define MSR_THERM_STATUS 0x19c 191#define MSR_IA32_MISC_ENABLE 0x1a0 192#define MSR_DEBUGCTLMSR 0x1d9 193#define MSR_LASTBRANCHFROMIP 0x1db 194#define MSR_LASTBRANCHTOIP 0x1dc 195#define MSR_LASTINTFROMIP 0x1dd 196#define MSR_LASTINTTOIP 0x1de 197#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 198#define MSR_MTRRVarBase 0x200 199#define MSR_MTRR64kBase 0x250 200#define MSR_MTRR16kBase 0x258 201#define MSR_MTRR4kBase 0x268 202#define MSR_PAT 0x277 203#define MSR_MTRRdefType 0x2ff 204#define MSR_MC0_CTL 0x400 205#define MSR_MC0_STATUS 0x401 206#define MSR_MC0_ADDR 0x402 207#define MSR_MC0_MISC 0x403 208#define MSR_MC1_CTL 0x404 209#define MSR_MC1_STATUS 0x405 210#define MSR_MC1_ADDR 0x406 211#define MSR_MC1_MISC 0x407 212#define MSR_MC2_CTL 0x408 213#define MSR_MC2_STATUS 0x409 214#define MSR_MC2_ADDR 0x40a 215#define MSR_MC2_MISC 0x40b 216#define MSR_MC3_CTL 0x40c 217#define MSR_MC3_STATUS 0x40d 218#define MSR_MC3_ADDR 0x40e 219#define MSR_MC3_MISC 0x40f 220#define MSR_MC4_CTL 0x410 221#define MSR_MC4_STATUS 0x411 222#define MSR_MC4_ADDR 0x412 223#define MSR_MC4_MISC 0x413 224 225/* 226 * Constants related to MSR's. 227 */ 228#define APICBASE_RESERVED 0x000006ff 229#define APICBASE_BSP 0x00000100 230#define APICBASE_ENABLED 0x00000800 231#define APICBASE_ADDRESS 0xfffff000 232 233/* 234 * PAT modes. 235 */ 236#define PAT_UNCACHEABLE 0x00 237#define PAT_WRITE_COMBINING 0x01 238#define PAT_WRITE_THROUGH 0x04 239#define PAT_WRITE_PROTECTED 0x05 240#define PAT_WRITE_BACK 0x06 241#define PAT_UNCACHED 0x07 242#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 243#define PAT_MASK(i) PAT_VALUE(i, 0xff) 244 245/* 246 * Constants related to MTRRs 247 */ 248#define MTRR_N64K 8 /* numbers of fixed-size entries */ 249#define MTRR_N16K 16 250#define MTRR_N4K 64 251 252/* 253 * Cyrix configuration registers, accessible as IO ports. 254 */ 255#define CCR0 0xc0 /* Configuration control register 0 */ 256#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 257 non-cacheable */ 258#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 259#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 260#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 261#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 262#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 263 state */ 264#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 265 assoc */ 266#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 267 268#define CCR1 0xc1 /* Configuration control register 1 */ 269#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 270#define CCR1_SMI 0x02 /* Enables SMM pins */ 271#define CCR1_SMAC 0x04 /* System management memory access */ 272#define CCR1_MMAC 0x08 /* Main memory access */ 273#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 274#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 275 276#define CCR2 0xc2 277#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 278#define CCR2_SADS 0x02 /* Slow ADS */ 279#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 280#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 281#define CCR2_WT1 0x10 /* WT region 1 */ 282#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 283#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 284 hold state. */ 285#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 286#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 287 288#define CCR3 0xc3 289#define CCR3_SMILOCK 0x01 /* SMM register lock */ 290#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 291#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 292#define CCR3_SMMMODE 0x08 /* SMM Mode */ 293#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 294#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 295#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 296#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 297 298#define CCR4 0xe8 299#define CCR4_IOMASK 0x07 300#define CCR4_MEM 0x08 /* Enables momory bypassing */ 301#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 302#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 303#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 304 305#define CCR5 0xe9 306#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 307#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 308#define CCR5_LBR1 0x10 /* Local bus region 1 */ 309#define CCR5_ARREN 0x20 /* Enables ARR region */ 310 311#define CCR6 0xea 312 313#define CCR7 0xeb 314 315/* Performance Control Register (5x86 only). */ 316#define PCR0 0x20 317#define PCR0_RSTK 0x01 /* Enables return stack */ 318#define PCR0_BTB 0x02 /* Enables branch target buffer */ 319#define PCR0_LOOP 0x04 /* Enables loop */ 320#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 321 serialize pipe. */ 322#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 323#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 324#define PCR0_LSSER 0x80 /* Disable reorder */ 325 326/* Device Identification Registers */ 327#define DIR0 0xfe 328#define DIR1 0xff 329 330/* 331 * The following four 3-byte registers control the non-cacheable regions. 332 * These registers must be written as three separate bytes. 333 * 334 * NCRx+0: A31-A24 of starting address 335 * NCRx+1: A23-A16 of starting address 336 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 337 * 338 * The non-cacheable region's starting address must be aligned to the 339 * size indicated by the NCR_SIZE_xx field. 340 */ 341#define NCR1 0xc4 342#define NCR2 0xc7 343#define NCR3 0xca 344#define NCR4 0xcd 345 346#define NCR_SIZE_0K 0 347#define NCR_SIZE_4K 1 348#define NCR_SIZE_8K 2 349#define NCR_SIZE_16K 3 350#define NCR_SIZE_32K 4 351#define NCR_SIZE_64K 5 352#define NCR_SIZE_128K 6 353#define NCR_SIZE_256K 7 354#define NCR_SIZE_512K 8 355#define NCR_SIZE_1M 9 356#define NCR_SIZE_2M 10 357#define NCR_SIZE_4M 11 358#define NCR_SIZE_8M 12 359#define NCR_SIZE_16M 13 360#define NCR_SIZE_32M 14 361#define NCR_SIZE_4G 15 362 363/* 364 * The address region registers are used to specify the location and 365 * size for the eight address regions. 366 * 367 * ARRx + 0: A31-A24 of start address 368 * ARRx + 1: A23-A16 of start address 369 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 370 */ 371#define ARR0 0xc4 372#define ARR1 0xc7 373#define ARR2 0xca 374#define ARR3 0xcd 375#define ARR4 0xd0 376#define ARR5 0xd3 377#define ARR6 0xd6 378#define ARR7 0xd9 379 380#define ARR_SIZE_0K 0 381#define ARR_SIZE_4K 1 382#define ARR_SIZE_8K 2 383#define ARR_SIZE_16K 3 384#define ARR_SIZE_32K 4 385#define ARR_SIZE_64K 5 386#define ARR_SIZE_128K 6 387#define ARR_SIZE_256K 7 388#define ARR_SIZE_512K 8 389#define ARR_SIZE_1M 9 390#define ARR_SIZE_2M 10 391#define ARR_SIZE_4M 11 392#define ARR_SIZE_8M 12 393#define ARR_SIZE_16M 13 394#define ARR_SIZE_32M 14 395#define ARR_SIZE_4G 15 396 397/* 398 * The region control registers specify the attributes associated with 399 * the ARRx addres regions. 400 */ 401#define RCR0 0xdc 402#define RCR1 0xdd 403#define RCR2 0xde 404#define RCR3 0xdf 405#define RCR4 0xe0 406#define RCR5 0xe1 407#define RCR6 0xe2 408#define RCR7 0xe3 409 410#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 411#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 412#define RCR_WWO 0x02 /* Weak write ordering. */ 413#define RCR_WL 0x04 /* Weak locking. */ 414#define RCR_WG 0x08 /* Write gathering. */ 415#define RCR_WT 0x10 /* Write-through. */ 416#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 417 418/* AMD Write Allocate Top-Of-Memory and Control Register */ 419#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 420#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 421#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 422 423/* VIA ACE crypto featureset: for via_feature_rng */ 424#define VIA_HAS_RNG 1 /* cpu has RNG */ 425 426/* VIA ACE crypto featureset: for via_feature_xcrypt */ 427#define VIA_HAS_AES 1 /* cpu has AES */ 428#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 429#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 430#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 431 432/* Centaur Extended Feature flags */ 433#define VIA_CPUID_HAS_RNG 0x000004 434#define VIA_CPUID_DO_RNG 0x000008 435#define VIA_CPUID_HAS_ACE 0x000040 436#define VIA_CPUID_DO_ACE 0x000080 437#define VIA_CPUID_HAS_ACE2 0x000100 438#define VIA_CPUID_DO_ACE2 0x000200 439#define VIA_CPUID_HAS_PHE 0x000400 440#define VIA_CPUID_DO_PHE 0x000800 441#define VIA_CPUID_HAS_PMM 0x001000 442#define VIA_CPUID_DO_PMM 0x002000 443 444/* VIA ACE xcrypt-* instruction context control options */ 445#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 446#define VIA_CRYPT_CWLO_ALG_M 0x00000070 447#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 448#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 449#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 450#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 451#define VIA_CRYPT_CWLO_NORMAL 0x00000000 452#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 453#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 454#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 455#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 456#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 457#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 458 459#ifndef LOCORE 460static __inline u_char 461read_cyrix_reg(u_char reg) 462{ 463 outb(0x22, reg); 464 return inb(0x23); 465} 466 467static __inline void 468write_cyrix_reg(u_char reg, u_char data) 469{ 470 outb(0x22, reg); 471 outb(0x23, data); 472} 473#endif 474 475#endif /* !_MACHINE_SPECIALREG_H_ */ 476