specialreg.h revision 205214
1191983Sweongyo/*- 2191983Sweongyo * Copyright (c) 1991 The Regents of the University of California. 3191983Sweongyo * All rights reserved. 4191983Sweongyo * 5191983Sweongyo * Redistribution and use in source and binary forms, with or without 6191983Sweongyo * modification, are permitted provided that the following conditions 7191983Sweongyo * are met: 8191983Sweongyo * 1. Redistributions of source code must retain the above copyright 9191983Sweongyo * notice, this list of conditions and the following disclaimer. 10191983Sweongyo * 2. Redistributions in binary form must reproduce the above copyright 11191983Sweongyo * notice, this list of conditions and the following disclaimer in the 12191983Sweongyo * documentation and/or other materials provided with the distribution. 13191983Sweongyo * 4. Neither the name of the University nor the names of its contributors 14191983Sweongyo * may be used to endorse or promote products derived from this software 15191983Sweongyo * without specific prior written permission. 16191983Sweongyo * 17191983Sweongyo * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18191983Sweongyo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19191983Sweongyo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20191983Sweongyo * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21191983Sweongyo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22191983Sweongyo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23191983Sweongyo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24191983Sweongyo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25191983Sweongyo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26191983Sweongyo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27191983Sweongyo * SUCH DAMAGE. 28191983Sweongyo * 29191983Sweongyo * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30191983Sweongyo * $FreeBSD: head/sys/i386/include/specialreg.h 205214 2010-03-16 16:01:19Z jhb $ 31191983Sweongyo */ 32191983Sweongyo 33191983Sweongyo#ifndef _MACHINE_SPECIALREG_H_ 34191983Sweongyo#define _MACHINE_SPECIALREG_H_ 35191983Sweongyo 36191983Sweongyo/* 37191983Sweongyo * Bits in 386 special registers: 38191983Sweongyo */ 39191983Sweongyo#define CR0_PE 0x00000001 /* Protected mode Enable */ 40191983Sweongyo#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41191983Sweongyo#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42191983Sweongyo#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43191983Sweongyo#define CR0_PG 0x80000000 /* PaGing enable */ 44191983Sweongyo 45191983Sweongyo/* 46191983Sweongyo * Bits in 486 special registers: 47191983Sweongyo */ 48191983Sweongyo#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49191983Sweongyo#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50191983Sweongyo all modes) */ 51194677Sthompsa#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52191983Sweongyo#define CR0_NW 0x20000000 /* Not Write-through */ 53191983Sweongyo#define CR0_CD 0x40000000 /* Cache Disable */ 54191983Sweongyo 55191983Sweongyo/* 56191983Sweongyo * Bits in PPro special registers 57191983Sweongyo */ 58191983Sweongyo#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59191983Sweongyo#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60191983Sweongyo#define CR4_TSD 0x00000004 /* Time stamp disable */ 61191983Sweongyo#define CR4_DE 0x00000008 /* Debugging extensions */ 62191983Sweongyo#define CR4_PSE 0x00000010 /* Page size extensions */ 63191983Sweongyo#define CR4_PAE 0x00000020 /* Physical address extension */ 64191983Sweongyo#define CR4_MCE 0x00000040 /* Machine check enable */ 65191983Sweongyo#define CR4_PGE 0x00000080 /* Page global enable */ 66191983Sweongyo#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67191983Sweongyo#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68191983Sweongyo#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69191983Sweongyo 70191983Sweongyo/* 71191983Sweongyo * Bits in AMD64 special registers. EFER is 64 bits wide. 72191983Sweongyo */ 73227309Sed#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74191983Sweongyo 75191983Sweongyo/* 76191983Sweongyo * CPUID instruction features register 77191983Sweongyo */ 78242126Shselasky#define CPUID_FPU 0x00000001 79191983Sweongyo#define CPUID_VME 0x00000002 80191983Sweongyo#define CPUID_DE 0x00000004 81191983Sweongyo#define CPUID_PSE 0x00000008 82191983Sweongyo#define CPUID_TSC 0x00000010 83191983Sweongyo#define CPUID_MSR 0x00000020 84191983Sweongyo#define CPUID_PAE 0x00000040 85191983Sweongyo#define CPUID_MCE 0x00000080 86191983Sweongyo#define CPUID_CX8 0x00000100 87191983Sweongyo#define CPUID_APIC 0x00000200 88191983Sweongyo#define CPUID_B10 0x00000400 89191983Sweongyo#define CPUID_SEP 0x00000800 90191983Sweongyo#define CPUID_MTRR 0x00001000 91191983Sweongyo#define CPUID_PGE 0x00002000 92191983Sweongyo#define CPUID_MCA 0x00004000 93191983Sweongyo#define CPUID_CMOV 0x00008000 94191983Sweongyo#define CPUID_PAT 0x00010000 95191983Sweongyo#define CPUID_PSE36 0x00020000 96191983Sweongyo#define CPUID_PSN 0x00040000 97191983Sweongyo#define CPUID_CLFSH 0x00080000 98191983Sweongyo#define CPUID_B20 0x00100000 99191983Sweongyo#define CPUID_DS 0x00200000 100191983Sweongyo#define CPUID_ACPI 0x00400000 101191983Sweongyo#define CPUID_MMX 0x00800000 102191983Sweongyo#define CPUID_FXSR 0x01000000 103191983Sweongyo#define CPUID_SSE 0x02000000 104191983Sweongyo#define CPUID_XMM 0x02000000 105191983Sweongyo#define CPUID_SSE2 0x04000000 106191983Sweongyo#define CPUID_SS 0x08000000 107191983Sweongyo#define CPUID_HTT 0x10000000 108191983Sweongyo#define CPUID_TM 0x20000000 109191983Sweongyo#define CPUID_IA64 0x40000000 110191983Sweongyo#define CPUID_PBE 0x80000000 111191983Sweongyo 112191983Sweongyo#define CPUID2_SSE3 0x00000001 113191983Sweongyo#define CPUID2_DTES64 0x00000004 114191983Sweongyo#define CPUID2_MON 0x00000008 115191983Sweongyo#define CPUID2_DS_CPL 0x00000010 116191983Sweongyo#define CPUID2_VMX 0x00000020 117191983Sweongyo#define CPUID2_SMX 0x00000040 118191983Sweongyo#define CPUID2_EST 0x00000080 119192984Sthompsa#define CPUID2_TM2 0x00000100 120191983Sweongyo#define CPUID2_SSSE3 0x00000200 121191983Sweongyo#define CPUID2_CNXTID 0x00000400 122192984Sthompsa#define CPUID2_CX16 0x00002000 123191983Sweongyo#define CPUID2_XTPR 0x00004000 124191983Sweongyo#define CPUID2_PDCM 0x00008000 125191983Sweongyo#define CPUID2_DCA 0x00040000 126191983Sweongyo#define CPUID2_SSE41 0x00080000 127191983Sweongyo#define CPUID2_SSE42 0x00100000 128191983Sweongyo#define CPUID2_X2APIC 0x00200000 129191983Sweongyo#define CPUID2_MOVBE 0x00400000 130191983Sweongyo#define CPUID2_POPCNT 0x00800000 131191983Sweongyo 132191983Sweongyo/* 133191983Sweongyo * Important bits in the AMD extended cpuid flags 134191983Sweongyo */ 135191983Sweongyo#define AMDID_SYSCALL 0x00000800 136191983Sweongyo#define AMDID_MP 0x00080000 137191983Sweongyo#define AMDID_NX 0x00100000 138191983Sweongyo#define AMDID_EXT_MMX 0x00400000 139191983Sweongyo#define AMDID_FFXSR 0x01000000 140191983Sweongyo#define AMDID_PAGE1GB 0x04000000 141228621Sbschmidt#define AMDID_RDTSCP 0x08000000 142228621Sbschmidt#define AMDID_LM 0x20000000 143228621Sbschmidt#define AMDID_EXT_3DNOW 0x40000000 144191983Sweongyo#define AMDID_3DNOW 0x80000000 145191983Sweongyo 146191983Sweongyo#define AMDID2_LAHF 0x00000001 147191983Sweongyo#define AMDID2_CMP 0x00000002 148191983Sweongyo#define AMDID2_SVM 0x00000004 149191983Sweongyo#define AMDID2_EXT_APIC 0x00000008 150191983Sweongyo#define AMDID2_CR8 0x00000010 151191983Sweongyo#define AMDID2_ABM 0x00000020 152191983Sweongyo#define AMDID2_SSE4A 0x00000040 153191983Sweongyo#define AMDID2_MAS 0x00000080 154191983Sweongyo#define AMDID2_PREFETCH 0x00000100 155191983Sweongyo#define AMDID2_OSVW 0x00000200 156191983Sweongyo#define AMDID2_IBS 0x00000400 157191983Sweongyo#define AMDID2_SSE5 0x00000800 158191983Sweongyo#define AMDID2_SKINIT 0x00001000 159191983Sweongyo#define AMDID2_WDT 0x00002000 160191983Sweongyo 161191983Sweongyo/* 162191983Sweongyo * CPUID instruction 1 eax info 163191983Sweongyo */ 164191983Sweongyo#define CPUID_STEPPING 0x0000000f 165191983Sweongyo#define CPUID_MODEL 0x000000f0 166191983Sweongyo#define CPUID_FAMILY 0x00000f00 167191983Sweongyo#define CPUID_EXT_MODEL 0x000f0000 168191983Sweongyo#define CPUID_EXT_FAMILY 0x0ff00000 169191983Sweongyo#define CPUID_TO_MODEL(id) \ 170191983Sweongyo ((((id) & CPUID_MODEL) >> 4) | \ 171191983Sweongyo ((((id) & CPUID_FAMILY) >= 0x600) ? \ 172191983Sweongyo (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 173223486Shselasky#define CPUID_TO_FAMILY(id) \ 174191983Sweongyo ((((id) & CPUID_FAMILY) >> 8) + \ 175191983Sweongyo ((((id) & CPUID_FAMILY) == 0xf00) ? \ 176191983Sweongyo (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 177191983Sweongyo 178191983Sweongyo/* 179191983Sweongyo * CPUID instruction 1 ebx info 180191983Sweongyo */ 181191983Sweongyo#define CPUID_BRAND_INDEX 0x000000ff 182191983Sweongyo#define CPUID_CLFUSH_SIZE 0x0000ff00 183191983Sweongyo#define CPUID_HTT_CORES 0x00ff0000 184191983Sweongyo#define CPUID_LOCAL_APIC_ID 0xff000000 185213804Shselasky 186191983Sweongyo/* 187191983Sweongyo * CPUID instruction 0xb ebx info. 188209447Sthompsa */ 189191983Sweongyo#define CPUID_TYPE_INVAL 0 190191983Sweongyo#define CPUID_TYPE_SMT 1 191191983Sweongyo#define CPUID_TYPE_CORE 2 192191983Sweongyo 193191983Sweongyo/* 194191983Sweongyo * AMD extended function 8000_0007h edx info 195191983Sweongyo */ 196193045Sthompsa#define AMDPM_TS 0x00000001 197193045Sthompsa#define AMDPM_FID 0x00000002 198191983Sweongyo#define AMDPM_VID 0x00000004 199192984Sthompsa#define AMDPM_TTP 0x00000008 200191983Sweongyo#define AMDPM_TM 0x00000010 201191983Sweongyo#define AMDPM_STC 0x00000020 202191983Sweongyo#define AMDPM_100MHZ_STEPS 0x00000040 203191983Sweongyo#define AMDPM_HW_PSTATE 0x00000080 204191983Sweongyo#define AMDPM_TSC_INVARIANT 0x00000100 205191983Sweongyo 206191983Sweongyo/* 207191983Sweongyo * AMD extended function 8000_0008h ecx info 208191983Sweongyo */ 209191983Sweongyo#define AMDID_CMP_CORES 0x000000ff 210191983Sweongyo 211191983Sweongyo/* 212191983Sweongyo * CPUID manufacturers identifiers 213191983Sweongyo */ 214191983Sweongyo#define AMD_VENDOR_ID "AuthenticAMD" 215191983Sweongyo#define CENTAUR_VENDOR_ID "CentaurHauls" 216191983Sweongyo#define CYRIX_VENDOR_ID "CyrixInstead" 217191983Sweongyo#define INTEL_VENDOR_ID "GenuineIntel" 218191983Sweongyo#define NEXGEN_VENDOR_ID "NexGenDriven" 219191983Sweongyo#define NSC_VENDOR_ID "Geode by NSC" 220191983Sweongyo#define RISE_VENDOR_ID "RiseRiseRise" 221191983Sweongyo#define SIS_VENDOR_ID "SiS SiS SiS " 222191983Sweongyo#define TRANSMETA_VENDOR_ID "GenuineTMx86" 223191983Sweongyo#define UMC_VENDOR_ID "UMC UMC UMC " 224191983Sweongyo 225191983Sweongyo/* 226191983Sweongyo * Model-specific registers for the i386 family 227191983Sweongyo */ 228191983Sweongyo#define MSR_P5_MC_ADDR 0x000 229191983Sweongyo#define MSR_P5_MC_TYPE 0x001 230192984Sthompsa#define MSR_TSC 0x010 231191983Sweongyo#define MSR_P5_CESR 0x011 232192499Sthompsa#define MSR_P5_CTR0 0x012 233191983Sweongyo#define MSR_P5_CTR1 0x013 234191983Sweongyo#define MSR_IA32_PLATFORM_ID 0x017 235191983Sweongyo#define MSR_APICBASE 0x01b 236191983Sweongyo#define MSR_EBL_CR_POWERON 0x02a 237191983Sweongyo#define MSR_TEST_CTL 0x033 238191983Sweongyo#define MSR_BIOS_UPDT_TRIG 0x079 239223486Shselasky#define MSR_BBL_CR_D0 0x088 240191983Sweongyo#define MSR_BBL_CR_D1 0x089 241191983Sweongyo#define MSR_BBL_CR_D2 0x08a 242191983Sweongyo#define MSR_BIOS_SIGN 0x08b 243191983Sweongyo#define MSR_PERFCTR0 0x0c1 244191983Sweongyo#define MSR_PERFCTR1 0x0c2 245191983Sweongyo#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 246191983Sweongyo#define MSR_MTRRcap 0x0fe 247191983Sweongyo#define MSR_BBL_CR_ADDR 0x116 248191983Sweongyo#define MSR_BBL_CR_DECC 0x118 249192984Sthompsa#define MSR_BBL_CR_CTL 0x119 250191983Sweongyo#define MSR_BBL_CR_TRIG 0x11a 251191983Sweongyo#define MSR_BBL_CR_BUSY 0x11b 252191983Sweongyo#define MSR_BBL_CR_CTL3 0x11e 253191983Sweongyo#define MSR_SYSENTER_CS_MSR 0x174 254191983Sweongyo#define MSR_SYSENTER_ESP_MSR 0x175 255191983Sweongyo#define MSR_SYSENTER_EIP_MSR 0x176 256191983Sweongyo#define MSR_MCG_CAP 0x179 257194228Sthompsa#define MSR_MCG_STATUS 0x17a 258191983Sweongyo#define MSR_MCG_CTL 0x17b 259191983Sweongyo#define MSR_EVNTSEL0 0x186 260191983Sweongyo#define MSR_EVNTSEL1 0x187 261191983Sweongyo#define MSR_THERM_CONTROL 0x19a 262191983Sweongyo#define MSR_THERM_INTERRUPT 0x19b 263191983Sweongyo#define MSR_THERM_STATUS 0x19c 264191983Sweongyo#define MSR_IA32_MISC_ENABLE 0x1a0 265191983Sweongyo#define MSR_DEBUGCTLMSR 0x1d9 266191983Sweongyo#define MSR_LASTBRANCHFROMIP 0x1db 267191983Sweongyo#define MSR_LASTBRANCHTOIP 0x1dc 268191983Sweongyo#define MSR_LASTINTFROMIP 0x1dd 269191983Sweongyo#define MSR_LASTINTTOIP 0x1de 270191983Sweongyo#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 271191983Sweongyo#define MSR_MTRRVarBase 0x200 272194228Sthompsa#define MSR_MTRR64kBase 0x250 273191983Sweongyo#define MSR_MTRR16kBase 0x258 274191983Sweongyo#define MSR_MTRR4kBase 0x268 275191983Sweongyo#define MSR_PAT 0x277 276194228Sthompsa#define MSR_MC0_CTL2 0x280 277191983Sweongyo#define MSR_MTRRdefType 0x2ff 278191983Sweongyo#define MSR_MC0_CTL 0x400 279191983Sweongyo#define MSR_MC0_STATUS 0x401 280191983Sweongyo#define MSR_MC0_ADDR 0x402 281191983Sweongyo#define MSR_MC0_MISC 0x403 282191983Sweongyo#define MSR_MC1_CTL 0x404 283191983Sweongyo#define MSR_MC1_STATUS 0x405 284191983Sweongyo#define MSR_MC1_ADDR 0x406 285191983Sweongyo#define MSR_MC1_MISC 0x407 286191983Sweongyo#define MSR_MC2_CTL 0x408 287191983Sweongyo#define MSR_MC2_STATUS 0x409 288191983Sweongyo#define MSR_MC2_ADDR 0x40a 289191983Sweongyo#define MSR_MC2_MISC 0x40b 290191983Sweongyo#define MSR_MC3_CTL 0x40c 291191983Sweongyo#define MSR_MC3_STATUS 0x40d 292191983Sweongyo#define MSR_MC3_ADDR 0x40e 293191983Sweongyo#define MSR_MC3_MISC 0x40f 294191983Sweongyo#define MSR_MC4_CTL 0x410 295191983Sweongyo#define MSR_MC4_STATUS 0x411 296191983Sweongyo#define MSR_MC4_ADDR 0x412 297199816Sthompsa#define MSR_MC4_MISC 0x413 298191983Sweongyo 299191983Sweongyo/* 300191983Sweongyo * Constants related to MSR's. 301191983Sweongyo */ 302191983Sweongyo#define APICBASE_RESERVED 0x000006ff 303191983Sweongyo#define APICBASE_BSP 0x00000100 304191983Sweongyo#define APICBASE_ENABLED 0x00000800 305191983Sweongyo#define APICBASE_ADDRESS 0xfffff000 306191983Sweongyo 307191983Sweongyo/* 308191983Sweongyo * PAT modes. 309191983Sweongyo */ 310191983Sweongyo#define PAT_UNCACHEABLE 0x00 311191983Sweongyo#define PAT_WRITE_COMBINING 0x01 312191983Sweongyo#define PAT_WRITE_THROUGH 0x04 313191983Sweongyo#define PAT_WRITE_PROTECTED 0x05 314191983Sweongyo#define PAT_WRITE_BACK 0x06 315191983Sweongyo#define PAT_UNCACHED 0x07 316191983Sweongyo#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 317191983Sweongyo#define PAT_MASK(i) PAT_VALUE(i, 0xff) 318191983Sweongyo 319191983Sweongyo/* 320191983Sweongyo * Constants related to MTRRs 321191983Sweongyo */ 322191983Sweongyo#define MTRR_UNCACHEABLE 0x00 323191983Sweongyo#define MTRR_WRITE_COMBINING 0x01 324191983Sweongyo#define MTRR_WRITE_THROUGH 0x04 325191983Sweongyo#define MTRR_WRITE_PROTECTED 0x05 326191983Sweongyo#define MTRR_WRITE_BACK 0x06 327191983Sweongyo#define MTRR_N64K 8 /* numbers of fixed-size entries */ 328191983Sweongyo#define MTRR_N16K 16 329191983Sweongyo#define MTRR_N4K 64 330191983Sweongyo#define MTRR_CAP_WC 0x0000000000000400ULL 331191983Sweongyo#define MTRR_CAP_FIXED 0x0000000000000100ULL 332191983Sweongyo#define MTRR_CAP_VCNT 0x00000000000000ffULL 333191983Sweongyo#define MTRR_DEF_ENABLE 0x0000000000000800ULL 334191983Sweongyo#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL 335191983Sweongyo#define MTRR_DEF_TYPE 0x00000000000000ffULL 336207554Ssobomax#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL 337191983Sweongyo#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL 338191983Sweongyo#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL 339191983Sweongyo#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL 340191983Sweongyo 341191983Sweongyo/* 342191983Sweongyo * Cyrix configuration registers, accessible as IO ports. 343191983Sweongyo */ 344191983Sweongyo#define CCR0 0xc0 /* Configuration control register 0 */ 345191983Sweongyo#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 346191983Sweongyo non-cacheable */ 347191983Sweongyo#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 348191983Sweongyo#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 349191983Sweongyo#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 350191983Sweongyo#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 351191983Sweongyo#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 352191983Sweongyo state */ 353191983Sweongyo#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 354191983Sweongyo assoc */ 355191983Sweongyo#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 356191983Sweongyo 357191983Sweongyo#define CCR1 0xc1 /* Configuration control register 1 */ 358191983Sweongyo#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 359191983Sweongyo#define CCR1_SMI 0x02 /* Enables SMM pins */ 360191983Sweongyo#define CCR1_SMAC 0x04 /* System management memory access */ 361191983Sweongyo#define CCR1_MMAC 0x08 /* Main memory access */ 362191983Sweongyo#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 363191983Sweongyo#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 364191983Sweongyo 365191983Sweongyo#define CCR2 0xc2 366191983Sweongyo#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 367191983Sweongyo#define CCR2_SADS 0x02 /* Slow ADS */ 368192468Ssam#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 369192468Ssam#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 370192468Ssam#define CCR2_WT1 0x10 /* WT region 1 */ 371192468Ssam#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 372192468Ssam#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 373191983Sweongyo hold state. */ 374191983Sweongyo#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 375191983Sweongyo#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 376191983Sweongyo 377191983Sweongyo#define CCR3 0xc3 378191983Sweongyo#define CCR3_SMILOCK 0x01 /* SMM register lock */ 379191983Sweongyo#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 380191983Sweongyo#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 381191983Sweongyo#define CCR3_SMMMODE 0x08 /* SMM Mode */ 382194228Sthompsa#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 383191983Sweongyo#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 384191983Sweongyo#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 385191983Sweongyo#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 386191983Sweongyo 387191983Sweongyo#define CCR4 0xe8 388191983Sweongyo#define CCR4_IOMASK 0x07 389191983Sweongyo#define CCR4_MEM 0x08 /* Enables momory bypassing */ 390191983Sweongyo#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 391192984Sthompsa#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 392191983Sweongyo#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 393194677Sthompsa 394191983Sweongyo#define CCR5 0xe9 395191983Sweongyo#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 396191983Sweongyo#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 397191983Sweongyo#define CCR5_LBR1 0x10 /* Local bus region 1 */ 398191983Sweongyo#define CCR5_ARREN 0x20 /* Enables ARR region */ 399191983Sweongyo 400191983Sweongyo#define CCR6 0xea 401191983Sweongyo 402191983Sweongyo#define CCR7 0xeb 403191983Sweongyo 404191983Sweongyo/* Performance Control Register (5x86 only). */ 405191983Sweongyo#define PCR0 0x20 406191983Sweongyo#define PCR0_RSTK 0x01 /* Enables return stack */ 407191983Sweongyo#define PCR0_BTB 0x02 /* Enables branch target buffer */ 408191983Sweongyo#define PCR0_LOOP 0x04 /* Enables loop */ 409191983Sweongyo#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 410191983Sweongyo serialize pipe. */ 411191983Sweongyo#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 412191983Sweongyo#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 413191983Sweongyo#define PCR0_LSSER 0x80 /* Disable reorder */ 414191983Sweongyo 415191983Sweongyo/* Device Identification Registers */ 416191983Sweongyo#define DIR0 0xfe 417191983Sweongyo#define DIR1 0xff 418191983Sweongyo 419191983Sweongyo/* 420191983Sweongyo * Machine Check register constants. 421191983Sweongyo */ 422191983Sweongyo#define MCG_CAP_COUNT 0x000000ff 423191983Sweongyo#define MCG_CAP_CTL_P 0x00000100 424191983Sweongyo#define MCG_CAP_EXT_P 0x00000200 425191983Sweongyo#define MCG_CAP_CMCI_P 0x00000400 426191983Sweongyo#define MCG_CAP_TES_P 0x00000800 427191983Sweongyo#define MCG_CAP_EXT_CNT 0x00ff0000 428191983Sweongyo#define MCG_CAP_SER_P 0x01000000 429191983Sweongyo#define MCG_STATUS_RIPV 0x00000001 430191983Sweongyo#define MCG_STATUS_EIPV 0x00000002 431191983Sweongyo#define MCG_STATUS_MCIP 0x00000004 432191983Sweongyo#define MCG_CTL_ENABLE 0xffffffffffffffffULL 433191983Sweongyo#define MCG_CTL_DISABLE 0x0000000000000000ULL 434191983Sweongyo#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 435227461Shselasky#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 436191983Sweongyo#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 437191983Sweongyo#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 438191983Sweongyo#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 439191983Sweongyo#define MC_STATUS_MCA_ERROR 0x000000000000ffffULL 440191983Sweongyo#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000ULL 441191983Sweongyo#define MC_STATUS_OTHER_INFO 0x01ffffff00000000ULL 442191983Sweongyo#define MC_STATUS_COR_COUNT 0x001fffc000000000ULL /* If MCG_CAP_TES_P */ 443191983Sweongyo#define MC_STATUS_TES_STATUS 0x0060000000000000ULL /* If MCG_CAP_TES_P */ 444191983Sweongyo#define MC_STATUS_AR 0x0080000000000000ULL /* If MCG_CAP_CMCI_P */ 445191983Sweongyo#define MC_STATUS_S 0x0100000000000000ULL /* If MCG_CAP_CMCI_P */ 446191983Sweongyo#define MC_STATUS_PCC 0x0200000000000000ULL 447191983Sweongyo#define MC_STATUS_ADDRV 0x0400000000000000ULL 448191983Sweongyo#define MC_STATUS_MISCV 0x0800000000000000ULL 449191983Sweongyo#define MC_STATUS_EN 0x1000000000000000ULL 450191983Sweongyo#define MC_STATUS_UC 0x2000000000000000ULL 451191983Sweongyo#define MC_STATUS_OVER 0x4000000000000000ULL 452191983Sweongyo#define MC_STATUS_VAL 0x8000000000000000ULL 453191983Sweongyo#define MC_MISC_RA_LSB 0x000000000000003fULL /* If MCG_CAP_SER_P */ 454191983Sweongyo#define MC_MISC_ADDRESS_MODE 0x00000000000001c0ULL /* If MCG_CAP_SER_P */ 455191983Sweongyo#define MC_CTL2_THRESHOLD 0x0000000000003fffULL 456191983Sweongyo#define MC_CTL2_CMCI_EN 0x0000000040000000ULL 457191983Sweongyo 458191983Sweongyo/* 459191983Sweongyo * The following four 3-byte registers control the non-cacheable regions. 460191983Sweongyo * These registers must be written as three separate bytes. 461191983Sweongyo * 462191983Sweongyo * NCRx+0: A31-A24 of starting address 463191983Sweongyo * NCRx+1: A23-A16 of starting address 464191983Sweongyo * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 465191983Sweongyo * 466191983Sweongyo * The non-cacheable region's starting address must be aligned to the 467191983Sweongyo * size indicated by the NCR_SIZE_xx field. 468191983Sweongyo */ 469191983Sweongyo#define NCR1 0xc4 470191983Sweongyo#define NCR2 0xc7 471191983Sweongyo#define NCR3 0xca 472191983Sweongyo#define NCR4 0xcd 473191983Sweongyo 474191983Sweongyo#define NCR_SIZE_0K 0 475191983Sweongyo#define NCR_SIZE_4K 1 476191983Sweongyo#define NCR_SIZE_8K 2 477191983Sweongyo#define NCR_SIZE_16K 3 478191983Sweongyo#define NCR_SIZE_32K 4 479191983Sweongyo#define NCR_SIZE_64K 5 480191983Sweongyo#define NCR_SIZE_128K 6 481191983Sweongyo#define NCR_SIZE_256K 7 482191983Sweongyo#define NCR_SIZE_512K 8 483191983Sweongyo#define NCR_SIZE_1M 9 484191983Sweongyo#define NCR_SIZE_2M 10 485191983Sweongyo#define NCR_SIZE_4M 11 486191983Sweongyo#define NCR_SIZE_8M 12 487191983Sweongyo#define NCR_SIZE_16M 13 488191983Sweongyo#define NCR_SIZE_32M 14 489191983Sweongyo#define NCR_SIZE_4G 15 490191983Sweongyo 491191983Sweongyo/* 492191983Sweongyo * The address region registers are used to specify the location and 493191983Sweongyo * size for the eight address regions. 494191983Sweongyo * 495191983Sweongyo * ARRx + 0: A31-A24 of start address 496191983Sweongyo * ARRx + 1: A23-A16 of start address 497191983Sweongyo * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 498191983Sweongyo */ 499191983Sweongyo#define ARR0 0xc4 500191983Sweongyo#define ARR1 0xc7 501191983Sweongyo#define ARR2 0xca 502191983Sweongyo#define ARR3 0xcd 503191983Sweongyo#define ARR4 0xd0 504191983Sweongyo#define ARR5 0xd3 505191983Sweongyo#define ARR6 0xd6 506191983Sweongyo#define ARR7 0xd9 507191983Sweongyo 508191983Sweongyo#define ARR_SIZE_0K 0 509191983Sweongyo#define ARR_SIZE_4K 1 510191983Sweongyo#define ARR_SIZE_8K 2 511191983Sweongyo#define ARR_SIZE_16K 3 512191983Sweongyo#define ARR_SIZE_32K 4 513191983Sweongyo#define ARR_SIZE_64K 5 514191983Sweongyo#define ARR_SIZE_128K 6 515191983Sweongyo#define ARR_SIZE_256K 7 516191983Sweongyo#define ARR_SIZE_512K 8 517191983Sweongyo#define ARR_SIZE_1M 9 518191983Sweongyo#define ARR_SIZE_2M 10 519191983Sweongyo#define ARR_SIZE_4M 11 520191983Sweongyo#define ARR_SIZE_8M 12 521191983Sweongyo#define ARR_SIZE_16M 13 522191983Sweongyo#define ARR_SIZE_32M 14 523191983Sweongyo#define ARR_SIZE_4G 15 524191983Sweongyo 525191983Sweongyo/* 526191983Sweongyo * The region control registers specify the attributes associated with 527191983Sweongyo * the ARRx addres regions. 528191983Sweongyo */ 529191983Sweongyo#define RCR0 0xdc 530191983Sweongyo#define RCR1 0xdd 531191983Sweongyo#define RCR2 0xde 532191983Sweongyo#define RCR3 0xdf 533191983Sweongyo#define RCR4 0xe0 534191983Sweongyo#define RCR5 0xe1 535191983Sweongyo#define RCR6 0xe2 536191983Sweongyo#define RCR7 0xe3 537191983Sweongyo 538191983Sweongyo#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 539191983Sweongyo#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 540191983Sweongyo#define RCR_WWO 0x02 /* Weak write ordering. */ 541191983Sweongyo#define RCR_WL 0x04 /* Weak locking. */ 542191983Sweongyo#define RCR_WG 0x08 /* Write gathering. */ 543227461Shselasky#define RCR_WT 0x10 /* Write-through. */ 544191983Sweongyo#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 545191983Sweongyo 546191983Sweongyo/* AMD Write Allocate Top-Of-Memory and Control Register */ 547191983Sweongyo#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 548191983Sweongyo#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 549191983Sweongyo#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 550191983Sweongyo 551191983Sweongyo/* AMD64 MSR's */ 552191983Sweongyo#define MSR_EFER 0xc0000080 /* extended features */ 553191983Sweongyo#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 554191983Sweongyo 555191983Sweongyo/* VIA ACE crypto featureset: for via_feature_rng */ 556191983Sweongyo#define VIA_HAS_RNG 1 /* cpu has RNG */ 557191983Sweongyo 558191983Sweongyo/* VIA ACE crypto featureset: for via_feature_xcrypt */ 559191983Sweongyo#define VIA_HAS_AES 1 /* cpu has AES */ 560191983Sweongyo#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 561191983Sweongyo#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 562191983Sweongyo#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 563191983Sweongyo 564191983Sweongyo/* Centaur Extended Feature flags */ 565191983Sweongyo#define VIA_CPUID_HAS_RNG 0x000004 566191983Sweongyo#define VIA_CPUID_DO_RNG 0x000008 567191983Sweongyo#define VIA_CPUID_HAS_ACE 0x000040 568191983Sweongyo#define VIA_CPUID_DO_ACE 0x000080 569191983Sweongyo#define VIA_CPUID_HAS_ACE2 0x000100 570191983Sweongyo#define VIA_CPUID_DO_ACE2 0x000200 571191983Sweongyo#define VIA_CPUID_HAS_PHE 0x000400 572191983Sweongyo#define VIA_CPUID_DO_PHE 0x000800 573191983Sweongyo#define VIA_CPUID_HAS_PMM 0x001000 574191983Sweongyo#define VIA_CPUID_DO_PMM 0x002000 575191983Sweongyo 576191983Sweongyo/* VIA ACE xcrypt-* instruction context control options */ 577191983Sweongyo#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 578191983Sweongyo#define VIA_CRYPT_CWLO_ALG_M 0x00000070 579191983Sweongyo#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 580191983Sweongyo#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 581191983Sweongyo#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 582191983Sweongyo#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 583191983Sweongyo#define VIA_CRYPT_CWLO_NORMAL 0x00000000 584191983Sweongyo#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 585191983Sweongyo#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 586191983Sweongyo#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 587191983Sweongyo#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 588191983Sweongyo#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 589191983Sweongyo#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 590191983Sweongyo 591191983Sweongyo#endif /* !_MACHINE_SPECIALREG_H_ */ 592191983Sweongyo