specialreg.h revision 221188
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD: head/sys/i386/include/specialreg.h 221188 2011-04-28 22:23:39Z jkim $ 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ 39#define CR0_PE 0x00000001 /* Protected mode Enable */ 40#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43#define CR0_PG 0x80000000 /* PaGing enable */ 44 45/* 46 * Bits in 486 special registers: 47 */ 48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50 all modes) */ 51#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52#define CR0_NW 0x20000000 /* Not Write-through */ 53#define CR0_CD 0x40000000 /* Cache Disable */ 54 55/* 56 * Bits in PPro special registers 57 */ 58#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60#define CR4_TSD 0x00000004 /* Time stamp disable */ 61#define CR4_DE 0x00000008 /* Debugging extensions */ 62#define CR4_PSE 0x00000010 /* Page size extensions */ 63#define CR4_PAE 0x00000020 /* Physical address extension */ 64#define CR4_MCE 0x00000040 /* Machine check enable */ 65#define CR4_PGE 0x00000080 /* Page global enable */ 66#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70/* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74 75/* 76 * CPUID instruction features register 77 */ 78#define CPUID_FPU 0x00000001 79#define CPUID_VME 0x00000002 80#define CPUID_DE 0x00000004 81#define CPUID_PSE 0x00000008 82#define CPUID_TSC 0x00000010 83#define CPUID_MSR 0x00000020 84#define CPUID_PAE 0x00000040 85#define CPUID_MCE 0x00000080 86#define CPUID_CX8 0x00000100 87#define CPUID_APIC 0x00000200 88#define CPUID_B10 0x00000400 89#define CPUID_SEP 0x00000800 90#define CPUID_MTRR 0x00001000 91#define CPUID_PGE 0x00002000 92#define CPUID_MCA 0x00004000 93#define CPUID_CMOV 0x00008000 94#define CPUID_PAT 0x00010000 95#define CPUID_PSE36 0x00020000 96#define CPUID_PSN 0x00040000 97#define CPUID_CLFSH 0x00080000 98#define CPUID_B20 0x00100000 99#define CPUID_DS 0x00200000 100#define CPUID_ACPI 0x00400000 101#define CPUID_MMX 0x00800000 102#define CPUID_FXSR 0x01000000 103#define CPUID_SSE 0x02000000 104#define CPUID_XMM 0x02000000 105#define CPUID_SSE2 0x04000000 106#define CPUID_SS 0x08000000 107#define CPUID_HTT 0x10000000 108#define CPUID_TM 0x20000000 109#define CPUID_IA64 0x40000000 110#define CPUID_PBE 0x80000000 111 112#define CPUID2_SSE3 0x00000001 113#define CPUID2_PCLMULQDQ 0x00000002 114#define CPUID2_DTES64 0x00000004 115#define CPUID2_MON 0x00000008 116#define CPUID2_DS_CPL 0x00000010 117#define CPUID2_VMX 0x00000020 118#define CPUID2_SMX 0x00000040 119#define CPUID2_EST 0x00000080 120#define CPUID2_TM2 0x00000100 121#define CPUID2_SSSE3 0x00000200 122#define CPUID2_CNXTID 0x00000400 123#define CPUID2_CX16 0x00002000 124#define CPUID2_XTPR 0x00004000 125#define CPUID2_PDCM 0x00008000 126#define CPUID2_PCID 0x00020000 127#define CPUID2_DCA 0x00040000 128#define CPUID2_SSE41 0x00080000 129#define CPUID2_SSE42 0x00100000 130#define CPUID2_X2APIC 0x00200000 131#define CPUID2_MOVBE 0x00400000 132#define CPUID2_POPCNT 0x00800000 133#define CPUID2_AESNI 0x02000000 134#define CPUID2_HV 0x80000000 135 136/* 137 * Important bits in the Thermal and Power Management flags 138 * CPUID.6 EAX and ECX. 139 */ 140#define CPUTPM1_SENSOR 0x00000001 141#define CPUTPM1_TURBO 0x00000002 142#define CPUTPM1_ARAT 0x00000004 143#define CPUTPM2_EFFREQ 0x00000001 144 145/* 146 * Important bits in the AMD extended cpuid flags 147 */ 148#define AMDID_SYSCALL 0x00000800 149#define AMDID_MP 0x00080000 150#define AMDID_NX 0x00100000 151#define AMDID_EXT_MMX 0x00400000 152#define AMDID_FFXSR 0x01000000 153#define AMDID_PAGE1GB 0x04000000 154#define AMDID_RDTSCP 0x08000000 155#define AMDID_LM 0x20000000 156#define AMDID_EXT_3DNOW 0x40000000 157#define AMDID_3DNOW 0x80000000 158 159#define AMDID2_LAHF 0x00000001 160#define AMDID2_CMP 0x00000002 161#define AMDID2_SVM 0x00000004 162#define AMDID2_EXT_APIC 0x00000008 163#define AMDID2_CR8 0x00000010 164#define AMDID2_ABM 0x00000020 165#define AMDID2_SSE4A 0x00000040 166#define AMDID2_MAS 0x00000080 167#define AMDID2_PREFETCH 0x00000100 168#define AMDID2_OSVW 0x00000200 169#define AMDID2_IBS 0x00000400 170#define AMDID2_SSE5 0x00000800 171#define AMDID2_SKINIT 0x00001000 172#define AMDID2_WDT 0x00002000 173 174/* 175 * CPUID instruction 1 eax info 176 */ 177#define CPUID_STEPPING 0x0000000f 178#define CPUID_MODEL 0x000000f0 179#define CPUID_FAMILY 0x00000f00 180#define CPUID_EXT_MODEL 0x000f0000 181#define CPUID_EXT_FAMILY 0x0ff00000 182#define CPUID_TO_MODEL(id) \ 183 ((((id) & CPUID_MODEL) >> 4) | \ 184 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 185 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 186#define CPUID_TO_FAMILY(id) \ 187 ((((id) & CPUID_FAMILY) >> 8) + \ 188 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 189 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 190 191/* 192 * CPUID instruction 1 ebx info 193 */ 194#define CPUID_BRAND_INDEX 0x000000ff 195#define CPUID_CLFUSH_SIZE 0x0000ff00 196#define CPUID_HTT_CORES 0x00ff0000 197#define CPUID_LOCAL_APIC_ID 0xff000000 198 199/* 200 * CPUID instruction 6 ecx info 201 */ 202#define CPUID_PERF_STAT 0x00000001 203#define CPUID_PERF_BIAS 0x00000008 204 205/* 206 * CPUID instruction 0xb ebx info. 207 */ 208#define CPUID_TYPE_INVAL 0 209#define CPUID_TYPE_SMT 1 210#define CPUID_TYPE_CORE 2 211 212/* 213 * AMD extended function 8000_0007h edx info 214 */ 215#define AMDPM_TS 0x00000001 216#define AMDPM_FID 0x00000002 217#define AMDPM_VID 0x00000004 218#define AMDPM_TTP 0x00000008 219#define AMDPM_TM 0x00000010 220#define AMDPM_STC 0x00000020 221#define AMDPM_100MHZ_STEPS 0x00000040 222#define AMDPM_HW_PSTATE 0x00000080 223#define AMDPM_TSC_INVARIANT 0x00000100 224#define AMDPM_CPB 0x00000200 225 226/* 227 * AMD extended function 8000_0008h ecx info 228 */ 229#define AMDID_CMP_CORES 0x000000ff 230 231/* 232 * CPUID manufacturers identifiers 233 */ 234#define AMD_VENDOR_ID "AuthenticAMD" 235#define CENTAUR_VENDOR_ID "CentaurHauls" 236#define CYRIX_VENDOR_ID "CyrixInstead" 237#define INTEL_VENDOR_ID "GenuineIntel" 238#define NEXGEN_VENDOR_ID "NexGenDriven" 239#define NSC_VENDOR_ID "Geode by NSC" 240#define RISE_VENDOR_ID "RiseRiseRise" 241#define SIS_VENDOR_ID "SiS SiS SiS " 242#define TRANSMETA_VENDOR_ID "GenuineTMx86" 243#define UMC_VENDOR_ID "UMC UMC UMC " 244 245/* 246 * Model-specific registers for the i386 family 247 */ 248#define MSR_P5_MC_ADDR 0x000 249#define MSR_P5_MC_TYPE 0x001 250#define MSR_TSC 0x010 251#define MSR_P5_CESR 0x011 252#define MSR_P5_CTR0 0x012 253#define MSR_P5_CTR1 0x013 254#define MSR_IA32_PLATFORM_ID 0x017 255#define MSR_APICBASE 0x01b 256#define MSR_EBL_CR_POWERON 0x02a 257#define MSR_TEST_CTL 0x033 258#define MSR_BIOS_UPDT_TRIG 0x079 259#define MSR_BBL_CR_D0 0x088 260#define MSR_BBL_CR_D1 0x089 261#define MSR_BBL_CR_D2 0x08a 262#define MSR_BIOS_SIGN 0x08b 263#define MSR_PERFCTR0 0x0c1 264#define MSR_PERFCTR1 0x0c2 265#define MSR_MPERF 0x0e7 266#define MSR_APERF 0x0e8 267#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 268#define MSR_MTRRcap 0x0fe 269#define MSR_BBL_CR_ADDR 0x116 270#define MSR_BBL_CR_DECC 0x118 271#define MSR_BBL_CR_CTL 0x119 272#define MSR_BBL_CR_TRIG 0x11a 273#define MSR_BBL_CR_BUSY 0x11b 274#define MSR_BBL_CR_CTL3 0x11e 275#define MSR_SYSENTER_CS_MSR 0x174 276#define MSR_SYSENTER_ESP_MSR 0x175 277#define MSR_SYSENTER_EIP_MSR 0x176 278#define MSR_MCG_CAP 0x179 279#define MSR_MCG_STATUS 0x17a 280#define MSR_MCG_CTL 0x17b 281#define MSR_EVNTSEL0 0x186 282#define MSR_EVNTSEL1 0x187 283#define MSR_THERM_CONTROL 0x19a 284#define MSR_THERM_INTERRUPT 0x19b 285#define MSR_THERM_STATUS 0x19c 286#define MSR_IA32_MISC_ENABLE 0x1a0 287#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 288#define MSR_DEBUGCTLMSR 0x1d9 289#define MSR_LASTBRANCHFROMIP 0x1db 290#define MSR_LASTBRANCHTOIP 0x1dc 291#define MSR_LASTINTFROMIP 0x1dd 292#define MSR_LASTINTTOIP 0x1de 293#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 294#define MSR_MTRRVarBase 0x200 295#define MSR_MTRR64kBase 0x250 296#define MSR_MTRR16kBase 0x258 297#define MSR_MTRR4kBase 0x268 298#define MSR_PAT 0x277 299#define MSR_MC0_CTL2 0x280 300#define MSR_MTRRdefType 0x2ff 301#define MSR_MC0_CTL 0x400 302#define MSR_MC0_STATUS 0x401 303#define MSR_MC0_ADDR 0x402 304#define MSR_MC0_MISC 0x403 305#define MSR_MC1_CTL 0x404 306#define MSR_MC1_STATUS 0x405 307#define MSR_MC1_ADDR 0x406 308#define MSR_MC1_MISC 0x407 309#define MSR_MC2_CTL 0x408 310#define MSR_MC2_STATUS 0x409 311#define MSR_MC2_ADDR 0x40a 312#define MSR_MC2_MISC 0x40b 313#define MSR_MC3_CTL 0x40c 314#define MSR_MC3_STATUS 0x40d 315#define MSR_MC3_ADDR 0x40e 316#define MSR_MC3_MISC 0x40f 317#define MSR_MC4_CTL 0x410 318#define MSR_MC4_STATUS 0x411 319#define MSR_MC4_ADDR 0x412 320#define MSR_MC4_MISC 0x413 321 322/* 323 * Constants related to MSR's. 324 */ 325#define APICBASE_RESERVED 0x000006ff 326#define APICBASE_BSP 0x00000100 327#define APICBASE_ENABLED 0x00000800 328#define APICBASE_ADDRESS 0xfffff000 329 330/* 331 * PAT modes. 332 */ 333#define PAT_UNCACHEABLE 0x00 334#define PAT_WRITE_COMBINING 0x01 335#define PAT_WRITE_THROUGH 0x04 336#define PAT_WRITE_PROTECTED 0x05 337#define PAT_WRITE_BACK 0x06 338#define PAT_UNCACHED 0x07 339#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 340#define PAT_MASK(i) PAT_VALUE(i, 0xff) 341 342/* 343 * Constants related to MTRRs 344 */ 345#define MTRR_UNCACHEABLE 0x00 346#define MTRR_WRITE_COMBINING 0x01 347#define MTRR_WRITE_THROUGH 0x04 348#define MTRR_WRITE_PROTECTED 0x05 349#define MTRR_WRITE_BACK 0x06 350#define MTRR_N64K 8 /* numbers of fixed-size entries */ 351#define MTRR_N16K 16 352#define MTRR_N4K 64 353#define MTRR_CAP_WC 0x0000000000000400 354#define MTRR_CAP_FIXED 0x0000000000000100 355#define MTRR_CAP_VCNT 0x00000000000000ff 356#define MTRR_DEF_ENABLE 0x0000000000000800 357#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 358#define MTRR_DEF_TYPE 0x00000000000000ff 359#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 360#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 361#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 362#define MTRR_PHYSMASK_VALID 0x0000000000000800 363 364/* 365 * Cyrix configuration registers, accessible as IO ports. 366 */ 367#define CCR0 0xc0 /* Configuration control register 0 */ 368#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 369 non-cacheable */ 370#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 371#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 372#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 373#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 374#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 375 state */ 376#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 377 assoc */ 378#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 379 380#define CCR1 0xc1 /* Configuration control register 1 */ 381#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 382#define CCR1_SMI 0x02 /* Enables SMM pins */ 383#define CCR1_SMAC 0x04 /* System management memory access */ 384#define CCR1_MMAC 0x08 /* Main memory access */ 385#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 386#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 387 388#define CCR2 0xc2 389#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 390#define CCR2_SADS 0x02 /* Slow ADS */ 391#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 392#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 393#define CCR2_WT1 0x10 /* WT region 1 */ 394#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 395#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 396 hold state. */ 397#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 398#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 399 400#define CCR3 0xc3 401#define CCR3_SMILOCK 0x01 /* SMM register lock */ 402#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 403#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 404#define CCR3_SMMMODE 0x08 /* SMM Mode */ 405#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 406#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 407#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 408#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 409 410#define CCR4 0xe8 411#define CCR4_IOMASK 0x07 412#define CCR4_MEM 0x08 /* Enables momory bypassing */ 413#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 414#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 415#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 416 417#define CCR5 0xe9 418#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 419#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 420#define CCR5_LBR1 0x10 /* Local bus region 1 */ 421#define CCR5_ARREN 0x20 /* Enables ARR region */ 422 423#define CCR6 0xea 424 425#define CCR7 0xeb 426 427/* Performance Control Register (5x86 only). */ 428#define PCR0 0x20 429#define PCR0_RSTK 0x01 /* Enables return stack */ 430#define PCR0_BTB 0x02 /* Enables branch target buffer */ 431#define PCR0_LOOP 0x04 /* Enables loop */ 432#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 433 serialize pipe. */ 434#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 435#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 436#define PCR0_LSSER 0x80 /* Disable reorder */ 437 438/* Device Identification Registers */ 439#define DIR0 0xfe 440#define DIR1 0xff 441 442/* 443 * Machine Check register constants. 444 */ 445#define MCG_CAP_COUNT 0x000000ff 446#define MCG_CAP_CTL_P 0x00000100 447#define MCG_CAP_EXT_P 0x00000200 448#define MCG_CAP_CMCI_P 0x00000400 449#define MCG_CAP_TES_P 0x00000800 450#define MCG_CAP_EXT_CNT 0x00ff0000 451#define MCG_CAP_SER_P 0x01000000 452#define MCG_STATUS_RIPV 0x00000001 453#define MCG_STATUS_EIPV 0x00000002 454#define MCG_STATUS_MCIP 0x00000004 455#define MCG_CTL_ENABLE 0xffffffffffffffff 456#define MCG_CTL_DISABLE 0x0000000000000000 457#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 458#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 459#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 460#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 461#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 462#define MC_STATUS_MCA_ERROR 0x000000000000ffff 463#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 464#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 465#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 466#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 467#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 468#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 469#define MC_STATUS_PCC 0x0200000000000000 470#define MC_STATUS_ADDRV 0x0400000000000000 471#define MC_STATUS_MISCV 0x0800000000000000 472#define MC_STATUS_EN 0x1000000000000000 473#define MC_STATUS_UC 0x2000000000000000 474#define MC_STATUS_OVER 0x4000000000000000 475#define MC_STATUS_VAL 0x8000000000000000 476#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 477#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 478#define MC_CTL2_THRESHOLD 0x0000000000007fff 479#define MC_CTL2_CMCI_EN 0x0000000040000000 480 481/* 482 * The following four 3-byte registers control the non-cacheable regions. 483 * These registers must be written as three separate bytes. 484 * 485 * NCRx+0: A31-A24 of starting address 486 * NCRx+1: A23-A16 of starting address 487 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 488 * 489 * The non-cacheable region's starting address must be aligned to the 490 * size indicated by the NCR_SIZE_xx field. 491 */ 492#define NCR1 0xc4 493#define NCR2 0xc7 494#define NCR3 0xca 495#define NCR4 0xcd 496 497#define NCR_SIZE_0K 0 498#define NCR_SIZE_4K 1 499#define NCR_SIZE_8K 2 500#define NCR_SIZE_16K 3 501#define NCR_SIZE_32K 4 502#define NCR_SIZE_64K 5 503#define NCR_SIZE_128K 6 504#define NCR_SIZE_256K 7 505#define NCR_SIZE_512K 8 506#define NCR_SIZE_1M 9 507#define NCR_SIZE_2M 10 508#define NCR_SIZE_4M 11 509#define NCR_SIZE_8M 12 510#define NCR_SIZE_16M 13 511#define NCR_SIZE_32M 14 512#define NCR_SIZE_4G 15 513 514/* 515 * The address region registers are used to specify the location and 516 * size for the eight address regions. 517 * 518 * ARRx + 0: A31-A24 of start address 519 * ARRx + 1: A23-A16 of start address 520 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 521 */ 522#define ARR0 0xc4 523#define ARR1 0xc7 524#define ARR2 0xca 525#define ARR3 0xcd 526#define ARR4 0xd0 527#define ARR5 0xd3 528#define ARR6 0xd6 529#define ARR7 0xd9 530 531#define ARR_SIZE_0K 0 532#define ARR_SIZE_4K 1 533#define ARR_SIZE_8K 2 534#define ARR_SIZE_16K 3 535#define ARR_SIZE_32K 4 536#define ARR_SIZE_64K 5 537#define ARR_SIZE_128K 6 538#define ARR_SIZE_256K 7 539#define ARR_SIZE_512K 8 540#define ARR_SIZE_1M 9 541#define ARR_SIZE_2M 10 542#define ARR_SIZE_4M 11 543#define ARR_SIZE_8M 12 544#define ARR_SIZE_16M 13 545#define ARR_SIZE_32M 14 546#define ARR_SIZE_4G 15 547 548/* 549 * The region control registers specify the attributes associated with 550 * the ARRx addres regions. 551 */ 552#define RCR0 0xdc 553#define RCR1 0xdd 554#define RCR2 0xde 555#define RCR3 0xdf 556#define RCR4 0xe0 557#define RCR5 0xe1 558#define RCR6 0xe2 559#define RCR7 0xe3 560 561#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 562#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 563#define RCR_WWO 0x02 /* Weak write ordering. */ 564#define RCR_WL 0x04 /* Weak locking. */ 565#define RCR_WG 0x08 /* Write gathering. */ 566#define RCR_WT 0x10 /* Write-through. */ 567#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 568 569/* AMD Write Allocate Top-Of-Memory and Control Register */ 570#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 571#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 572#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 573 574/* AMD64 MSR's */ 575#define MSR_EFER 0xc0000080 /* extended features */ 576#define MSR_HWCR 0xc0010015 577#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 578#define MSR_MC0_CTL_MASK 0xc0010044 579 580/* VIA ACE crypto featureset: for via_feature_rng */ 581#define VIA_HAS_RNG 1 /* cpu has RNG */ 582 583/* VIA ACE crypto featureset: for via_feature_xcrypt */ 584#define VIA_HAS_AES 1 /* cpu has AES */ 585#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 586#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 587#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 588 589/* Centaur Extended Feature flags */ 590#define VIA_CPUID_HAS_RNG 0x000004 591#define VIA_CPUID_DO_RNG 0x000008 592#define VIA_CPUID_HAS_ACE 0x000040 593#define VIA_CPUID_DO_ACE 0x000080 594#define VIA_CPUID_HAS_ACE2 0x000100 595#define VIA_CPUID_DO_ACE2 0x000200 596#define VIA_CPUID_HAS_PHE 0x000400 597#define VIA_CPUID_DO_PHE 0x000800 598#define VIA_CPUID_HAS_PMM 0x001000 599#define VIA_CPUID_DO_PMM 0x002000 600 601/* VIA ACE xcrypt-* instruction context control options */ 602#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 603#define VIA_CRYPT_CWLO_ALG_M 0x00000070 604#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 605#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 606#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 607#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 608#define VIA_CRYPT_CWLO_NORMAL 0x00000000 609#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 610#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 611#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 612#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 613#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 614#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 615 616#endif /* !_MACHINE_SPECIALREG_H_ */ 617