specialreg.h revision 170150
1117395Skan/*- 2117395Skan * Copyright (c) 1991 The Regents of the University of California. 3132718Skan * All rights reserved. 4117395Skan * 5132718Skan * Redistribution and use in source and binary forms, with or without 6117395Skan * modification, are permitted provided that the following conditions 7117395Skan * are met: 8117395Skan * 1. Redistributions of source code must retain the above copyright 9117395Skan * notice, this list of conditions and the following disclaimer. 10132718Skan * 2. Redistributions in binary form must reproduce the above copyright 11117395Skan * notice, this list of conditions and the following disclaimer in the 12117395Skan * documentation and/or other materials provided with the distribution. 13117395Skan * 4. Neither the name of the University nor the names of its contributors 14117395Skan * may be used to endorse or promote products derived from this software 15117395Skan * without specific prior written permission. 16132718Skan * 17169689Skan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18169689Skan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19117395Skan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20117395Skan * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21117395Skan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22117395Skan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23117395Skan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24117395Skan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25117395Skan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26117395Skan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27117395Skan * SUCH DAMAGE. 28117395Skan * 29117395Skan * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 30117395Skan * $FreeBSD: head/sys/i386/include/specialreg.h 170150 2007-05-31 11:26:45Z des $ 31117395Skan */ 32117395Skan 33117395Skan#ifndef _MACHINE_SPECIALREG_H_ 34117395Skan#define _MACHINE_SPECIALREG_H_ 35117395Skan 36117395Skan/* 37117395Skan * Bits in 386 special registers: 38117395Skan */ 39117395Skan#define CR0_PE 0x00000001 /* Protected mode Enable */ 40117395Skan#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41117395Skan#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 42117395Skan#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43117395Skan#define CR0_PG 0x80000000 /* PaGing enable */ 44117395Skan 45117395Skan/* 46117395Skan * Bits in 486 special registers: 47117395Skan */ 48117395Skan#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 49117395Skan#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 50117395Skan all modes) */ 51117395Skan#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52117395Skan#define CR0_NW 0x20000000 /* Not Write-through */ 53117395Skan#define CR0_CD 0x40000000 /* Cache Disable */ 54117395Skan 55117395Skan/* 56117395Skan * Bits in PPro special registers 57117395Skan */ 58117395Skan#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 59117395Skan#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 60117395Skan#define CR4_TSD 0x00000004 /* Time stamp disable */ 61117395Skan#define CR4_DE 0x00000008 /* Debugging extensions */ 62117395Skan#define CR4_PSE 0x00000010 /* Page size extensions */ 63117395Skan#define CR4_PAE 0x00000020 /* Physical address extension */ 64117395Skan#define CR4_MCE 0x00000040 /* Machine check enable */ 65117395Skan#define CR4_PGE 0x00000080 /* Page global enable */ 66117395Skan#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67117395Skan#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68117395Skan#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69117395Skan 70117395Skan/* 71117395Skan * Bits in AMD64 special registers. EFER is 64 bits wide. 72117395Skan */ 73117395Skan#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74117395Skan 75117395Skan/* 76117395Skan * CPUID instruction features register 77117395Skan */ 78117395Skan#define CPUID_FPU 0x00000001 79117395Skan#define CPUID_VME 0x00000002 80117395Skan#define CPUID_DE 0x00000004 81117395Skan#define CPUID_PSE 0x00000008 82117395Skan#define CPUID_TSC 0x00000010 83117395Skan#define CPUID_MSR 0x00000020 84117395Skan#define CPUID_PAE 0x00000040 85117395Skan#define CPUID_MCE 0x00000080 86117395Skan#define CPUID_CX8 0x00000100 87117395Skan#define CPUID_APIC 0x00000200 88117395Skan#define CPUID_B10 0x00000400 89117395Skan#define CPUID_SEP 0x00000800 90117395Skan#define CPUID_MTRR 0x00001000 91117395Skan#define CPUID_PGE 0x00002000 92117395Skan#define CPUID_MCA 0x00004000 93117395Skan#define CPUID_CMOV 0x00008000 94117395Skan#define CPUID_PAT 0x00010000 95117395Skan#define CPUID_PSE36 0x00020000 96117395Skan#define CPUID_PSN 0x00040000 97117395Skan#define CPUID_CLFSH 0x00080000 98117395Skan#define CPUID_B20 0x00100000 99117395Skan#define CPUID_DS 0x00200000 100117395Skan#define CPUID_ACPI 0x00400000 101117395Skan#define CPUID_MMX 0x00800000 102117395Skan#define CPUID_FXSR 0x01000000 103117395Skan#define CPUID_SSE 0x02000000 104117395Skan#define CPUID_XMM 0x02000000 105117395Skan#define CPUID_SSE2 0x04000000 106117395Skan#define CPUID_SS 0x08000000 107117395Skan#define CPUID_HTT 0x10000000 108117395Skan#define CPUID_TM 0x20000000 109117395Skan#define CPUID_IA64 0x40000000 110117395Skan#define CPUID_PBE 0x80000000 111117395Skan 112117395Skan#define CPUID2_SSE3 0x00000001 113117395Skan#define CPUID2_MON 0x00000008 114117395Skan#define CPUID2_DS_CPL 0x00000010 115117395Skan#define CPUID2_VMX 0x00000020 116117395Skan#define CPUID2_SMX 0x00000040 117117395Skan#define CPUID2_EST 0x00000080 118117395Skan#define CPUID2_TM2 0x00000100 119117395Skan#define CPUID2_SSSE3 0x00000200 120117395Skan#define CPUID2_CNXTID 0x00000400 121117395Skan#define CPUID2_CX16 0x00002000 122117395Skan#define CPUID2_XTPR 0x00004000 123117395Skan#define CPUID2_PDCM 0x00008000 124117395Skan#define CPUID2_DCA 0x00040000 125117395Skan 126117395Skan/* 127117395Skan * Important bits in the AMD extended cpuid flags 128117395Skan */ 129117395Skan#define AMDID_SYSCALL 0x00000800 130117395Skan#define AMDID_MP 0x00080000 131117395Skan#define AMDID_NX 0x00100000 132117395Skan#define AMDID_EXT_MMX 0x00400000 133117395Skan#define AMDID_FFXSR 0x01000000 134117395Skan#define AMDID_RDTSCP 0x08000000 135117395Skan#define AMDID_LM 0x20000000 136117395Skan#define AMDID_EXT_3DNOW 0x40000000 137117395Skan#define AMDID_3DNOW 0x80000000 138117395Skan 139117395Skan#define AMDID2_LAHF 0x00000001 140117395Skan#define AMDID2_CMP 0x00000002 141117395Skan#define AMDID2_SVM 0x00000004 142117395Skan#define AMDID2_EXT_APIC 0x00000008 143117395Skan#define AMDID2_CR8 0x00000010 144117395Skan#define AMDID2_PREFETCH 0x00000100 145117395Skan 146117395Skan/* 147117395Skan * CPUID instruction 1 ebx info 148117395Skan */ 149117395Skan#define CPUID_BRAND_INDEX 0x000000ff 150117395Skan#define CPUID_CLFUSH_SIZE 0x0000ff00 151117395Skan#define CPUID_HTT_CORES 0x00ff0000 152117395Skan#define CPUID_LOCAL_APIC_ID 0xff000000 153117395Skan 154117395Skan/* 155117395Skan * AMD extended function 8000_0008h ecx info 156117395Skan */ 157117395Skan#define AMDID_CMP_CORES 0x000000ff 158117395Skan 159117395Skan/* 160117395Skan * Model-specific registers for the i386 family 161117395Skan */ 162117395Skan#define MSR_P5_MC_ADDR 0x000 163#define MSR_P5_MC_TYPE 0x001 164#define MSR_TSC 0x010 165#define MSR_P5_CESR 0x011 166#define MSR_P5_CTR0 0x012 167#define MSR_P5_CTR1 0x013 168#define MSR_IA32_PLATFORM_ID 0x017 169#define MSR_APICBASE 0x01b 170#define MSR_EBL_CR_POWERON 0x02a 171#define MSR_TEST_CTL 0x033 172#define MSR_BIOS_UPDT_TRIG 0x079 173#define MSR_BBL_CR_D0 0x088 174#define MSR_BBL_CR_D1 0x089 175#define MSR_BBL_CR_D2 0x08a 176#define MSR_BIOS_SIGN 0x08b 177#define MSR_PERFCTR0 0x0c1 178#define MSR_PERFCTR1 0x0c2 179#define MSR_MTRRcap 0x0fe 180#define MSR_BBL_CR_ADDR 0x116 181#define MSR_BBL_CR_DECC 0x118 182#define MSR_BBL_CR_CTL 0x119 183#define MSR_BBL_CR_TRIG 0x11a 184#define MSR_BBL_CR_BUSY 0x11b 185#define MSR_BBL_CR_CTL3 0x11e 186#define MSR_SYSENTER_CS_MSR 0x174 187#define MSR_SYSENTER_ESP_MSR 0x175 188#define MSR_SYSENTER_EIP_MSR 0x176 189#define MSR_MCG_CAP 0x179 190#define MSR_MCG_STATUS 0x17a 191#define MSR_MCG_CTL 0x17b 192#define MSR_EVNTSEL0 0x186 193#define MSR_EVNTSEL1 0x187 194#define MSR_THERM_CONTROL 0x19a 195#define MSR_THERM_INTERRUPT 0x19b 196#define MSR_THERM_STATUS 0x19c 197#define MSR_IA32_MISC_ENABLE 0x1a0 198#define MSR_DEBUGCTLMSR 0x1d9 199#define MSR_LASTBRANCHFROMIP 0x1db 200#define MSR_LASTBRANCHTOIP 0x1dc 201#define MSR_LASTINTFROMIP 0x1dd 202#define MSR_LASTINTTOIP 0x1de 203#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 204#define MSR_MTRRVarBase 0x200 205#define MSR_MTRR64kBase 0x250 206#define MSR_MTRR16kBase 0x258 207#define MSR_MTRR4kBase 0x268 208#define MSR_PAT 0x277 209#define MSR_MTRRdefType 0x2ff 210#define MSR_MC0_CTL 0x400 211#define MSR_MC0_STATUS 0x401 212#define MSR_MC0_ADDR 0x402 213#define MSR_MC0_MISC 0x403 214#define MSR_MC1_CTL 0x404 215#define MSR_MC1_STATUS 0x405 216#define MSR_MC1_ADDR 0x406 217#define MSR_MC1_MISC 0x407 218#define MSR_MC2_CTL 0x408 219#define MSR_MC2_STATUS 0x409 220#define MSR_MC2_ADDR 0x40a 221#define MSR_MC2_MISC 0x40b 222#define MSR_MC3_CTL 0x40c 223#define MSR_MC3_STATUS 0x40d 224#define MSR_MC3_ADDR 0x40e 225#define MSR_MC3_MISC 0x40f 226#define MSR_MC4_CTL 0x410 227#define MSR_MC4_STATUS 0x411 228#define MSR_MC4_ADDR 0x412 229#define MSR_MC4_MISC 0x413 230 231/* 232 * Constants related to MSR's. 233 */ 234#define APICBASE_RESERVED 0x000006ff 235#define APICBASE_BSP 0x00000100 236#define APICBASE_ENABLED 0x00000800 237#define APICBASE_ADDRESS 0xfffff000 238 239/* 240 * PAT modes. 241 */ 242#define PAT_UNCACHEABLE 0x00 243#define PAT_WRITE_COMBINING 0x01 244#define PAT_WRITE_THROUGH 0x04 245#define PAT_WRITE_PROTECTED 0x05 246#define PAT_WRITE_BACK 0x06 247#define PAT_UNCACHED 0x07 248#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 249#define PAT_MASK(i) PAT_VALUE(i, 0xff) 250 251/* 252 * Constants related to MTRRs 253 */ 254#define MTRR_N64K 8 /* numbers of fixed-size entries */ 255#define MTRR_N16K 16 256#define MTRR_N4K 64 257 258/* 259 * Cyrix configuration registers, accessible as IO ports. 260 */ 261#define CCR0 0xc0 /* Configuration control register 0 */ 262#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 263 non-cacheable */ 264#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 265#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 266#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 267#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 268#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 269 state */ 270#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 271 assoc */ 272#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 273 274#define CCR1 0xc1 /* Configuration control register 1 */ 275#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 276#define CCR1_SMI 0x02 /* Enables SMM pins */ 277#define CCR1_SMAC 0x04 /* System management memory access */ 278#define CCR1_MMAC 0x08 /* Main memory access */ 279#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 280#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 281 282#define CCR2 0xc2 283#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 284#define CCR2_SADS 0x02 /* Slow ADS */ 285#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 286#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 287#define CCR2_WT1 0x10 /* WT region 1 */ 288#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 289#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 290 hold state. */ 291#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 292#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 293 294#define CCR3 0xc3 295#define CCR3_SMILOCK 0x01 /* SMM register lock */ 296#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 297#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 298#define CCR3_SMMMODE 0x08 /* SMM Mode */ 299#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 300#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 301#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 302#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 303 304#define CCR4 0xe8 305#define CCR4_IOMASK 0x07 306#define CCR4_MEM 0x08 /* Enables momory bypassing */ 307#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 308#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 309#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 310 311#define CCR5 0xe9 312#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 313#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 314#define CCR5_LBR1 0x10 /* Local bus region 1 */ 315#define CCR5_ARREN 0x20 /* Enables ARR region */ 316 317#define CCR6 0xea 318 319#define CCR7 0xeb 320 321/* Performance Control Register (5x86 only). */ 322#define PCR0 0x20 323#define PCR0_RSTK 0x01 /* Enables return stack */ 324#define PCR0_BTB 0x02 /* Enables branch target buffer */ 325#define PCR0_LOOP 0x04 /* Enables loop */ 326#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 327 serialize pipe. */ 328#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 329#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 330#define PCR0_LSSER 0x80 /* Disable reorder */ 331 332/* Device Identification Registers */ 333#define DIR0 0xfe 334#define DIR1 0xff 335 336/* 337 * The following four 3-byte registers control the non-cacheable regions. 338 * These registers must be written as three separate bytes. 339 * 340 * NCRx+0: A31-A24 of starting address 341 * NCRx+1: A23-A16 of starting address 342 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 343 * 344 * The non-cacheable region's starting address must be aligned to the 345 * size indicated by the NCR_SIZE_xx field. 346 */ 347#define NCR1 0xc4 348#define NCR2 0xc7 349#define NCR3 0xca 350#define NCR4 0xcd 351 352#define NCR_SIZE_0K 0 353#define NCR_SIZE_4K 1 354#define NCR_SIZE_8K 2 355#define NCR_SIZE_16K 3 356#define NCR_SIZE_32K 4 357#define NCR_SIZE_64K 5 358#define NCR_SIZE_128K 6 359#define NCR_SIZE_256K 7 360#define NCR_SIZE_512K 8 361#define NCR_SIZE_1M 9 362#define NCR_SIZE_2M 10 363#define NCR_SIZE_4M 11 364#define NCR_SIZE_8M 12 365#define NCR_SIZE_16M 13 366#define NCR_SIZE_32M 14 367#define NCR_SIZE_4G 15 368 369/* 370 * The address region registers are used to specify the location and 371 * size for the eight address regions. 372 * 373 * ARRx + 0: A31-A24 of start address 374 * ARRx + 1: A23-A16 of start address 375 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 376 */ 377#define ARR0 0xc4 378#define ARR1 0xc7 379#define ARR2 0xca 380#define ARR3 0xcd 381#define ARR4 0xd0 382#define ARR5 0xd3 383#define ARR6 0xd6 384#define ARR7 0xd9 385 386#define ARR_SIZE_0K 0 387#define ARR_SIZE_4K 1 388#define ARR_SIZE_8K 2 389#define ARR_SIZE_16K 3 390#define ARR_SIZE_32K 4 391#define ARR_SIZE_64K 5 392#define ARR_SIZE_128K 6 393#define ARR_SIZE_256K 7 394#define ARR_SIZE_512K 8 395#define ARR_SIZE_1M 9 396#define ARR_SIZE_2M 10 397#define ARR_SIZE_4M 11 398#define ARR_SIZE_8M 12 399#define ARR_SIZE_16M 13 400#define ARR_SIZE_32M 14 401#define ARR_SIZE_4G 15 402 403/* 404 * The region control registers specify the attributes associated with 405 * the ARRx addres regions. 406 */ 407#define RCR0 0xdc 408#define RCR1 0xdd 409#define RCR2 0xde 410#define RCR3 0xdf 411#define RCR4 0xe0 412#define RCR5 0xe1 413#define RCR6 0xe2 414#define RCR7 0xe3 415 416#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 417#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 418#define RCR_WWO 0x02 /* Weak write ordering. */ 419#define RCR_WL 0x04 /* Weak locking. */ 420#define RCR_WG 0x08 /* Write gathering. */ 421#define RCR_WT 0x10 /* Write-through. */ 422#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 423 424/* AMD Write Allocate Top-Of-Memory and Control Register */ 425#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 426#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 427#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 428 429/* AMD64 MSR's */ 430#define MSR_EFER 0xc0000080 /* extended features */ 431 432/* VIA ACE crypto featureset: for via_feature_rng */ 433#define VIA_HAS_RNG 1 /* cpu has RNG */ 434 435/* VIA ACE crypto featureset: for via_feature_xcrypt */ 436#define VIA_HAS_AES 1 /* cpu has AES */ 437#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 438#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 439#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 440 441/* Centaur Extended Feature flags */ 442#define VIA_CPUID_HAS_RNG 0x000004 443#define VIA_CPUID_DO_RNG 0x000008 444#define VIA_CPUID_HAS_ACE 0x000040 445#define VIA_CPUID_DO_ACE 0x000080 446#define VIA_CPUID_HAS_ACE2 0x000100 447#define VIA_CPUID_DO_ACE2 0x000200 448#define VIA_CPUID_HAS_PHE 0x000400 449#define VIA_CPUID_DO_PHE 0x000800 450#define VIA_CPUID_HAS_PMM 0x001000 451#define VIA_CPUID_DO_PMM 0x002000 452 453/* VIA ACE xcrypt-* instruction context control options */ 454#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 455#define VIA_CRYPT_CWLO_ALG_M 0x00000070 456#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 457#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 458#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 459#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 460#define VIA_CRYPT_CWLO_NORMAL 0x00000000 461#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 462#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 463#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 464#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 465#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 466#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 467 468#ifndef LOCORE 469static __inline u_char 470read_cyrix_reg(u_char reg) 471{ 472 outb(0x22, reg); 473 return inb(0x23); 474} 475 476static __inline void 477write_cyrix_reg(u_char reg, u_char data) 478{ 479 outb(0x22, reg); 480 outb(0x23, data); 481} 482#endif 483 484#endif /* !_MACHINE_SPECIALREG_H_ */ 485