Searched refs:clk_rate (Results 1 - 25 of 155) sorted by last modified time

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/linux-master/sound/soc/sunxi/
H A Dsun4i-i2s.c344 unsigned int oversample_rate, clk_rate, bclk_parent_rate; local
354 clk_rate = 22579200;
367 clk_rate = 24576000;
375 ret = clk_set_rate(i2s->mod_clk, clk_rate);
394 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
/linux-master/sound/soc/loongson/
H A Dloongson_i2s_pci.c128 device_property_read_u32(&pdev->dev, "clock-frequency", &i2s->clk_rate);
129 if (!i2s->clk_rate) {
/linux-master/sound/soc/img/
H A Dimg-i2s-out.c218 long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate; local
257 clk_rate = clk_get_rate(i2s->clk_ref);
259 diff_a = abs((clk_rate / 256) - rate);
260 diff_b = abs((clk_rate / 384) - rate);
/linux-master/drivers/mmc/host/
H A Drenesas_sdhi_internal_dmac.c86 .clk_rate = 0,
H A Drenesas_sdhi_core.c1087 if (taps[i].clk_rate == 0 ||
1088 taps[i].clk_rate == host->mmc->f_max) {
H A Dsdhci-msm.c270 unsigned long clk_rate; member in struct:sdhci_msm_host
387 msm_host->clk_rate = desired_rate;
742 if (msm_host->clk_rate < 150000000)
814 * before changing the clk_rate at GCC.
848 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
867 * before changing the clk_rate at GCC.
1791 host->mmc->actual_clock = msm_host->clk_rate = 0;
2727 if (msm_host->restore_dll_config && msm_host->clk_rate) {
2733 dev_pm_opp_set_rate(dev, msm_host->clk_rate);
/linux-master/drivers/spi/
H A Dspi-cadence-quadspi.c62 u32 clk_rate; member in struct:cqspi_flash_pdata
1516 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
H A Dspi-stm32.c304 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
333 u32 clk_rate; member in struct:stm32_spi
542 /* Ensure spi->clk_rate is even */
543 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
561 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
2121 spi->clk_rate = clk_get_rate(spi->clk);
2122 if (!spi->clk_rate) {
2173 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
2174 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
/linux-master/drivers/pwm/
H A Dpwm-sti.c120 unsigned long clk_rate; local
124 clk_rate = clk_get_rate(pc->pwm_clk);
125 if (!clk_rate) {
131 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1
133 value = NSEC_PER_SEC / clk_rate;
H A Dpwm-img.c261 unsigned long clk_rate; local
304 clk_rate = clk_get_rate(imgchip->pwm_clk);
305 if (!clk_rate) {
313 do_div(val, clk_rate);
317 do_div(val, clk_rate);
/linux-master/drivers/net/ethernet/xilinx/
H A Dxilinx_axienet_main.c234 u64 clk_rate = 125000000; /* arbitrary guess if no clock rate set */ local
237 clk_rate = clk_get_rate(lp->axi_clk);
240 result = DIV64_U64_ROUND_CLOSEST((u64)coalesce_usec * clk_rate,
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_main.c303 u32 clk_rate; local
305 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
315 if (clk_rate < CSR_F_35M)
317 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
319 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
321 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
323 else if ((clk_rate >
[all...]
H A Ddwmac4_core.c28 u32 clk_rate; local
52 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
53 writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c169 u32 clk_rate = clk_get_rate(priv->sxgbe_clk); local
174 if (clk_rate < SXGBE_CSR_F_150M)
176 else if (clk_rate <= SXGBE_CSR_F_250M)
178 else if (clk_rate <= SXGBE_CSR_F_300M)
180 else if (clk_rate <= SXGBE_CSR_F_350M)
182 else if (clk_rate <= SXGBE_CSR_F_400M)
184 else if (clk_rate <= SXGBE_CSR_F_500M)
/linux-master/drivers/net/ethernet/marvell/
H A Dmvneta.c1699 unsigned long clk_rate; local
1701 clk_rate = clk_get_rate(pp->clk);
1702 val = (clk_rate / 1000000) * value;
/linux-master/drivers/hwmon/
H A Daspeed-g6-pwm-tach.c138 unsigned long clk_rate; member in struct:aspeed_pwm_tach_data
173 state->period = DIV_ROUND_UP_ULL(dividend, priv->clk_rate);
178 state->duty_cycle = DIV_ROUND_UP_ULL(dividend, priv->clk_rate);
195 expect_period = div64_u64(ULLONG_MAX, (u64)priv->clk_rate);
205 div_h = order_base_2(DIV64_U64_ROUND_UP(priv->clk_rate * expect_period, divisor));
210 div_l = div64_u64(priv->clk_rate * expect_period, divisor);
221 priv->clk_rate, div_h, div_l);
223 duty_pt = div64_u64(state->duty_cycle * priv->clk_rate,
293 priv->clk_rate, tach_val, tach_div);
295 rpm = (u64)priv->clk_rate * 6
[all...]
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_core_perf.c138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
282 u64 clk_rate; local
292 clk_rate = 0;
296 clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
297 clk_rate);
301 return clk_rate;
309 u64 clk_rate = 0; local
380 clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
382 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
384 trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate);
[all...]
/linux-master/drivers/usb/phy/
H A Dphy-generic.c205 u32 clk_rate = 0; local
211 if (of_property_read_u32(node, "clock-frequency", &clk_rate))
212 clk_rate = 0;
245 if (!IS_ERR(nop->clk) && clk_rate) {
246 err = clk_set_rate(nop->clk, clk_rate);
/linux-master/drivers/tty/serial/
H A Dqcom_geni_serial.c128 unsigned long clk_rate; member in struct:qcom_geni_serial_port
1222 unsigned long clk_rate; local
1237 clk_rate = get_clk_div_rate(port->se.clk, baud,
1239 if (!clk_rate) {
1246 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
1247 baud * sampling_rate, clk_rate, clk_div);
1249 uport->uartclk = clk_rate;
1250 port->clk_rate = clk_rate;
1251 dev_pm_opp_set_rate(uport->dev, clk_rate);
[all...]
/linux-master/drivers/remoteproc/
H A Dst_remoteproc.c47 u32 clk_rate; member in struct:st_rproc
314 err = of_property_read_u32(np, "clock-frequency", &ddata->clk_rate);
376 clk_set_rate(ddata->clk, ddata->clk_rate);
/linux-master/drivers/iio/adc/
H A Drockchip_saradc.c62 unsigned long clk_rate; member in struct:rockchip_saradc_data
240 .clk_rate = 1000000,
254 .clk_rate = 50000,
272 .clk_rate = 1000000,
292 .clk_rate = 1000000,
312 .clk_rate = 1000000,
485 ret = clk_set_rate(info->clk, info->data->clk_rate);
/linux-master/drivers/phy/st/
H A Dphy-stm32-usbphyc.c204 static void stm32_usbphyc_get_pll_params(u32 clk_rate, argument
222 do_div(ndiv, (clk_rate * 2));
226 do_div(frac, (clk_rate * 2));
234 u32 clk_rate = clk_get_rate(usbphyc->clk); local
238 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
239 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
241 clk_rate);
245 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
257 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
/linux-master/drivers/phy/ralink/
H A Dphy-mt7621-pci.c120 unsigned long clk_rate; local
122 clk_rate = clk_get_rate(phy->sys_clk);
123 if (!clk_rate)
142 if (clk_rate == 40000000) { /* 40MHz Xtal */
148 } else if (clk_rate == 25000000) { /* 25MHz Xal */
199 if (clk_rate == 40000000) { /* 40MHz Xtal */
/linux-master/drivers/phy/intel/
H A Dphy-intel-lgm-combo.c89 unsigned long clk_rate; member in struct:intel_combo_phy
264 ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate);
267 cbphy->clk_rate);
493 cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode];
/linux-master/drivers/mtd/nand/raw/
H A Dmeson_nand.c122 unsigned long clk_rate; member in struct:meson_nfc_nand_chip
170 unsigned long clk_rate; member in struct:meson_nfc
273 if (nfc->clk_rate != meson_chip->clk_rate) {
274 ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate);
279 nfc->clk_rate = meson_chip->clk_rate;
1271 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;

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