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0f3841a5 |
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09-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: report correct number of chip-select Set the ->num_chipselect field in struct cqspi_st and struct spi_controller to the current number of chip-select. The value is dependent on declared flashes in devicetree. Previously, the num-cs property from devicetree or the maximum value was being reported. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-3-a4f9dfed9ab4@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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7cc3522a |
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09-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: set maximum chip-select to 4 Change the maximum chip-select count in cadence-qspi to 4 instead of 16. The value gets used as default ->num_chipselect when the num-cs DT property isn't received from devicetree. It also determines the cqspi->f_pdata array size. Hardware only supports values up to 4; see cqspi_chipselect() that sets CS using a one-bit-per-CS 4-bit register field. Add a static_assert() call as a defensive measure to ensure we stay under the SPI subsystem limit. It got set to 4 when introduced in 4d8ff6b0991d ("spi: Add multi-cs memories support in SPI core") and later increased to 16 in 2f8c7c3715f2 ("spi: Raise limit on number of chip selects"). Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-2-a4f9dfed9ab4@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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0d62c64a |
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09-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: assert each subnode flash CS is valid Check each flash CS against the num-cs property from devicetree. Fallback to the driver max supported value (CQSPI_MAX_CHIPSELECT) if num-cs isn't present. cqspi->num_chipselect is set in cqspi_of_get_pdata() to the num-cs devicetree property, or to CQSPI_MAX_CHIPSELECT if num-cs is not set. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://msgid.link/r/20240209-cdns-qspi-cs-v1-1-a4f9dfed9ab4@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
28e59d8b |
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07-Feb-2024 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
spi: cadence-quadspi: Follow renaming of SPI "master" to "controller" In commit 8caab75fd2c2 ("spi: Generalize SPI "master" to "controller"") some functions and struct members were renamed. To not break all drivers compatibility macros were provided. To be able to remove these compatibility macros push the renaming into this driver. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/d741960846b7f4896eeff91a4c8c7dfa8a6f8b7b.1707324794.git.u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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#
e71011da |
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07-Feb-2024 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
spi: cadence-quadspi: Don't emit error message on allocation error Drivers are not supposed to emit an error message when a memory allocation fails, as the kernel is very loud in this case already anyhow. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/8da90785395664bf17d16428f46e84b95ef5cc3b.1707324794.git.u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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#
078d62de |
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22-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: add system-wide suspend and resume callbacks Each SPI controller is expected to call the spi_controller_suspend() and spi_controller_resume() callbacks at system-wide suspend and resume. It (1) handles the kthread worker for queued controllers and (2) marks the controller as suspended to have spi_sync() fail while the controller is unavailable. Those two operations do not require the controller to be active, we do not need to increment the runtime PM usage counter. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-4-6b6af8bcbf59@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
4efa1250 |
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22-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: put runtime in runtime PM hooks names Follow kernel naming convention with regards to power-management callback function names. The convention in the kernel is: - prefix_suspend means the system-wide suspend callback; - prefix_runtime_suspend means the runtime PM suspend callback. The same applies to resume callbacks. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-3-6b6af8bcbf59@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
959043af |
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22-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: remove system-wide suspend helper calls from runtime PM hooks The ->runtime_suspend() and ->runtime_resume() callbacks are not expected to call spi_controller_suspend() and spi_controller_resume(). Remove calls to those in the cadence-qspi driver. Those helpers have two roles currently: - They stop/start the queue, including dealing with the kworker. - They toggle the SPI controller SPI_CONTROLLER_SUSPENDED flag. It requires acquiring ctlr->bus_lock_mutex. Step one is irrelevant because cadence-qspi is not queued. Step two however has two implications: - A deadlock occurs, because ->runtime_resume() is called in a context where the lock is already taken (in the ->exec_op() callback, where the usage count is incremented). - It would disallow all operations once the device is auto-suspended. Here is a brief call tree highlighting the mutex deadlock: spi_mem_exec_op() ... spi_mem_access_start() mutex_lock(&ctlr->bus_lock_mutex) cqspi_exec_mem_op() pm_runtime_resume_and_get() cqspi_resume() spi_controller_resume() mutex_lock(&ctlr->bus_lock_mutex) ... spi_mem_access_end() mutex_unlock(&ctlr->bus_lock_mutex) ... Fixes: 0578a6dbfe75 ("spi: spi-cadence-quadspi: add runtime pm support") Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-2-6b6af8bcbf59@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
32ce3bb5 |
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22-Feb-2024 |
Théo Lebrun <theo.lebrun@bootlin.com> |
spi: cadence-qspi: fix pointer reference in runtime PM hooks dev_get_drvdata() gets used to acquire the pointer to cqspi and the SPI controller. Neither embed the other; this lead to memory corruption. On a given platform (Mobileye EyeQ5) the memory corruption is hidden inside cqspi->f_pdata. Also, this uninitialised memory is used as a mutex (ctlr->bus_lock_mutex) by spi_controller_suspend(). Fixes: 2087e85bb66e ("spi: cadence-quadspi: fix suspend-resume implementations") Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://msgid.link/r/20240222-cdns-qspi-pm-fix-v4-1-6b6af8bcbf59@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
5cb47517 |
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29-Nov-2023 |
Yang Yingliang <yangyingliang@huawei.com> |
spi: cadence-quadspi: add missing clk_disable_unprepare() in cqspi_probe() cqspi_jh7110_clk_init() is called after clk_prepare_enable(cqspi->clk), if it fails, it should goto label 'probe_reset_failed' to disable cqspi->clk. In the error path after calling cqspi_jh7110_clk_init(), cqspi_jh7110_disable_clk() need be called. Fixes: 33f1ef6d4eb6 ("spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20231129081147.628004-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
86401132 |
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19-Sep-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: spi-cadence-quadspi: Fix missing unwind goto warnings The following smatch warnings [0] were recently introduced: drivers/spi/spi-cadence-quadspi.c:1882 cqspi_probe() warn: missing unwind goto? Fix these warnings by releasing dma channel and adding a goto fail probe. [0] https://lore.kernel.org/all/5e21c351-cd08-443e-8509-aecf242a4da9@kadam.mountain/ Fixes: 0578a6dbfe75 ("spi: spi-cadence-quadspi: add runtime pm support") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/202309140543.03dMbMM5-lkp@intel.com/ Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230919074658.41666-1-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
0578a6db |
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29-Aug-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: spi-cadence-quadspi: add runtime pm support Add runtime pm support to cadence-qspi driver, this allows the driver to suspend whenever it's is not actively being used thus reducing active power consumed by the system. Also, with the use of devm_pm_runtime_enable we no longer need the fallback probe_pm_failed that used to pm_runtime_disable Co-developed-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230829062706.786637-1-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
1c75d749 |
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07-Aug-2023 |
Yang Yingliang <yangyingliang@huawei.com> |
spi: cadence-quadspi: switch to use modern name Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230807140717.3484180-11-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
33f1ef6d |
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03-Aug-2023 |
William Qiu <william.qiu@starfivetech.com> |
spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Add JH7110's clock initialization code to the driver. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230804020254.291239-3-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
749396cb |
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14-Jul-2023 |
Rob Herring <robh@kernel.org> |
spi: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230714174955.4064174-1-robh@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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#
947c70a2 |
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06-Jun-2023 |
Jiasheng Jiang <jiasheng@iscas.ac.cn> |
spi: cadence-quadspi: Add missing check for dma_set_mask Add check for dma_set_mask() and return the error if it fails. Fixes: 1a6f854f7daa ("spi: cadence-quadspi: Add Xilinx Versal external DMA support") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Link: https://lore.kernel.org/r/20230606093859.27818-1-jiasheng@iscas.ac.cn Signed-off-by: Mark Brown <broonie@kernel.org>
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#
f5c2f9f9 |
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15-May-2023 |
Brad Larson <blarson@amd.com> |
spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson <blarson@amd.com Link: https://lore.kernel.org/r/20230515181606.65953-8-blarson@amd.com Signed-off-by: Mark Brown <broonie@kernel.org
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#
be3206e8 |
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19-Apr-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS Using this macro makes the code more readable. It also inits the members of dev_pm_ops in the following manner without us explicitly needing to: .suspend = cqspi_suspend, \ .resume = cqspi_resume, \ .freeze = cqspi_suspend, \ .thaw = cqspi_resume, \ .poweroff = cqspi_suspend, \ .restore = cqspi_resume Also get rid of conditional compilation based on CONFIG_PM_SLEEP because it introduces build issues with certain configs when CQSPI_DEV_PM_OPS is just NULL. Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202304191900.2fARFQW9-lkp@intel.com/ Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230420054257.925092-1-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
2087e85bb |
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17-Apr-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: fix suspend-resume implementations The cadence QSPI driver misbehaves after performing a full system suspend resume: ... spi-nor spi0.0: resume() failed ... This results in a flash connected via OSPI interface after system suspend- resume to be unusable. fix these suspend and resume functions. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230417091027.966146-3-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
c0b53f4e |
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20-Mar-2023 |
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> |
spi: cadence-quadspi: Disable the SPI before reconfiguring Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Link: https://lore.kernel.org/r/20230320095931.2651714-3-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
22c8ce0a |
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20-Mar-2023 |
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> |
spi: cadence-quadspi: Update the read timeout based on the length When performing indirect read via external DMA the timeout for completion is set equal to the read length instead of fixed timeout value. For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Link: https://lore.kernel.org/r/20230320095931.2651714-2-sai.krishna.potthuri@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
9e264f3f |
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10-Mar-2023 |
Amit Kumar Mahapatra via Alsa-devel <alsa-devel@alsa-project.org> |
spi: Replace all spi->chip_select and spi->cs_gpiod references with function call Supporting multi-cs in spi drivers would require the chip_select & cs_gpiod members of struct spi_device to be an array. But changing the type of these members to array would break the spi driver functionality. To make the transition smoother introduced four new APIs to get/set the spi->chip_select & spi->cs_gpiod and replaced all spi->chip_select and spi->cs_gpiod references with get or set API calls. While adding multi-cs support in further patches the chip_select & cs_gpiod members of the spi_device structure would be converted to arrays & the "idx" parameter of the APIs would be used as array index i.e., spi->chip_select[idx] & spi->cs_gpiod[idx] respectively. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Acked-by: Heiko Stuebner <heiko@sntech.de> # Rockchip drivers Reviewed-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> # Aspeed driver Reviewed-by: Dhruva Gole <d-gole@ti.com> # SPI Cadence QSPI Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> # spi-stm32-qspi Acked-by: William Zhang <william.zhang@broadcom.com> # bcm63xx-hsspi driver Reviewed-by: Serge Semin <fancer.lancer@gmail.com> # DW SSI part Link: https://lore.kernel.org/r/167847070432.26.15076794204368669839@mailman-core.alsa-project.org Signed-off-by: Mark Brown <broonie@kernel.org>
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#
6fe41879 |
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03-Mar-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
spi: cadence-quadspi: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230303172041.2103336-16-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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#
47fef94a |
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02-Mar-2023 |
William Qiu <william.qiu@starfivetech.com> |
spi: cadence-quadspi: Add support for StarFive JH7110 QSPI Add QSPI reset operation in device probe and add RISCV support to QUAD SPI Kconfig. Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230302105221.197421-3-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
152ac606 |
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22-Feb-2023 |
Hongbin Ji <jhb_ee@163.com> |
spi: cadence-quadspi: Fix cancel the indirect read mask This is to cancel the indirect read transfer process, so should be use CQSPI_REG_INDIRECTRD_CANCEL_MASK Signed-off-by: Hongbin Ji <jhb_ee@163.com> Link: https://lore.kernel.org/r/20230222092128.4237-1-jhb_ee@163.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
d403fb6e |
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25-Jan-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: use STIG mode for small reads Fix the issue where some flash chips like cypress S25HS256T return the value of the same register over and over in DAC mode. For example in the TI K3-AM62x Processors refer [0] Technical Reference Manual there is a layer of digital logic in front of the QSPI/OSPI Drive when used in DAC mode. This is part of the Flash Subsystem (FSS) which provides access to external Flash devices. The FSS0_0_SYSCONFIG Register (Offset = 4h) has a BIT Field for OSPI_32B_DISABLE_MODE which has a Reset value = 0. This means, OSPI 32bit mode enabled by default. Thus, by default controller operates in 32 bit mode causing it to always align all data to 4 bytes from a 4byte aligned address. In some flash chips like cypress for example if we try to read some regs in DAC mode then it keeps sending the value of the first register that was requested and inorder to read the next reg, we have to stop and re-initiate a new transaction. This causes wrong register values to be read than what is desired when registers are read in DAC mode. Hence if the data.nbytes is very less then prefer STIG mode for such small reads. [0] https://www.ti.com/lit/ug/spruiv7a/spruiv7a.pdf Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-5-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
a8674ae0 |
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25-Jan-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: setup ADDR Bits in cmd reads Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-4-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
e8c51b16 |
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25-Jan-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: Add flag for direct mode writes Create new flag inorder to avoid playing with use_direct_mode flag currently being used throughout the driver. Disable DAC write if auto polling is disabled or CQSPI_DISABLE_DAC_MODE is set. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-3-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
d4f43a2d |
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25-Jan-2023 |
Dhruva Gole <d-gole@ti.com> |
spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause issues in future command reads. This issue came to light when some flash reads in STIG mode were coming back dirty. Signed-off-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230125081023.1573712-2-d-gole@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
f8fc65e5 |
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28-Nov-2022 |
Nathan Barrett-Morrison <nathan.morrison@timesys.com> |
spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation This Cadence QSPI IP has a 4-bit clock divisor field for baud rate division. For example: 0b0000 = /2 0b0001 = /4 0b0010 = /6 ... 0b1111 = /32 The maximum divisor is 32 (when div = CQSPI_REG_CONFIG_BAUD_MASK). If we assume a reference clock of 500MHz and we set our spi-max-frequency to something low, such as 10 MHz. The calculated bit field for the divisor ends up being: DIV_ROUND_UP(500000000/(2*10000000))-1 = 25 25 is 0b11001... which truncates to a divisor field of 0b1001 (or /20). This is higher than our anticipated max-frequency of 10MHz (500MHz/20 = 25 MHz). Instead, let's make sure we're always using the maximum divisor (/32) in this case and give the user a warning about the rate adjustment. Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Link: https://lore.kernel.org/r/20221128164147.158441-1-nathan.morrison@timesys.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
4e12ef2b |
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28-Sep-2022 |
Yang Yingliang <yangyingliang@huawei.com> |
spi: cadence-quadspi: Use devm_platform_{get_and_}ioremap_resource() Use the devm_platform_{get_and}_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220928145852.1882221-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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4d0ef0a1 |
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24-Sep-2022 |
Zhang Qilong <zhangqilong3@huawei.com> |
spi: cadence-quadspi: Fix PM disable depth imbalance in cqspi_probe The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes:73d5fe0462702 ("spi: cadence-quadspi: Remove spi_master_put() in probe failure path") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20220924121310.78331-2-zhangqilong3@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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9ee5b6d5 |
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12-Aug-2022 |
Niravkumar L Rabara <niravkumar.l.rabara@intel.com> |
spi: cadence-quadspi: Disable irqs during indirect reads On architecture where reading the SRAM is slower than the pace at controller fills it, with interrupt enabled while reading from SRAM FIFO causes unwanted interrupt storm to CPU. The inner "bytes to read" loop never exits and waits for the completion so it is enough to only enable the watermark interrupt when we are out of bytes to read, which only happens when we start the transfer (waiting for the FIFO to fill up initially) if the SRAM is slow. So only using read watermark interrupt, as the current implementation doesn't utilize the SRAM full and indirect complete read interrupt. And disable all the read interrupts while reading from SRAM. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Link: https://lore.kernel.org/r/20220813042616.1372110-1-niravkumar.l.rabara@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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8523c968 |
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31-May-2022 |
Vaishnav Achath <vaishnav.a@ti.com> |
spi: cadence-quadspi: Remove spi_master_put() in probe failure path Currently the spi_master is allocated by devm_spi_alloc_master() and devres core manages the deallocation, but in probe failure path spi_master_put() is being handled manually which causes "refcount underflow use-after-free" warning when probe failure happens after allocating spi_master. Trimmed backtrace during failure: refcount_t: underflow; use-after-free. pc : refcount_warn_saturate+0xf4/0x144 Call trace: refcount_warn_saturate kobject_put put_device devm_spi_release_controller devres_release_all This commit makes relevant changes to remove spi_master_put() from probe failure path. Fixes: 606e5d408184 ("spi: cadence-quadspi: Handle spi_unregister_master() in remove()") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220601071611.11853-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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73d5fe04 |
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31-May-2022 |
Vaishnav Achath <vaishnav.a@ti.com> |
spi: cadence-quadspi: Remove spi_master_put() in probe failure path Currently the spi_master is allocated by devm_spi_alloc_master() and devres core manages the deallocation, but in probe failure path spi_master_put() is being handled manually which causes "refcount underflow use-after-free" warning when probe failure happens after allocating spi_master. Trimmed backtrace during failure: refcount_t: underflow; use-after-free. pc : refcount_warn_saturate+0xf4/0x144 Call trace: refcount_warn_saturate kobject_put put_device devm_spi_release_controller devres_release_all This commit makes relevant changes to remove spi_master_put() from probe failure path. Fixes: 606e5d408184 ("spi: cadence-quadspi: Handle spi_unregister_master() in remove()") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220601071611.11853-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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606e5d40 |
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11-May-2022 |
Vaishnav Achath <vaishnav.a@ti.com> |
spi: cadence-quadspi: Handle spi_unregister_master() in remove() Currently devres managed removal of the spi_controller happens after removing the power domain of the host platform_device.While this does not affect the clean removal of the controller, but affects graceful removal of the child devices if the child device removal requires issuing commands over SPI. Eg. flash device being soft reset to 1S-1S-1S mode before removal so that on next probe operations in 1S-1S-1S mode is successful. Failure is seen when `rmmod spi-cadence-quadspi` is performed: root@j7-evm:~# rmmod spi_cadence_quadspi [ 49.230996] cadence-qspi 47050000.spi: QSPI is still busy after 500ms timeout. [ 49.238209] spi-nor spi1.0: operation failed with -110 [ 49.244457] spi-nor spi1.0: Software reset failed: -110 and on subsequent modprobe the OSPI flash probe fails as it is in 8D-8D-8D mode since the previous soft reset did not happen. root@j7-evm:~# modprobe spi_cadence_quadspi [ 73.253536] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff [ 73.260476] spi-nor: probe of spi0.0 failed with error -2 This commit adds necessary changes to perform spi_unregister_master() in the host device remove() so that the child devices are gracefully removed before the power domain is removed. changes tested on J721E with mt35xu512aba flash. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Link: https://lore.kernel.org/r/20220511115516.14894-1-vaishnav.a@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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0d868829 |
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09-May-2022 |
Ian Abbott <abbotti@mev.co.uk> |
spi: cadence-quadspi: remove unnecessary (void *) casts Remove a couple of unnecessary casts to `(void *)` when initializing the `.data` members in the device ID table. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Link: https://lore.kernel.org/r/20220510115141.212779-3-abbotti@mev.co.uk Signed-off-by: Mark Brown <broonie@kernel.org>
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76159e2f |
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09-May-2022 |
Ian Abbott <abbotti@mev.co.uk> |
spi: cadence-quadspi: Add missing blank line in cqspi_request_mmap_dma() Fix "WARNING: Missing a blank line after declarations" reported by checkpatch.pl. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Link: https://lore.kernel.org/r/20220510115141.212779-2-abbotti@mev.co.uk Signed-off-by: Mark Brown <broonie@kernel.org>
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f724c296 |
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27-Apr-2022 |
Ian Abbott <abbotti@mev.co.uk> |
spi: cadence-quadspi: fix Direct Access Mode disable for SoCFPGA The Cadence QSPI compatible string required for the SoCFPGA platform changed from the default "cdns,qspi-nor" to "intel,socfpga-qspi" with the introduction of an additional quirk in commit 98d948eb8331 ("spi: cadence-quadspi: fix write completion support"). However, that change did not preserve the previously used quirk for this platform. Reinstate the `CQSPI_DISABLE_DAC_MODE` quirk for the SoCFPGA platform. Fixes: 98d948eb8331 ("spi: cadence-quadspi: fix write completion support") Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Link: https://lore.kernel.org/r/20220427153446.10113-1-abbotti@mev.co.uk Signed-off-by: Mark Brown <broonie@kernel.org>
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b7be05d5 |
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14-Apr-2022 |
Minghao Chi <chi.minghao@zte.com.cn> |
spi: spi-cadence-quadspi: using pm_runtime_resume_and_get instead of pm_runtime_get_sync Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220414085637.2541805-1-chi.minghao@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
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1aeda096 |
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20-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
spi: cadence-quadspi: allow operations with cmd/addr buswidth >1 With the removal of the incorrect logic of cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previously allowed 8-8-8 ops). Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-2-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
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28ac902a |
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20-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
spi: cadence-quadspi: drop cqspi_set_protocol() As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220420155616.281730-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
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f1d388f2 |
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06-Apr-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
spi: cadence-quadspi: fix incorrect supports_op() return value Since the conversion to spi-mem, the driver advertised support for various operations that cqspi_set_protocol() was never expected to handle correctly - in particuar all non-DTR operations with command or address buswidth > 1. For DTR, all operations except for 8-8-8 would fail, as cqspi_set_protocol() returns -EINVAL. In non-DTR mode, this resulted in data corruption for SPI-NOR flashes that support such operations. As a minimal fix that can be backported to stable kernels, simply disallow the unsupported operations again to avoid this issue. Fixes: a314f6367787 ("mtd: spi-nor: Convert cadence-quadspi to use spi-mem framework") Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220406132832.199777-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
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#
97e4827d |
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31-Mar-2022 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
spi: cadence-quadspi: fix protocol setup for non-1-1-X operations cqspi_set_protocol() only set the data width, but ignored the command and address width (except for 8-8-8 DTR ops), leading to corruption of all transfers using 1-X-X or X-X-X ops. Fix by setting the other two widths as well. While we're at it, simplify the code a bit by replacing the CQSPI_INST_TYPE_* constants with ilog2(). Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash with 1-4-4 read and write operations. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20220331110819.133392-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Mark Brown <broonie@kernel.org>
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9a15efc5 |
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27-Jan-2022 |
Miquel Raynal <miquel.raynal@bootlin.com> |
spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper Now that spi_mem_default_supports_op() has access to the static controller capabilities (relating to memory operations), and now that these capabilities have been filled by the relevant controllers, there is no need for a specific helper checking only DTR operations, so let's just kill spi_mem_dtr_supports_op() and simply use spi_mem_default_supports_op() instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com
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a9be4549 |
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27-Jan-2022 |
Miquel Raynal <miquel.raynal@bootlin.com> |
spi: cadence-quadspi: Provide a capability structure This controller has DTR support, so advertize it with a capability now that the spi-controller structure contains this new field. This will later be used by the core to discriminate whether an operation is supported or not, in a more generic way than having different helpers. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-4-miquel.raynal@bootlin.com
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#
98d948eb |
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08-Nov-2021 |
Dinh Nguyen <dinguyen@kernel.org> |
spi: cadence-quadspi: fix write completion support Some versions of the Cadence QSPI controller does not have the write completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is not configured. Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register. Fixes: 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling) Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211108200854.3616121-1-dinguyen@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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d9c55c95 |
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13-Oct-2021 |
Arnd Bergmann <arnd@arndb.de> |
spi: cadence-quadspi: fix dma_unmap_single() call There are separate constants for the dma-mapping API and the dmaengine API, mixing them up causes a warning in some builds: In file included from drivers/spi/spi-cadence-quadspi.c:12: drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_versal_indirect_read_dma': drivers/spi/spi-cadence-quadspi.c:950:55: error: implicit conversion from 'enum dma_transfer_direction' to 'enum dma_data_direction' [-Werror=enum-conversion] 950 | dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_DEV_TO_MEM); | ^~~~~~~~~~~~~~ include/linux/dma-mapping.h:407:70: note: in definition of macro 'dma_unmap_single' 407 | #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0) | ^ Fixes: 1a6f854f7daa ("spi: cadence-quadspi: Add Xilinx Versal external DMA support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211013144600.2378037-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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1a6f854f |
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24-Sep-2021 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
spi: cadence-quadspi: Add Xilinx Versal external DMA support Add support to read the data from the flash using external DMA. Cadence Octal SPI Flash Controller has optional DMA peripheral interface to communicate indirect mode of operations with external DMA. Xilinx Versal OSPI has external DMA enabled, this will automatically request the external DMA to fetch the data from SRAM. It supports only reading the data from SRAM (DMA read) and doesn't support writing the data to SRAM (DMA write). Xilinx Versal OSPI read the data from the flash device using external DMA and write the data to the flash device using software triggered indirect mode. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1632478031-12242-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
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09e393e3 |
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24-Sep-2021 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC Add OSPI support for Xilinx Versal SoCs. Disable the Direct Access Controller for Xilinx Versal OSPI. On Xilinx Versal platform, AXI interface need to be selected as Linear mode (driven from interconnect rather than external DMA) to use Software triggered 'indirect' mode of operation. This will be achieved by calling Xilinx firmware API. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1632478031-12242-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Mark Brown <broonie@kernel.org>
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0395be96 |
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16-Jul-2021 |
Apurva Nandan <a-nandan@ti.com> |
spi: cadence-quadspi: Fix check condition for DTR ops buswidth and dtr fields in spi_mem_op are only valid when the corresponding spi_mem_op phase has a non-zero length. For example, SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR phase. Fix the dtr checks in set_protocol() and suppports_mem_op() to ignore empty spi_mem_op phases, as checking for dtr field in empty phase will result in false negatives. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20210716232504.182-3-a-nandan@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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9cb2ff11 |
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12-Jul-2021 |
Apurva Nandan <a-nandan@ti.com> |
spi: cadence-quadspi: Disable Auto-HW polling cadence-quadspi has a builtin Auto-HW polling funtionality using which it keep tracks of completion of write operations. When Auto-HW polling is enabled, it automatically initiates status register read operation, until the flash clears its busy bit. cadence-quadspi controller doesn't allow an address phase when auto-polling the busy bit on the status register. Unlike SPI NOR flashes, SPI NAND flashes do require the address of status register when polling the busy bit using the read register operation. As Auto-HW polling is enabled by default, cadence-quadspi returns a timeout for every write operation after an indefinite amount of polling on SPI NAND flashes. Disable Auto-HW polling completely as the spi-nor core, spinand core, etc. take care of polling the busy bit on their own. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Link: https://lore.kernel.org/r/20210713125743.1540-2-a-nandan@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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0e85ee89 |
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16-Jul-2021 |
Yoshitaka Ikeda <ikeda@nskint.co.jp> |
spi: spi-cadence-quadspi: Fix division by zero warning Fix below division by zero warning: - The reason for dividing by zero is because the dummy bus width is zero, but if the dummy n bytes is zero, it indicates that there is no data transfer, so we can just return zero without doing any calculations. [ 0.795337] Division by zero in kernel. : [ 0.834051] [<807fd40c>] (__div0) from [<804e1acc>] (Ldiv0+0x8/0x10) [ 0.839097] [<805f0710>] (cqspi_exec_mem_op) from [<805edb4c>] (spi_mem_exec_op+0x3b0/0x3f8) Fixes: 7512eaf54190 ("spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1") Signed-off-by: Yoshitaka Ikeda <ikeda@nskint.co.jp> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/92eea403-9b21-2488-9cc1-664bee760c5e@nskint.co.jp Signed-off-by: Mark Brown <broonie@kernel.org>
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0ccfd1ba |
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16-Jul-2021 |
Yoshitaka Ikeda <ikeda@nskint.co.jp> |
spi: spi-cadence-quadspi: Revert "Fix division by zero warning" Revert to change to a better code. This reverts commit 55cef88bbf12f3bfbe5c2379a8868a034707e755. Signed-off-by: Yoshitaka Ikeda <ikeda@nskint.co.jp> Link: https://lore.kernel.org/r/bd30bdb4-07c4-f713-5648-01c898d51f1b@nskint.co.jp Signed-off-by: Mark Brown <broonie@kernel.org>
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55cef88b |
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15-Jul-2021 |
Yoshitaka Ikeda <ikeda@nskint.co.jp> |
spi: spi-cadence-quadspi: Fix division by zero warning Fix below division by zero warning: - Added an if statement because buswidth can be zero, resulting in division by zero. - The modified code was based on another driver (atmel-quadspi). [ 0.795337] Division by zero in kernel. : [ 0.834051] [<807fd40c>] (__div0) from [<804e1acc>] (Ldiv0+0x8/0x10) [ 0.839097] [<805f0710>] (cqspi_exec_mem_op) from [<805edb4c>] (spi_mem_exec_op+0x3b0/0x3f8) Fixes: 7512eaf54190 ("spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1") Signed-off-by: Yoshitaka Ikeda <ikeda@nskint.co.jp> Link: https://lore.kernel.org/r/ed989af6-da88-4e0b-9ed8-126db6cad2e4@nskint.co.jp Signed-off-by: Mark Brown <broonie@kernel.org>
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31890269 |
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04-Mar-2021 |
Jay Fang <f.fangjian@huawei.com> |
spi: cadence-quadspi: Silence shiftTooManyBitsSigned warning drivers/spi/spi-cadence-quadspi.c:267:18: warning: Shifting signed 32-bit value by 31 bits is undefined behaviour [shiftTooManyBitsSigned] return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB); ^ Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1614854872-8694-1-git-send-email-f.fangjian@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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87d62d8f |
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15-Feb-2021 |
Junlin Yang <yangjunlin@yulong.com> |
spi: cadence-quadspi: add missing of_node_put Fix OF node leaks by calling of_node_put in for_each_available_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210215110425.1012-1-angkery@163.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ea94191e |
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11-Mar-2021 |
Meng Li <Meng.Li@windriver.com> |
spi: cadence: set cqspi to the driver_data field of struct device When initialize cadence qspi controller, it is need to set cqspi to the driver_data field of struct device, because it will be used in function cqspi_remove/suspend/resume(). Otherwise, there will be a crash trace as below when invoking these finctions. Fixes: 31fb632b5d43 ("spi: Move cadence-quadspi driver to drivers/spi/") Cc: stable@vger.kernel.org Signed-off-by: Meng Li <Meng.Li@windriver.com> Link: https://lore.kernel.org/r/20210311091220.3615-1-Meng.Li@windriver.com Signed-off-by: Mark Brown <broonie@kernel.org>
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d2275139 |
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04-Feb-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Use spi_mem_dtr_supports_op() Use the newly introduced spi_mem_dtr_supports_op() to check DTR op support. This means the buswidth check does not need to be replicated. It also happens to fix a bug where STR ops with a 2-byte opcode would be reported as supported. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20210204141218.32229-2-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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b436fb7d |
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23-Nov-2020 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ad2775dc |
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23-Nov-2020 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
spi: cadence-quadspi: Disable the DAC for Intel LGM SoC On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use Direct Access Controller(DAC). This patch adds a quirk to disable the Direct Access Controller for data transfer instead it uses indirect data transfe DAC bit resets to 1 so there is no need to explicitly set it. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ab2d2875 |
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23-Nov-2020 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
spi: cadence-quadspi: Add QSPI support for Intel LGM SoC Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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2ef0170e |
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08-Jan-2021 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Fix build warning on 32-bit platforms The kernel test robot reports the following warning. drivers/spi/spi-cadence-quadspi.c:966:24: warning: comparison of distinct pointer types ('typeof (len) *' (aka 'unsigned int *') and 'typeof (500UL) *' (aka 'unsigned long *')) [-Wcompare-distinct-pointer-types] msecs_to_jiffies(max(len, 500UL)))) { ^~~~~~~~~~~~~~~ include/linux/minmax.h:58:19: note: expanded from macro 'max' #define max(x, y) __careful_cmp(x, y, >) ^~~~~~~~~~~~~~~~~~~~~~ include/linux/minmax.h:42:24: note: expanded from macro '__careful_cmp' __builtin_choose_expr(__safe_cmp(x, y), \ ^~~~~~~~~~~~~~~~ include/linux/minmax.h:32:4: note: expanded from macro '__safe_cmp' (__typecheck(x, y) && __no_side_effects(x, y)) ^~~~~~~~~~~~~~~~~ include/linux/minmax.h:18:28: note: expanded from macro '__typecheck' (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) ~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~ 1 warning generated. This happens because size_t is unsigned long on 64-bit platforms like arm64 but it is unsigned int on 32-bit platforms like arm. Omitting the "UL" would result in a warning on 64-bit platforms. Squash it by type casting the arguments to size_t using max_t(). This way builds on both type of platforms can be satisfied. There is no chance of any truncation since 500 is small enough to fit into both int and long. Fixes: f453f293979f ("spi: cadence-quadspi: Wait at least 500 ms for direct reads") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20210108181457.30291-1-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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8728a81b |
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07-Jan-2021 |
Yanteng Si <siyanteng@loongson.cn> |
spi: Fix distinct pointer types warning for ARCH=mips Fix a new warning report by build for make ARCH=MIPS allmodconfig: drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_direct_read_execute': ./include/linux/minmax.h:18:28: warning: comparison of distinct pointer types lacks a cast 18 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) | ^~ ./include/linux/minmax.h:32:4: note: in expansion of macro '__typecheck' 32 | (__typecheck(x, y) && __no_side_effects(x, y)) | ^~~~~~~~~~~ ./include/linux/minmax.h:42:24: note: in expansion of macro '__safe_cmp' 42 | __builtin_choose_expr(__safe_cmp(x, y), \ | ^~~~~~~~~~ ./include/linux/minmax.h:58:19: note: in expansion of macro '__careful_cmp' 58 | #define max(x, y) __careful_cmp(x, y, >) | ^~~~~~~~~~~~~ drivers/spi/spi-cadence-quadspi.c:1153:24: note: in expansion of macro 'max' 1153 | msecs_to_jiffies(max(len, 500UL)))) { | ^~~ "len" is unsigned,however,"500" is unsigned long. Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Link: https://lore.kernel.org/r/20210107115704.3835282-1-siyanteng@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
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f453f293 |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Add DTR support Double Transfer Rate (DTR) mode transfers data twice per clock cycle. Add support for parsing DTR ops and set up the registers to allow it. Most SPI NOR flashes expect 2 byte commands. Parse the 2-byte opcode from SPI MEM and set it up in the CQSPI_REG_OP_EXT_LOWER register. Increment the delay needed before issuing indirect writes because larger delay is needed for DTR mode. With the current delay some writes end up missing. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-8-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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0920a32c |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Wait at least 500 ms for direct reads When performing a direct read via DMA the timeout for completion is set equal to the read length. This is fine for larger reads. For a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA. Make sure the timeout is at least 500 ms to allow DMA ample time to finish. For reads larger than 500 bytes, the timeout will continue to be equal to the read length. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20201222184425.7028-7-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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a273596b |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Implement a simple supports_op hook The default SPI MEM supports_op hook rejects DTR ops by default. Add a simple supports_op hook that very closely imitates the SPI MEM one. It will be extended in later commits to allow DTR ops. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-6-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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7512eaf541 |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1 SPI MEM deals with dummy bytes but the controller deals with dummy cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses 4S mode then 1 byte will be sent in 2 cycles. To correctly translate dummy bytes to dummy cycles, the dummy buswidth also needs to be taken into account. Divide 8 by the buswidth to get the correct multiplier for getting the number of cycles. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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888d517b |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Set dummy cycles from STIG commands If a command does not have an address phase it goes via the STIG path. The dummy cycles are not initialized for the STIG commands. As a result, STIG commands with dummy cycles will not work. Initialize the dummy cycle field before issuing the STIG command to make sure it is sent correctly. Move the code to calculate dummy cycle value to a separate function so it is not repeated twice. DTR support will add some more logic here to it is worth it to extract it out in a function. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-4-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ceeda328 |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Abort read if dummy cycles required are too many The controller can only support up to 31 dummy cycles. If the command requires more it falls back to using 31. This command is likely to fail because the correct number of cycles are not waited upon. Rather than silently issuing an incorrect command, fail loudly so the caller can get a chance to find out the command can't be supported by the controller. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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3a5c09c8 |
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22-Dec-2020 |
Pratyush Yadav <p.yadav@ti.com> |
spi: cadence-quadspi: Set master max_speed_hz As of commit 9326e4f1e5dd ("spi: Limit the spi device max speed to controller's max speed"), the SPI device max speed is set to the controller's max speed if it is larger. The Cadence QSPI controller does not set the controller's max speed so it is left at its initial value of 0. This means the SPI device max speed is always set to 0. The SPI device max speed is used to calculate the baud rate divider when performing an operation. If this speed is 0, the default divider of 32 is used. No matter what speed is specified by the device tree property 'spi-max-frequency', the device will always operate at ref_clk / 32. Fix this by setting master->max_speed_hz to the ref clock speed so the correct divider can be calculated. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-2-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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ac9978fc |
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16-Nov-2020 |
Zhihao Cheng <chengzhihao1@huawei.com> |
spi: cadence-quadspi: Fix error return code in cqspi_probe Fix to return the error code from devm_reset_control_get_optional_exclusive() instaed of 0 in cqspi_probe(). Fixes: 31fb632b5d43ca ("spi: Move cadence-quadspi driver to drivers/spi/") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20201116141836.2970579-1-chengzhihao1@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
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436a5c20 |
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01-Sep-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
spi: cadence-quadspi: Simplify with dev_err_probe() Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200901152713.18629-5-krzk@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
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83048015 |
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31-Aug-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: spi-cadence-quadspi: Fix mapping of buffers for DMA reads Buffers need to mapped to DMA channel's device pointer instead of SPI controller's device pointer as its system DMA that actually does data transfer. Data inconsistencies have been reported when reading from flash without this fix. Fixes: ffa639e069fb ("mtd: spi-nor: cadence-quadspi: Add DMA support for direct mode reads") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/20200831130720.4524-1-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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2ea370a9 |
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25-Aug-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
spi: spi-cadence-quadspi: Populate get_name() interface Implement get_name() interface of spi_controller_mem_ops so as to avoid changing of mtd->name due to driver being moved over to spi-mem framework from SPI NOR. This avoids breaking of MTD cmdline args being passed by bootloaders which maybe using old driver name. Fixes: 31fb632b5d43c ("spi: Move cadence-quadspi driver to drivers/spi/") Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200825172506.14375-1-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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31fb632b |
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31-May-2020 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
spi: Move cadence-quadspi driver to drivers/spi/ Now that cadence-quadspi has been converted to use spi-mem framework, move it under drivers/spi/ Update license header to match SPI subsystem style Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-9-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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