1124208Sdes// SPDX-License-Identifier: GPL-2.0-or-later 2124208Sdes/* 3124208Sdes * Rockchip Successive Approximation Register (SAR) A/D Converter 4124208Sdes * Copyright (C) 2014 ROCKCHIP, Inc. 5124208Sdes */ 6124208Sdes 7124208Sdes#include <linux/bitfield.h> 8124208Sdes#include <linux/module.h> 9124208Sdes#include <linux/mutex.h> 10124208Sdes#include <linux/platform_device.h> 11124208Sdes#include <linux/interrupt.h> 12124208Sdes#include <linux/io.h> 13124208Sdes#include <linux/of.h> 14124208Sdes#include <linux/clk.h> 15124208Sdes#include <linux/completion.h> 16124208Sdes#include <linux/delay.h> 17124208Sdes#include <linux/reset.h> 18124208Sdes#include <linux/regulator/consumer.h> 19124208Sdes#include <linux/iio/buffer.h> 20124208Sdes#include <linux/iio/iio.h> 21124208Sdes#include <linux/iio/trigger_consumer.h> 22124208Sdes#include <linux/iio/triggered_buffer.h> 23124208Sdes 24124208Sdes#define SARADC_DATA 0x00 2598937Sdes 2698937Sdes#define SARADC_STAS 0x04 2798937Sdes#define SARADC_STAS_BUSY BIT(0) 2898937Sdes 2998937Sdes#define SARADC_CTRL 0x08 30162852Sdes#define SARADC_CTRL_IRQ_STATUS BIT(6) 3198937Sdes#define SARADC_CTRL_IRQ_ENABLE BIT(5) 3298937Sdes#define SARADC_CTRL_POWER_CTRL BIT(3) 3398937Sdes#define SARADC_CTRL_CHN_MASK 0x7 3498937Sdes 3598937Sdes#define SARADC_DLY_PU_SOC 0x0c 3698937Sdes#define SARADC_DLY_PU_SOC_MASK 0x3f 3798937Sdes 3898937Sdes#define SARADC_TIMEOUT msecs_to_jiffies(100) 3998937Sdes#define SARADC_MAX_CHANNELS 8 4098937Sdes 4198937Sdes/* v2 registers */ 42221420Sdes#define SARADC2_CONV_CON 0x000 43323129Sdes#define SARADC_T_PD_SOC 0x004 44323129Sdes#define SARADC_T_DAS_SOC 0x00c 45323129Sdes#define SARADC2_END_INT_EN 0x104 46323129Sdes#define SARADC2_ST_CON 0x108 47323129Sdes#define SARADC2_STATUS 0x10c 48323129Sdes#define SARADC2_END_INT_ST 0x110 49323129Sdes#define SARADC2_DATA_BASE 0x120 50323129Sdes 51323129Sdes#define SARADC2_EN_END_INT BIT(0) 52323129Sdes#define SARADC2_START BIT(4) 53323129Sdes#define SARADC2_SINGLE_MODE BIT(5) 54323129Sdes 55323129Sdes#define SARADC2_CONV_CHANNELS GENMASK(3, 0) 56221420Sdes 57221420Sdesstruct rockchip_saradc; 58221487Sdes 59221420Sdesstruct rockchip_saradc_data { 6098937Sdes const struct iio_chan_spec *channels; 6198937Sdes int num_channels; 6298937Sdes unsigned long clk_rate; 6398937Sdes void (*start)(struct rockchip_saradc *info, int chn); 6498937Sdes int (*read)(struct rockchip_saradc *info); 6598937Sdes void (*power_down)(struct rockchip_saradc *info); 6698937Sdes}; 6798937Sdes 68221420Sdesstruct rockchip_saradc { 69221420Sdes void __iomem *regs; 70221420Sdes struct clk *pclk; 71221420Sdes struct clk *clk; 72221420Sdes struct completion completion; 73221420Sdes struct regulator *vref; 74221420Sdes /* lock to protect against multiple access to the device */ 75221420Sdes struct mutex lock; 76221420Sdes int uv_vref; 77221420Sdes struct reset_control *reset; 78221420Sdes const struct rockchip_saradc_data *data; 79221420Sdes u16 last_val; 80221420Sdes const struct iio_chan_spec *last_chan; 81221420Sdes struct notifier_block nb; 82221420Sdes}; 83221420Sdes 84221420Sdesstatic void rockchip_saradc_reset_controller(struct reset_control *reset); 85221420Sdes 86221420Sdesstatic void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) 87221420Sdes{ 88221420Sdes /* 8 clock periods as delay between power up and start cmd */ 89221420Sdes writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); 90221420Sdes /* Select the channel to be used and trigger conversion */ 91221420Sdes writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) | 92221420Sdes SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); 93221420Sdes} 94221420Sdes 95221420Sdesstatic void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) 96221420Sdes{ 97221420Sdes int val; 98221420Sdes 99221420Sdes if (info->reset) 100240075Sdes rockchip_saradc_reset_controller(info->reset); 101240075Sdes 102240075Sdes writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); 103240075Sdes writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); 104240075Sdes val = FIELD_PREP(SARADC2_EN_END_INT, 1); 105240075Sdes val |= SARADC2_EN_END_INT << 16; 10698937Sdes writel_relaxed(val, info->regs + SARADC2_END_INT_EN); 10798937Sdes val = FIELD_PREP(SARADC2_START, 1) | 10898937Sdes FIELD_PREP(SARADC2_SINGLE_MODE, 1) | 10998937Sdes FIELD_PREP(SARADC2_CONV_CHANNELS, chn); 110149749Sdes val |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16; 111149749Sdes writel(val, info->regs + SARADC2_CONV_CON); 112149749Sdes} 113149749Sdes 114149749Sdesstatic void rockchip_saradc_start(struct rockchip_saradc *info, int chn) 11598937Sdes{ 11698937Sdes info->data->start(info, chn); 11798937Sdes} 118294332Sdes 119294332Sdesstatic int rockchip_saradc_read_v1(struct rockchip_saradc *info) 120294332Sdes{ 121294332Sdes return readl_relaxed(info->regs + SARADC_DATA); 122294332Sdes} 123294332Sdes 124294332Sdesstatic int rockchip_saradc_read_v2(struct rockchip_saradc *info) 125294332Sdes{ 126294332Sdes int offset; 127294332Sdes 128294332Sdes /* Clear irq */ 129181111Sdes writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); 130149749Sdes 131149749Sdes offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; 132149749Sdes 13398937Sdes return readl_relaxed(info->regs + offset); 13498937Sdes} 13598937Sdes 13698937Sdesstatic int rockchip_saradc_read(struct rockchip_saradc *info) 13798937Sdes{ 13898937Sdes return info->data->read(info); 13998937Sdes} 14098937Sdes 14198937Sdesstatic void rockchip_saradc_power_down_v1(struct rockchip_saradc *info) 14298937Sdes{ 14398937Sdes writel_relaxed(0, info->regs + SARADC_CTRL); 14498937Sdes} 14598937Sdes 14698937Sdesstatic void rockchip_saradc_power_down(struct rockchip_saradc *info) 14798937Sdes{ 14898937Sdes if (info->data->power_down) 14998937Sdes info->data->power_down(info); 15098937Sdes} 151162852Sdes 152162852Sdesstatic int rockchip_saradc_conversion(struct rockchip_saradc *info, 15398937Sdes struct iio_chan_spec const *chan) 15498937Sdes{ 155226046Sdes reinit_completion(&info->completion); 156226046Sdes 157226046Sdes info->last_chan = chan; 158226046Sdes rockchip_saradc_start(info, chan->channel); 15998937Sdes 16098937Sdes if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) 16198937Sdes return -ETIMEDOUT; 16298937Sdes 163126274Sdes return 0; 16498937Sdes} 16598937Sdes 16698937Sdesstatic int rockchip_saradc_read_raw(struct iio_dev *indio_dev, 16798937Sdes struct iio_chan_spec const *chan, 16898937Sdes int *val, int *val2, long mask) 16998937Sdes{ 17098937Sdes struct rockchip_saradc *info = iio_priv(indio_dev); 17198937Sdes int ret; 17298937Sdes 17398937Sdes switch (mask) { 17498937Sdes case IIO_CHAN_INFO_RAW: 17598937Sdes mutex_lock(&info->lock); 17698937Sdes 17798937Sdes ret = rockchip_saradc_conversion(info, chan); 17898937Sdes if (ret) { 17998937Sdes rockchip_saradc_power_down(info); 18098937Sdes mutex_unlock(&info->lock); 18198937Sdes return ret; 18298937Sdes } 18398937Sdes 18498937Sdes *val = info->last_val; 18598937Sdes mutex_unlock(&info->lock); 18698937Sdes return IIO_VAL_INT; 18798937Sdes case IIO_CHAN_INFO_SCALE: 18898937Sdes *val = info->uv_vref / 1000; 18998937Sdes *val2 = chan->scan_type.realbits; 19098937Sdes return IIO_VAL_FRACTIONAL_LOG2; 19198937Sdes default: 19298937Sdes return -EINVAL; 19398937Sdes } 19498937Sdes} 19598937Sdes 19698937Sdesstatic irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) 19798937Sdes{ 19898937Sdes struct rockchip_saradc *info = dev_id; 19998937Sdes 200106121Sdes /* Read value */ 20198937Sdes info->last_val = rockchip_saradc_read(info); 20298937Sdes info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); 20398937Sdes 20498937Sdes rockchip_saradc_power_down(info); 20598937Sdes 20698937Sdes complete(&info->completion); 20798937Sdes 20898937Sdes return IRQ_HANDLED; 20998937Sdes} 21098937Sdes 21198937Sdesstatic const struct iio_info rockchip_saradc_iio_info = { 21298937Sdes .read_raw = rockchip_saradc_read_raw, 213240075Sdes}; 21498937Sdes 21598937Sdes#define SARADC_CHANNEL(_index, _id, _res) { \ 21698937Sdes .type = IIO_VOLTAGE, \ 217106121Sdes .indexed = 1, \ 21898937Sdes .channel = _index, \ 21998937Sdes .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 22098937Sdes .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 22198937Sdes .datasheet_name = _id, \ 22298937Sdes .scan_index = _index, \ 22398937Sdes .scan_type = { \ 22498937Sdes .sign = 'u', \ 225106121Sdes .realbits = _res, \ 22698937Sdes .storagebits = 16, \ 22798937Sdes .endianness = IIO_CPU, \ 22898937Sdes }, \ 22998937Sdes} 230106121Sdes 23198937Sdesstatic const struct iio_chan_spec rockchip_saradc_iio_channels[] = { 23298937Sdes SARADC_CHANNEL(0, "adc0", 10), 23398937Sdes SARADC_CHANNEL(1, "adc1", 10), 234106121Sdes SARADC_CHANNEL(2, "adc2", 10), 23598937Sdes}; 23698937Sdes 23798937Sdesstatic const struct rockchip_saradc_data saradc_data = { 23898937Sdes .channels = rockchip_saradc_iio_channels, 23998937Sdes .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), 24098937Sdes .clk_rate = 1000000, 24198937Sdes .start = rockchip_saradc_start_v1, 24298937Sdes .read = rockchip_saradc_read_v1, 24398937Sdes .power_down = rockchip_saradc_power_down_v1, 24498937Sdes}; 24598937Sdes 24698937Sdesstatic const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { 24798937Sdes SARADC_CHANNEL(0, "adc0", 12), 24898937Sdes SARADC_CHANNEL(1, "adc1", 12), 24998937Sdes}; 250106121Sdes 25198937Sdesstatic const struct rockchip_saradc_data rk3066_tsadc_data = { 25298937Sdes .channels = rockchip_rk3066_tsadc_iio_channels, 25398937Sdes .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), 25498937Sdes .clk_rate = 50000, 25598937Sdes .start = rockchip_saradc_start_v1, 25698937Sdes .read = rockchip_saradc_read_v1, 25798937Sdes .power_down = rockchip_saradc_power_down_v1, 25898937Sdes}; 25998937Sdes 26098937Sdesstatic const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { 26198937Sdes SARADC_CHANNEL(0, "adc0", 10), 26298937Sdes SARADC_CHANNEL(1, "adc1", 10), 263106121Sdes SARADC_CHANNEL(2, "adc2", 10), 26498937Sdes SARADC_CHANNEL(3, "adc3", 10), 26598937Sdes SARADC_CHANNEL(4, "adc4", 10), 26698937Sdes SARADC_CHANNEL(5, "adc5", 10), 26798937Sdes}; 26898937Sdes 26998937Sdesstatic const struct rockchip_saradc_data rk3399_saradc_data = { 27098937Sdes .channels = rockchip_rk3399_saradc_iio_channels, 27198937Sdes .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), 27298937Sdes .clk_rate = 1000000, 27398937Sdes .start = rockchip_saradc_start_v1, 27498937Sdes .read = rockchip_saradc_read_v1, 27598937Sdes .power_down = rockchip_saradc_power_down_v1, 27698937Sdes}; 27798937Sdes 27898937Sdesstatic const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { 27998937Sdes SARADC_CHANNEL(0, "adc0", 10), 28098937Sdes SARADC_CHANNEL(1, "adc1", 10), 28198937Sdes SARADC_CHANNEL(2, "adc2", 10), 28298937Sdes SARADC_CHANNEL(3, "adc3", 10), 28398937Sdes SARADC_CHANNEL(4, "adc4", 10), 28498937Sdes SARADC_CHANNEL(5, "adc5", 10), 28598937Sdes SARADC_CHANNEL(6, "adc6", 10), 28698937Sdes SARADC_CHANNEL(7, "adc7", 10), 28798937Sdes}; 28898937Sdes 28998937Sdesstatic const struct rockchip_saradc_data rk3568_saradc_data = { 29098937Sdes .channels = rockchip_rk3568_saradc_iio_channels, 29198937Sdes .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels), 29298937Sdes .clk_rate = 1000000, 293261320Sdes .start = rockchip_saradc_start_v1, 294261320Sdes .read = rockchip_saradc_read_v1, 295261320Sdes .power_down = rockchip_saradc_power_down_v1, 296261320Sdes}; 297261320Sdes 298261320Sdesstatic const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { 299261320Sdes SARADC_CHANNEL(0, "adc0", 12), 300261320Sdes SARADC_CHANNEL(1, "adc1", 12), 301261320Sdes SARADC_CHANNEL(2, "adc2", 12), 302261320Sdes SARADC_CHANNEL(3, "adc3", 12), 303261320Sdes SARADC_CHANNEL(4, "adc4", 12), 304261320Sdes SARADC_CHANNEL(5, "adc5", 12), 305261320Sdes SARADC_CHANNEL(6, "adc6", 12), 306261320Sdes SARADC_CHANNEL(7, "adc7", 12), 307261320Sdes}; 30898937Sdes 30998937Sdesstatic const struct rockchip_saradc_data rk3588_saradc_data = { 31098937Sdes .channels = rockchip_rk3588_saradc_iio_channels, 31198937Sdes .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), 31298937Sdes .clk_rate = 1000000, 313248619Sdes .start = rockchip_saradc_start_v2, 314248619Sdes .read = rockchip_saradc_read_v2, 315248619Sdes}; 316248619Sdes 317106121Sdesstatic const struct of_device_id rockchip_saradc_match[] = { 318106121Sdes { 319106121Sdes .compatible = "rockchip,saradc", 320106121Sdes .data = &saradc_data, 32198937Sdes }, { 32298937Sdes .compatible = "rockchip,rk3066-tsadc", 32398937Sdes .data = &rk3066_tsadc_data, 324126274Sdes }, { 32598937Sdes .compatible = "rockchip,rk3399-saradc", 32698937Sdes .data = &rk3399_saradc_data, 327221420Sdes }, { 328221420Sdes .compatible = "rockchip,rk3568-saradc", 329221420Sdes .data = &rk3568_saradc_data, 330221420Sdes }, { 33198937Sdes .compatible = "rockchip,rk3588-saradc", 33298937Sdes .data = &rk3588_saradc_data, 33398937Sdes }, 33498937Sdes {}, 33598937Sdes}; 33698937SdesMODULE_DEVICE_TABLE(of, rockchip_saradc_match); 33798937Sdes 33898937Sdes/* 33998937Sdes * Reset SARADC Controller. 34098937Sdes */ 34198937Sdesstatic void rockchip_saradc_reset_controller(struct reset_control *reset) 34298937Sdes{ 34398937Sdes reset_control_assert(reset); 34498937Sdes usleep_range(10, 20); 34598937Sdes reset_control_deassert(reset); 34698937Sdes} 34798937Sdes 34898937Sdesstatic void rockchip_saradc_regulator_disable(void *data) 34998937Sdes{ 35098937Sdes struct rockchip_saradc *info = data; 35198937Sdes 35298937Sdes regulator_disable(info->vref); 35398937Sdes} 35498937Sdes 35598937Sdesstatic irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) 35698937Sdes{ 35798937Sdes struct iio_poll_func *pf = p; 35898937Sdes struct iio_dev *i_dev = pf->indio_dev; 35998937Sdes struct rockchip_saradc *info = iio_priv(i_dev); 36098937Sdes /* 36198937Sdes * @values: each channel takes an u16 value 36298937Sdes * @timestamp: will be 8-byte aligned automatically 36398937Sdes */ 36498937Sdes struct { 36598937Sdes u16 values[SARADC_MAX_CHANNELS]; 36698937Sdes int64_t timestamp; 36798937Sdes } data; 36898937Sdes int ret; 36998937Sdes int i, j = 0; 37098937Sdes 37198937Sdes mutex_lock(&info->lock); 372146998Sdes 373146998Sdes for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) { 374146998Sdes const struct iio_chan_spec *chan = &i_dev->channels[i]; 375197679Sdes 376197679Sdes ret = rockchip_saradc_conversion(info, chan); 377197679Sdes if (ret) { 378146998Sdes rockchip_saradc_power_down(info); 37998937Sdes goto out; 38098937Sdes } 38198937Sdes 38298937Sdes data.values[j] = info->last_val; 38398937Sdes j++; 38498937Sdes } 38598937Sdes 38698937Sdes iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev)); 38798937Sdesout: 38898937Sdes mutex_unlock(&info->lock); 389255767Sdes 390255767Sdes iio_trigger_notify_done(i_dev->trig); 39198937Sdes 39298937Sdes return IRQ_HANDLED; 39398937Sdes} 394255767Sdes 395255767Sdesstatic int rockchip_saradc_volt_notify(struct notifier_block *nb, 396255767Sdes unsigned long event, void *data) 397255767Sdes{ 398255767Sdes struct rockchip_saradc *info = 399255767Sdes container_of(nb, struct rockchip_saradc, nb); 400255767Sdes 401255767Sdes if (event & REGULATOR_EVENT_VOLTAGE_CHANGE) 40298937Sdes info->uv_vref = (unsigned long)data; 40398937Sdes 40498937Sdes return NOTIFY_OK; 40598937Sdes} 40698937Sdes 40798937Sdesstatic void rockchip_saradc_regulator_unreg_notifier(void *data) 40898937Sdes{ 40998937Sdes struct rockchip_saradc *info = data; 41098937Sdes 41198937Sdes regulator_unregister_notifier(info->vref, &info->nb); 41298937Sdes} 41398937Sdes 41498937Sdesstatic int rockchip_saradc_probe(struct platform_device *pdev) 41598937Sdes{ 41698937Sdes const struct rockchip_saradc_data *match_data; 41798937Sdes struct rockchip_saradc *info = NULL; 41898937Sdes struct device_node *np = pdev->dev.of_node; 419124208Sdes struct iio_dev *indio_dev = NULL; 420124208Sdes int ret; 421124208Sdes int irq; 422124208Sdes 42398937Sdes if (!np) 42498937Sdes return -ENODEV; 42598937Sdes 42698937Sdes indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); 427226046Sdes if (!indio_dev) 428226046Sdes return dev_err_probe(&pdev->dev, -ENOMEM, 429294328Sdes "failed allocating iio device\n"); 430226046Sdes 43198937Sdes info = iio_priv(indio_dev); 432226046Sdes 433226046Sdes match_data = of_device_get_match_data(&pdev->dev); 43498937Sdes if (!match_data) 43598937Sdes return dev_err_probe(&pdev->dev, -ENODEV, 43698937Sdes "failed to match device\n"); 43798937Sdes 43898937Sdes info->data = match_data; 43998937Sdes 44098937Sdes /* Sanity check for possible later IP variants with more channels */ 44198937Sdes if (info->data->num_channels > SARADC_MAX_CHANNELS) 44298937Sdes return dev_err_probe(&pdev->dev, -EINVAL, 44398937Sdes "max channels exceeded"); 44498937Sdes 44598937Sdes info->regs = devm_platform_ioremap_resource(pdev, 0); 44698937Sdes if (IS_ERR(info->regs)) 44798937Sdes return PTR_ERR(info->regs); 44898937Sdes 44998937Sdes /* 45098937Sdes * The reset should be an optional property, as it should work 45198937Sdes * with old devicetrees as well 45298937Sdes */ 45398937Sdes info->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 45498937Sdes "saradc-apb"); 45598937Sdes if (IS_ERR(info->reset)) { 45698937Sdes ret = PTR_ERR(info->reset); 45798937Sdes return dev_err_probe(&pdev->dev, ret, "failed to get saradc-apb\n"); 45898937Sdes } 45998937Sdes 46098937Sdes init_completion(&info->completion); 46198937Sdes 46298937Sdes irq = platform_get_irq(pdev, 0); 46398937Sdes if (irq < 0) 46498937Sdes return irq; 46598937Sdes 46698937Sdes ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, 46798937Sdes 0, dev_name(&pdev->dev), info); 46898937Sdes if (ret < 0) { 46998937Sdes dev_err(&pdev->dev, "failed requesting irq %d\n", irq); 47098937Sdes return ret; 47198937Sdes } 47298937Sdes 47398937Sdes info->vref = devm_regulator_get(&pdev->dev, "vref"); 47498937Sdes if (IS_ERR(info->vref)) 47598937Sdes return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), 47698937Sdes "failed to get regulator\n"); 47798937Sdes 47898937Sdes if (info->reset) 47998937Sdes rockchip_saradc_reset_controller(info->reset); 48098937Sdes 48198937Sdes /* 48298937Sdes * Use a default value for the converter clock. 48398937Sdes * This may become user-configurable in the future. 48498937Sdes */ 48598937Sdes ret = clk_set_rate(info->clk, info->data->clk_rate); 486113908Sdes if (ret < 0) 487113908Sdes return dev_err_probe(&pdev->dev, ret, 488113908Sdes "failed to set adc clk rate\n"); 489113908Sdes 490113908Sdes ret = regulator_enable(info->vref); 491113908Sdes if (ret < 0) 492113908Sdes return dev_err_probe(&pdev->dev, ret, 493113908Sdes "failed to enable vref regulator\n"); 494113908Sdes 495113908Sdes ret = devm_add_action_or_reset(&pdev->dev, 496113908Sdes rockchip_saradc_regulator_disable, info); 497113908Sdes if (ret) 498113908Sdes return dev_err_probe(&pdev->dev, ret, 499113908Sdes "failed to register devm action\n"); 50098937Sdes 50198937Sdes ret = regulator_get_voltage(info->vref); 50298937Sdes if (ret < 0) 50398937Sdes return ret; 50498937Sdes 50598937Sdes info->uv_vref = ret; 50698937Sdes 50798937Sdes info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); 50898937Sdes if (IS_ERR(info->pclk)) 50998937Sdes return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), 51098937Sdes "failed to get pclk\n"); 51198937Sdes 51298937Sdes info->clk = devm_clk_get_enabled(&pdev->dev, "saradc"); 51398937Sdes if (IS_ERR(info->clk)) 514149749Sdes return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), 515149749Sdes "failed to get adc clock\n"); 516149749Sdes 517149749Sdes platform_set_drvdata(pdev, indio_dev); 518157016Sdes 519157016Sdes indio_dev->name = dev_name(&pdev->dev); 520157016Sdes indio_dev->info = &rockchip_saradc_iio_info; 521157016Sdes indio_dev->modes = INDIO_DIRECT_MODE; 522181111Sdes 523181111Sdes indio_dev->channels = info->data->channels; 524181111Sdes indio_dev->num_channels = info->data->num_channels; 525181111Sdes ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL, 52698937Sdes rockchip_saradc_trigger_handler, 52798937Sdes NULL); 52898937Sdes if (ret) 52998937Sdes return ret; 53098937Sdes 53198937Sdes info->nb.notifier_call = rockchip_saradc_volt_notify; 53298937Sdes ret = regulator_register_notifier(info->vref, &info->nb); 53398937Sdes if (ret) 53498937Sdes return ret; 53598937Sdes 53698937Sdes ret = devm_add_action_or_reset(&pdev->dev, 53798937Sdes rockchip_saradc_regulator_unreg_notifier, 53898937Sdes info); 53998937Sdes if (ret) 54098937Sdes return ret; 54198937Sdes 54298937Sdes mutex_init(&info->lock); 543124208Sdes 544124208Sdes return devm_iio_device_register(&pdev->dev, indio_dev); 545124208Sdes} 546124208Sdes 547124208Sdesstatic int rockchip_saradc_suspend(struct device *dev) 548124208Sdes{ 549124208Sdes struct iio_dev *indio_dev = dev_get_drvdata(dev); 550124208Sdes struct rockchip_saradc *info = iio_priv(indio_dev); 551124208Sdes 552124208Sdes clk_disable_unprepare(info->clk); 553124208Sdes clk_disable_unprepare(info->pclk); 554124208Sdes regulator_disable(info->vref); 555124208Sdes 556124208Sdes return 0; 557124208Sdes} 558124208Sdes 559181111Sdesstatic int rockchip_saradc_resume(struct device *dev) 560137015Sdes{ 561137015Sdes struct iio_dev *indio_dev = dev_get_drvdata(dev); 562124208Sdes struct rockchip_saradc *info = iio_priv(indio_dev); 563162852Sdes int ret; 564162852Sdes 565162852Sdes ret = regulator_enable(info->vref); 566162852Sdes if (ret) 567162852Sdes return ret; 568162852Sdes 569162852Sdes ret = clk_prepare_enable(info->pclk); 570162852Sdes if (ret) 571162852Sdes return ret; 572162852Sdes 573162852Sdes ret = clk_prepare_enable(info->clk); 574162852Sdes if (ret) 575162852Sdes clk_disable_unprepare(info->pclk); 576162852Sdes 577162852Sdes return ret; 578162852Sdes} 57998937Sdes 58098937Sdesstatic DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops, 58198937Sdes rockchip_saradc_suspend, 58298937Sdes rockchip_saradc_resume); 58398937Sdes 58498937Sdesstatic struct platform_driver rockchip_saradc_driver = { 58598937Sdes .probe = rockchip_saradc_probe, 58699060Sdes .driver = { 58799060Sdes .name = "rockchip-saradc", 58899060Sdes .of_match_table = rockchip_saradc_match, 58999060Sdes .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops), 59099060Sdes }, 59199060Sdes}; 59299060Sdes 59399060Sdesmodule_platform_driver(rockchip_saradc_driver); 59499060Sdes 59599060SdesMODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 59699060SdesMODULE_DESCRIPTION("Rockchip SARADC driver"); 59799060SdesMODULE_LICENSE("GPL v2"); 59898937Sdes