1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2021 Aspeed Technology Inc. 4 * 5 * PWM/TACH controller driver for Aspeed ast2600 SoCs. 6 * This drivers doesn't support earlier version of the IP. 7 * 8 * The hardware operates in time quantities of length 9 * Q := (DIV_L + 1) << DIV_H / input-clk 10 * The length of a PWM period is (DUTY_CYCLE_PERIOD + 1) * Q. 11 * The maximal value for DUTY_CYCLE_PERIOD is used here to provide 12 * a fine grained selection for the duty cycle. 13 * 14 * This driver uses DUTY_CYCLE_RISING_POINT = 0, so from the start of a 15 * period the output is active until DUTY_CYCLE_FALLING_POINT * Q. Note 16 * that if DUTY_CYCLE_RISING_POINT = DUTY_CYCLE_FALLING_POINT the output is 17 * always active. 18 * 19 * Register usage: 20 * PIN_ENABLE: When it is unset the pwm controller will emit inactive level to the external. 21 * Use to determine whether the PWM channel is enabled or disabled 22 * CLK_ENABLE: When it is unset the pwm controller will assert the duty counter reset and 23 * emit inactive level to the PIN_ENABLE mux after that the driver can still change the pwm period 24 * and duty and the value will apply when CLK_ENABLE be set again. 25 * Use to determine whether duty_cycle bigger than 0. 26 * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately. 27 * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two 28 * values are equal it means the duty cycle = 100%. 29 * 30 * The glitch may generate at: 31 * - Enabled changing when the duty_cycle bigger than 0% and less than 100%. 32 * - Polarity changing when the duty_cycle bigger than 0% and less than 100%. 33 * 34 * Limitations: 35 * - When changing both duty cycle and period, we cannot prevent in 36 * software that the output might produce a period with mixed 37 * settings. 38 * - Disabling the PWM doesn't complete the current period. 39 * 40 * Improvements: 41 * - When only changing one of duty cycle or period, our pwm controller will not 42 * generate the glitch, the configure will change at next cycle of pwm. 43 * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. 44 */ 45 46#include <linux/bitfield.h> 47#include <linux/clk.h> 48#include <linux/delay.h> 49#include <linux/errno.h> 50#include <linux/hwmon.h> 51#include <linux/io.h> 52#include <linux/kernel.h> 53#include <linux/math64.h> 54#include <linux/module.h> 55#include <linux/of_device.h> 56#include <linux/of_platform.h> 57#include <linux/platform_device.h> 58#include <linux/pwm.h> 59#include <linux/reset.h> 60#include <linux/sysfs.h> 61 62/* The channel number of Aspeed pwm controller */ 63#define PWM_ASPEED_NR_PWMS 16 64/* PWM Control Register */ 65#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00) 66#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19) 67#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18) 68#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17) 69#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16) 70#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15) 71#define PWM_ASPEED_CTRL_INVERSE BIT(14) 72#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13) 73#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12) 74#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8) 75#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0) 76 77/* PWM Duty Cycle Register */ 78#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04) 79#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24) 80#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16) 81#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8) 82#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0) 83 84/* PWM fixed value */ 85#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD) 86 87/* The channel number of Aspeed tach controller */ 88#define TACH_ASPEED_NR_TACHS 16 89/* TACH Control Register */ 90#define TACH_ASPEED_CTRL(ch) (((ch) * 0x10) + 0x08) 91#define TACH_ASPEED_IER BIT(31) 92#define TACH_ASPEED_INVERS_LIMIT BIT(30) 93#define TACH_ASPEED_LOOPBACK BIT(29) 94#define TACH_ASPEED_ENABLE BIT(28) 95#define TACH_ASPEED_DEBOUNCE_MASK GENMASK(27, 26) 96#define TACH_ASPEED_DEBOUNCE_BIT 26 97#define TACH_ASPEED_IO_EDGE_MASK GENMASK(25, 24) 98#define TACH_ASPEED_IO_EDGE_BIT 24 99#define TACH_ASPEED_CLK_DIV_T_MASK GENMASK(23, 20) 100#define TACH_ASPEED_CLK_DIV_BIT 20 101#define TACH_ASPEED_THRESHOLD_MASK GENMASK(19, 0) 102/* [27:26] */ 103#define DEBOUNCE_3_CLK 0x00 104#define DEBOUNCE_2_CLK 0x01 105#define DEBOUNCE_1_CLK 0x02 106#define DEBOUNCE_0_CLK 0x03 107/* [25:24] */ 108#define F2F_EDGES 0x00 109#define R2R_EDGES 0x01 110#define BOTH_EDGES 0x02 111/* [23:20] */ 112/* divisor = 4 to the nth power, n = register value */ 113#define DEFAULT_TACH_DIV 1024 114#define DIV_TO_REG(divisor) (ilog2(divisor) >> 1) 115 116/* TACH Status Register */ 117#define TACH_ASPEED_STS(ch) (((ch) * 0x10) + 0x0C) 118 119/*PWM_TACH_STS */ 120#define TACH_ASPEED_ISR BIT(31) 121#define TACH_ASPEED_PWM_OUT BIT(25) 122#define TACH_ASPEED_PWM_OEN BIT(24) 123#define TACH_ASPEED_DEB_INPUT BIT(23) 124#define TACH_ASPEED_RAW_INPUT BIT(22) 125#define TACH_ASPEED_VALUE_UPDATE BIT(21) 126#define TACH_ASPEED_FULL_MEASUREMENT BIT(20) 127#define TACH_ASPEED_VALUE_MASK GENMASK(19, 0) 128/********************************************************** 129 * Software setting 130 *********************************************************/ 131#define DEFAULT_FAN_PULSE_PR 2 132 133struct aspeed_pwm_tach_data { 134 struct device *dev; 135 void __iomem *base; 136 struct clk *clk; 137 struct reset_control *reset; 138 unsigned long clk_rate; 139 struct pwm_chip chip; 140 bool tach_present[TACH_ASPEED_NR_TACHS]; 141 u32 tach_divisor; 142}; 143 144static inline struct aspeed_pwm_tach_data * 145aspeed_pwm_chip_to_data(struct pwm_chip *chip) 146{ 147 return container_of(chip, struct aspeed_pwm_tach_data, chip); 148} 149 150static int aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 151 struct pwm_state *state) 152{ 153 struct aspeed_pwm_tach_data *priv = aspeed_pwm_chip_to_data(chip); 154 u32 hwpwm = pwm->hwpwm; 155 bool polarity, pin_en, clk_en; 156 u32 duty_pt, val; 157 u64 div_h, div_l, duty_cycle_period, dividend; 158 159 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm)); 160 polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val); 161 pin_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val); 162 clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val); 163 div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val); 164 div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); 165 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); 166 duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val); 167 duty_cycle_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val); 168 /* 169 * This multiplication doesn't overflow, the upper bound is 170 * 1000000000 * 256 * 256 << 15 = 0x1dcd650000000000 171 */ 172 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * (duty_cycle_period + 1) 173 << div_h; 174 state->period = DIV_ROUND_UP_ULL(dividend, priv->clk_rate); 175 176 if (clk_en && duty_pt) { 177 dividend = (u64)NSEC_PER_SEC * (div_l + 1) * duty_pt 178 << div_h; 179 state->duty_cycle = DIV_ROUND_UP_ULL(dividend, priv->clk_rate); 180 } else { 181 state->duty_cycle = clk_en ? state->period : 0; 182 } 183 state->polarity = polarity ? PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; 184 state->enabled = pin_en; 185 return 0; 186} 187 188static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 189 const struct pwm_state *state) 190{ 191 struct aspeed_pwm_tach_data *priv = aspeed_pwm_chip_to_data(chip); 192 u32 hwpwm = pwm->hwpwm, duty_pt, val; 193 u64 div_h, div_l, divisor, expect_period; 194 bool clk_en; 195 196 expect_period = div64_u64(ULLONG_MAX, (u64)priv->clk_rate); 197 expect_period = min(expect_period, state->period); 198 dev_dbg(chip->dev, "expect period: %lldns, duty_cycle: %lldns", 199 expect_period, state->duty_cycle); 200 /* 201 * Pick the smallest value for div_h so that div_l can be the biggest 202 * which results in a finer resolution near the target period value. 203 */ 204 divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * 205 (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1); 206 div_h = order_base_2(DIV64_U64_ROUND_UP(priv->clk_rate * expect_period, divisor)); 207 if (div_h > 0xf) 208 div_h = 0xf; 209 210 divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h; 211 div_l = div64_u64(priv->clk_rate * expect_period, divisor); 212 213 if (div_l == 0) 214 return -ERANGE; 215 216 div_l -= 1; 217 218 if (div_l > 255) 219 div_l = 255; 220 221 dev_dbg(chip->dev, "clk source: %ld div_h %lld, div_l : %lld\n", 222 priv->clk_rate, div_h, div_l); 223 /* duty_pt = duty_cycle * (PERIOD + 1) / period */ 224 duty_pt = div64_u64(state->duty_cycle * priv->clk_rate, 225 (u64)NSEC_PER_SEC * (div_l + 1) << div_h); 226 dev_dbg(chip->dev, "duty_cycle = %lld, duty_pt = %d\n", 227 state->duty_cycle, duty_pt); 228 229 /* 230 * Fixed DUTY_CYCLE_PERIOD to its max value to get a 231 * fine-grained resolution for duty_cycle at the expense of a 232 * coarser period resolution. 233 */ 234 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); 235 val &= ~PWM_ASPEED_DUTY_CYCLE_PERIOD; 236 val |= FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, 237 PWM_ASPEED_FIXED_PERIOD); 238 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); 239 240 if (duty_pt == 0) { 241 /* emit inactive level and assert the duty counter reset */ 242 clk_en = 0; 243 } else { 244 clk_en = 1; 245 if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1)) 246 duty_pt = 0; 247 val = readl(priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); 248 val &= ~(PWM_ASPEED_DUTY_CYCLE_RISING_POINT | 249 PWM_ASPEED_DUTY_CYCLE_FALLING_POINT); 250 val |= FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, duty_pt); 251 writel(val, priv->base + PWM_ASPEED_DUTY_CYCLE(hwpwm)); 252 } 253 254 val = readl(priv->base + PWM_ASPEED_CTRL(hwpwm)); 255 val &= ~(PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L | 256 PWM_ASPEED_CTRL_PIN_ENABLE | PWM_ASPEED_CTRL_CLK_ENABLE | 257 PWM_ASPEED_CTRL_INVERSE); 258 val |= FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | 259 FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) | 260 FIELD_PREP(PWM_ASPEED_CTRL_PIN_ENABLE, state->enabled) | 261 FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en) | 262 FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, state->polarity); 263 writel(val, priv->base + PWM_ASPEED_CTRL(hwpwm)); 264 265 return 0; 266} 267 268static const struct pwm_ops aspeed_pwm_ops = { 269 .apply = aspeed_pwm_apply, 270 .get_state = aspeed_pwm_get_state, 271}; 272 273static void aspeed_tach_ch_enable(struct aspeed_pwm_tach_data *priv, u8 tach_ch, 274 bool enable) 275{ 276 if (enable) 277 writel(readl(priv->base + TACH_ASPEED_CTRL(tach_ch)) | 278 TACH_ASPEED_ENABLE, 279 priv->base + TACH_ASPEED_CTRL(tach_ch)); 280 else 281 writel(readl(priv->base + TACH_ASPEED_CTRL(tach_ch)) & 282 ~TACH_ASPEED_ENABLE, 283 priv->base + TACH_ASPEED_CTRL(tach_ch)); 284} 285 286static int aspeed_tach_val_to_rpm(struct aspeed_pwm_tach_data *priv, u32 tach_val) 287{ 288 u64 rpm; 289 u32 tach_div; 290 291 tach_div = tach_val * priv->tach_divisor * DEFAULT_FAN_PULSE_PR; 292 293 dev_dbg(priv->dev, "clk %ld, tach_val %d , tach_div %d\n", 294 priv->clk_rate, tach_val, tach_div); 295 296 rpm = (u64)priv->clk_rate * 60; 297 do_div(rpm, tach_div); 298 299 return (int)rpm; 300} 301 302static int aspeed_get_fan_tach_ch_rpm(struct aspeed_pwm_tach_data *priv, 303 u8 fan_tach_ch) 304{ 305 u32 val; 306 307 val = readl(priv->base + TACH_ASPEED_STS(fan_tach_ch)); 308 309 if (!(val & TACH_ASPEED_FULL_MEASUREMENT)) 310 return 0; 311 val = FIELD_GET(TACH_ASPEED_VALUE_MASK, val); 312 return aspeed_tach_val_to_rpm(priv, val); 313} 314 315static int aspeed_tach_hwmon_read(struct device *dev, 316 enum hwmon_sensor_types type, u32 attr, 317 int channel, long *val) 318{ 319 struct aspeed_pwm_tach_data *priv = dev_get_drvdata(dev); 320 u32 reg_val; 321 322 switch (attr) { 323 case hwmon_fan_input: 324 *val = aspeed_get_fan_tach_ch_rpm(priv, channel); 325 break; 326 case hwmon_fan_div: 327 reg_val = readl(priv->base + TACH_ASPEED_CTRL(channel)); 328 reg_val = FIELD_GET(TACH_ASPEED_CLK_DIV_T_MASK, reg_val); 329 *val = BIT(reg_val << 1); 330 break; 331 default: 332 return -EOPNOTSUPP; 333 } 334 return 0; 335} 336 337static int aspeed_tach_hwmon_write(struct device *dev, 338 enum hwmon_sensor_types type, u32 attr, 339 int channel, long val) 340{ 341 struct aspeed_pwm_tach_data *priv = dev_get_drvdata(dev); 342 u32 reg_val; 343 344 switch (attr) { 345 case hwmon_fan_div: 346 if (!is_power_of_2(val) || (ilog2(val) % 2) || 347 DIV_TO_REG(val) > 0xb) 348 return -EINVAL; 349 priv->tach_divisor = val; 350 reg_val = readl(priv->base + TACH_ASPEED_CTRL(channel)); 351 reg_val &= ~TACH_ASPEED_CLK_DIV_T_MASK; 352 reg_val |= FIELD_PREP(TACH_ASPEED_CLK_DIV_T_MASK, 353 DIV_TO_REG(priv->tach_divisor)); 354 writel(reg_val, priv->base + TACH_ASPEED_CTRL(channel)); 355 break; 356 default: 357 return -EOPNOTSUPP; 358 } 359 360 return 0; 361} 362 363static umode_t aspeed_tach_dev_is_visible(const void *drvdata, 364 enum hwmon_sensor_types type, 365 u32 attr, int channel) 366{ 367 const struct aspeed_pwm_tach_data *priv = drvdata; 368 369 if (!priv->tach_present[channel]) 370 return 0; 371 switch (attr) { 372 case hwmon_fan_input: 373 return 0444; 374 case hwmon_fan_div: 375 return 0644; 376 } 377 return 0; 378} 379 380static const struct hwmon_ops aspeed_tach_ops = { 381 .is_visible = aspeed_tach_dev_is_visible, 382 .read = aspeed_tach_hwmon_read, 383 .write = aspeed_tach_hwmon_write, 384}; 385 386static const struct hwmon_channel_info *aspeed_tach_info[] = { 387 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 388 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 389 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 390 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 391 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 392 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 393 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV, 394 HWMON_F_INPUT | HWMON_F_DIV, HWMON_F_INPUT | HWMON_F_DIV), 395 NULL 396}; 397 398static const struct hwmon_chip_info aspeed_tach_chip_info = { 399 .ops = &aspeed_tach_ops, 400 .info = aspeed_tach_info, 401}; 402 403static void aspeed_present_fan_tach(struct aspeed_pwm_tach_data *priv, u8 *tach_ch, int count) 404{ 405 u8 ch, index; 406 u32 val; 407 408 for (index = 0; index < count; index++) { 409 ch = tach_ch[index]; 410 priv->tach_present[ch] = true; 411 priv->tach_divisor = DEFAULT_TACH_DIV; 412 413 val = readl(priv->base + TACH_ASPEED_CTRL(ch)); 414 val &= ~(TACH_ASPEED_INVERS_LIMIT | TACH_ASPEED_DEBOUNCE_MASK | 415 TACH_ASPEED_IO_EDGE_MASK | TACH_ASPEED_CLK_DIV_T_MASK | 416 TACH_ASPEED_THRESHOLD_MASK); 417 val |= (DEBOUNCE_3_CLK << TACH_ASPEED_DEBOUNCE_BIT) | 418 F2F_EDGES | 419 FIELD_PREP(TACH_ASPEED_CLK_DIV_T_MASK, 420 DIV_TO_REG(priv->tach_divisor)); 421 writel(val, priv->base + TACH_ASPEED_CTRL(ch)); 422 423 aspeed_tach_ch_enable(priv, ch, true); 424 } 425} 426 427static int aspeed_create_fan_monitor(struct device *dev, 428 struct device_node *child, 429 struct aspeed_pwm_tach_data *priv) 430{ 431 int ret, count; 432 u8 *tach_ch; 433 434 count = of_property_count_u8_elems(child, "tach-ch"); 435 if (count < 1) 436 return -EINVAL; 437 tach_ch = devm_kcalloc(dev, count, sizeof(*tach_ch), GFP_KERNEL); 438 if (!tach_ch) 439 return -ENOMEM; 440 ret = of_property_read_u8_array(child, "tach-ch", tach_ch, count); 441 if (ret) 442 return ret; 443 444 aspeed_present_fan_tach(priv, tach_ch, count); 445 446 return 0; 447} 448 449static void aspeed_pwm_tach_reset_assert(void *data) 450{ 451 struct reset_control *rst = data; 452 453 reset_control_assert(rst); 454} 455 456static int aspeed_pwm_tach_probe(struct platform_device *pdev) 457{ 458 struct device *dev = &pdev->dev, *hwmon; 459 int ret; 460 struct device_node *child; 461 struct aspeed_pwm_tach_data *priv; 462 463 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 464 if (!priv) 465 return -ENOMEM; 466 priv->dev = dev; 467 priv->base = devm_platform_ioremap_resource(pdev, 0); 468 if (IS_ERR(priv->base)) 469 return PTR_ERR(priv->base); 470 471 priv->clk = devm_clk_get_enabled(dev, NULL); 472 if (IS_ERR(priv->clk)) 473 return dev_err_probe(dev, PTR_ERR(priv->clk), 474 "Couldn't get clock\n"); 475 priv->clk_rate = clk_get_rate(priv->clk); 476 priv->reset = devm_reset_control_get_exclusive(dev, NULL); 477 if (IS_ERR(priv->reset)) 478 return dev_err_probe(dev, PTR_ERR(priv->reset), 479 "Couldn't get reset control\n"); 480 481 ret = reset_control_deassert(priv->reset); 482 if (ret) 483 return dev_err_probe(dev, ret, 484 "Couldn't deassert reset control\n"); 485 ret = devm_add_action_or_reset(dev, aspeed_pwm_tach_reset_assert, 486 priv->reset); 487 if (ret) 488 return ret; 489 490 priv->chip.dev = dev; 491 priv->chip.ops = &aspeed_pwm_ops; 492 priv->chip.npwm = PWM_ASPEED_NR_PWMS; 493 494 ret = devm_pwmchip_add(dev, &priv->chip); 495 if (ret) 496 return dev_err_probe(dev, ret, "Failed to add PWM chip\n"); 497 498 for_each_child_of_node(dev->of_node, child) { 499 ret = aspeed_create_fan_monitor(dev, child, priv); 500 if (ret) { 501 of_node_put(child); 502 dev_warn(dev, "Failed to create fan %d", ret); 503 return 0; 504 } 505 } 506 507 hwmon = devm_hwmon_device_register_with_info(dev, "aspeed_tach", priv, 508 &aspeed_tach_chip_info, NULL); 509 ret = PTR_ERR_OR_ZERO(hwmon); 510 if (ret) 511 return dev_err_probe(dev, ret, 512 "Failed to register hwmon device\n"); 513 514 of_platform_populate(dev->of_node, NULL, NULL, dev); 515 516 return 0; 517} 518 519static int aspeed_pwm_tach_remove(struct platform_device *pdev) 520{ 521 struct aspeed_pwm_tach_data *priv = platform_get_drvdata(pdev); 522 523 reset_control_assert(priv->reset); 524 525 return 0; 526} 527 528static const struct of_device_id aspeed_pwm_tach_match[] = { 529 { 530 .compatible = "aspeed,ast2600-pwm-tach", 531 }, 532 {}, 533}; 534MODULE_DEVICE_TABLE(of, aspeed_pwm_tach_match); 535 536static struct platform_driver aspeed_pwm_tach_driver = { 537 .probe = aspeed_pwm_tach_probe, 538 .remove = aspeed_pwm_tach_remove, 539 .driver = { 540 .name = "aspeed-g6-pwm-tach", 541 .of_match_table = aspeed_pwm_tach_match, 542 }, 543}; 544 545module_platform_driver(aspeed_pwm_tach_driver); 546 547MODULE_AUTHOR("Billy Tsai <billy_tsai@aspeedtech.com>"); 548MODULE_DESCRIPTION("Aspeed ast2600 PWM and Fan Tach device driver"); 549MODULE_LICENSE("GPL"); 550