Lines Matching refs:clk_rate
138 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n",
282 u64 clk_rate;
292 clk_rate = 0;
296 clk_rate = max(dpu_cstate->new_perf.core_clk_rate,
297 clk_rate);
301 return clk_rate;
309 u64 clk_rate = 0;
380 clk_rate = _dpu_core_perf_get_core_clk_rate(kms);
382 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate);
384 trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate);
386 clk_rate = min(clk_rate, kms->perf.max_core_clk_rate);
387 ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate);
389 DPU_ERROR("failed to set core clock rate %llu\n", clk_rate);
393 kms->perf.core_clk_rate = clk_rate;
394 DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate);