| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 137 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
138 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
140 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 184 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
186 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
188 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
192 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
193 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
197 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
199 * dppclk_khz > 0.
207 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
209 clk_mgr->dccg, dpp_inst, dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
120 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
124 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
126 clk_mgr->dccg, dpp_inst, dppclk_khz);
187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
188 new_clocks->dppclk_khz = 100000;
194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
195 new_clocks->dppclk_khz
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 202 if (new_clocks->dppclk_khz < 100000)
203 new_clocks->dppclk_khz = 100000;
207 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
208 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
210 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
227 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
231 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 42 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
45 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
94 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
122 * 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz
184 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 300 if (new_clocks->dppclk_khz) {
302 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
303 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
317 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
319 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
321 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
325 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
326 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
330 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz >
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 213 if (new_clocks->dppclk_khz < 100000)
214 new_clocks->dppclk_khz = 100000;
216 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
217 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
219 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
236 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
240 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 286 if (new_clocks->dppclk_khz < 100000)
287 new_clocks->dppclk_khz = 100000;
289 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
290 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
292 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
309 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
313 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 285 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
286 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
289 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
290 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
440 else if (a->dppclk_khz != b->dppclk_khz)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 187 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
188 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
192 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
193 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
195 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
215 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
219 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 154 if (new_clocks->dppclk_khz < 100000)
155 new_clocks->dppclk_khz = 100000;
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
160 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
174 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
178 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_utils.c | 295 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
349 context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;
350 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)
351 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;
375 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_debug.c | 354 context->bw_ctx.bw.dcn.clk.dppclk_khz,
362 context->bw_ctx.bw.dcn.clk.dppclk_khz,
|
| /linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_trace.h | 495 __field(int, dppclk_khz)
514 __entry->dppclk_khz = clk->dppclk_khz;
531 TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
538 __entry->dppclk_khz,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 304 int dppclk_khz; member in struct:dcn_fe_bandwidth
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 556 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
564 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 517 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
521 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
1550 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
1552 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
2780 * context->bw_ctx.bw.dcn.clk.dispclk_khz / dppclk_khz. current
2809 context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2821 pipe_ctx->plane_res.bw.dppclk_khz);
2823 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
3924 current_clocks->dppclk_khz
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer_debug.c | 479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 1669 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1719 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1720 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1722 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1724 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1764 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1773 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1169 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1195 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1196 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1197 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1213 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1420 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc.h | 543 int dppclk_khz; member in struct:dc_clocks
581 int bw_dppclk_khz; /*a copy of dppclk_khz*/
|
| /linux-master/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 1607 uint32_t dppclk_khz; /**< dppclk kHz */ member in struct:dmub_clocks
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 1592 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1683 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
|