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04e1ef8a |
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02-Feb-2024 |
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> |
drm/amd/display: Simplify the calculation of variables ./drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c:236:49-51: WARNING !A || A && B is equivalent to !A || B. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=8169 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9ade4870 |
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14-Dec-2023 |
Gabe Teeger <gabe.teeger@amd.com> |
drm/amd/display: Fix Mismatch between pipe and stream [Why] Failing mode validation during dc_commit, leading to blackscreen with an 8k DP2 display during mode change. [What] Fix mixmatch between pipe and stream, which prevented us from recognizing the link as DP2. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5a82b8d6 |
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30-Nov-2023 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Fix lightup regression with DP2 single display configs [WHY] Previous fix for multiple displays downstream of DP2 MST hub caused regression [HOW] Match sink IDs instead of sink struct addresses Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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09a4ec5d |
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17-Nov-2023 |
Dillon Varone <dillon.varone@amd.com> |
drm/amd/display: Refactor dc_state interface [WHY?] Part of the dc_state interface that deals with adding streams and planes should remain public, while others that deal with internal status' and subvp should be private to DC. [HOW?] Move and rename the public functions to dc_state.h and private functions to dc_state_priv.h. Also add some additional functions for extracting subvp meta data from the state. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2170fb03 |
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06-Dec-2023 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Revert DP2 MST hub triple display fix [WHY] Introduces regression with DP2 native displays [HOW] Revert the change Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2cbed167 |
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01-Dec-2023 |
Johnson Chen <johnson.chen@amd.com> |
drm/amd/display: Fix null pointer Add guard for NULL pointer access Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Johnson Chen <johnson.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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fa745b55 |
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01-Dec-2023 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Only enumerate top local sink as DP2 output [WHY] Many DCN generations only have two HPO link encoders and therefore only support driving a max of two DP2 PHYs. DP2 MST hubs currently can not pass 3x display validation as each downstream sink is enumerated as separate DP2 output. [HOW] Count MST hubs once by treating only 1st remote sink in topology as an encoder. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1290183d |
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02-Nov-2023 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: always use mpc factor of 2 for stereo timings [why] In the new pipe resource management logic, the special handling for stereo timings is missing. This commit implements the same stereo timings handling as old pipe resource management code. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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35c1d966 |
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11-Oct-2023 |
Sung Joon Kim <sungkim@amd.com> |
drm/amd/display: Fix handling duplicate planes on one stream [why] DML2 does not handle the case when we have a single stream sourcing 2 or more planes that are duplicates of one another. To properly handle this scenario, pipe index to plane index mapping is used to decide which plane is being processed and programmed. [how] Create static array of pipe index to plane index map. Populate the array properly and use in appropriate places. Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d30a584c |
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19-Oct-2023 |
Stylon Wang <stylon.wang@amd.com> |
drm/amd/display: Fix copyright notice in DML2 code [Why & How] Fix incomplete copyright notice in DML2 code. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9158920c |
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16-Aug-2023 |
Taimur Hassan <syed.hassan@amd.com> |
drm/amd/display: Move stereo timing check to helper Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1d93c4db |
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09-Aug-2023 |
Sung Joon Kim <sungkim@amd.com> |
drm/amd/display: Use fixed DET Buffer Size [why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e47d7ca7 |
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09-Aug-2023 |
Sung Joon Kim <sungkim@amd.com> |
drm/amd/display: Handle multiple streams sourcing same surface [why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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eb918cbb |
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31-Jul-2023 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: Add z8_marks in dml Add z8 watermarks to struct for later ASIC use. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7966f319 |
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28-Jul-2023 |
Qingqing Zhuo <Qingqing.Zhuo@amd.com> |
drm/amd/display: Introduce DML2 DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Co-developed-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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