1/* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 28#include "dccg.h" 29#include "clk_mgr_internal.h" 30 31// For dce12_get_dp_ref_freq_khz 32#include "dce100/dce_clk_mgr.h" 33// For dcn20_update_clocks_update_dpp_dto 34#include "dcn20/dcn20_clk_mgr.h" 35#include "dcn31/dcn31_clk_mgr.h" 36#include "dcn316_clk_mgr.h" 37#include "reg_helper.h" 38#include "core_types.h" 39#include "dcn316_smu.h" 40#include "dm_helpers.h" 41#include "dc_dmub_srv.h" 42#include "link.h" 43 44// DCN316 this is CLK1 instance 45#define MAX_INSTANCE 7 46#define MAX_SEGMENT 6 47 48struct IP_BASE_INSTANCE { 49 unsigned int segment[MAX_SEGMENT]; 50}; 51 52struct IP_BASE { 53 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 54}; 55 56#define regCLK1_CLK_PLL_REQ 0x0237 57#define regCLK1_CLK_PLL_REQ_BASE_IDX 0 58 59#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 60#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 61#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 62#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 63#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 64#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 65 66#define TO_CLK_MGR_DCN316(clk_mgr)\ 67 container_of(clk_mgr, struct clk_mgr_dcn316, base) 68 69static int dcn316_get_active_display_cnt_wa( 70 struct dc *dc, 71 struct dc_state *context) 72{ 73 int i, display_count; 74 bool tmds_present = false; 75 76 display_count = 0; 77 for (i = 0; i < context->stream_count; i++) { 78 const struct dc_stream_state *stream = context->streams[i]; 79 80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 83 tmds_present = true; 84 } 85 86 for (i = 0; i < dc->link_count; i++) { 87 const struct dc_link *link = dc->links[i]; 88 89 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 90 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && 91 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 92 display_count++; 93 } 94 95 /* WA for hang on HDMI after display off back back on*/ 96 if (display_count == 0 && tmds_present) 97 display_count = 1; 98 99 return display_count; 100} 101 102static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, 103 bool safe_to_lower, bool disable) 104{ 105 struct dc *dc = clk_mgr_base->ctx->dc; 106 int i; 107 108 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 109 struct pipe_ctx *pipe = safe_to_lower 110 ? &context->res_ctx.pipe_ctx[i] 111 : &dc->current_state->res_ctx.pipe_ctx[i]; 112 113 if (pipe->top_pipe || pipe->prev_odm_pipe) 114 continue; 115 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || 116 !pipe->stream->link_enc)) { 117 if (disable) { 118 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) 119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 120 121 reset_sync_context_for_pipe(dc, context, i); 122 } else 123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 124 } 125 } 126} 127 128static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) 129{ 130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 131 132 dcn316_smu_enable_pme_wa(clk_mgr); 133} 134 135static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 136 struct dc_state *context, 137 bool safe_to_lower) 138{ 139 union dmub_rb_cmd cmd; 140 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 141 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 142 struct dc *dc = clk_mgr_base->ctx->dc; 143 int display_count; 144 bool update_dppclk = false; 145 bool update_dispclk = false; 146 bool dpp_clock_lowered = false; 147 148 if (dc->work_arounds.skip_clock_update) 149 return; 150 151 /* 152 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 153 * also if safe to lower is false, we just go in the higher state 154 */ 155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 156 if (safe_to_lower) { 157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 158 dcn316_smu_set_dtbclk(clk_mgr, false); 159 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 160 } 161 /* check that we're not already in lower */ 162 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 163 display_count = dcn316_get_active_display_cnt_wa(dc, context); 164 /* if we can go lower, go lower */ 165 if (display_count == 0) { 166 union display_idle_optimization_u idle_info = { 0 }; 167 idle_info.idle_info.df_request_disabled = 1; 168 idle_info.idle_info.phy_ref_clk_off = 1; 169 idle_info.idle_info.s0i2_rdy = 1; 170 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 171 /* update power state */ 172 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 173 } 174 } 175 } else { 176 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 177 dcn316_smu_set_dtbclk(clk_mgr, true); 178 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 179 } 180 181 /* check that we're not already in D0 */ 182 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 183 union display_idle_optimization_u idle_info = { 0 }; 184 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 185 /* update power state */ 186 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 187 } 188 } 189 190 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 191 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 192 dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 193 } 194 195 if (should_set_clock(safe_to_lower, 196 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 197 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 198 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 199 } 200 201 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 202 if (new_clocks->dppclk_khz < 100000) 203 new_clocks->dppclk_khz = 100000; 204 if (new_clocks->dispclk_khz < 100000) 205 new_clocks->dispclk_khz = 100000; 206 207 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 208 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 209 dpp_clock_lowered = true; 210 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 211 update_dppclk = true; 212 } 213 214 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 215 dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); 216 217 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 218 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 219 dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); 220 221 update_dispclk = true; 222 } 223 224 if (dpp_clock_lowered) { 225 // increase per DPP DTO before lowering global dppclk 226 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 227 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 228 } else { 229 // increase global DPPCLK before lowering per DPP DTO 230 if (update_dppclk || update_dispclk) 231 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 232 // always update dtos unless clock is lowered and not safe to lower 233 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 234 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 235 } 236 237 // notify DMCUB of latest clocks 238 memset(&cmd, 0, sizeof(cmd)); 239 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; 240 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; 241 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; 242 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = 243 clk_mgr_base->clks.dcfclk_deep_sleep_khz; 244 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; 245 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; 246 247 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 248} 249 250static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 251 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 252{ 253 return; 254} 255 256static struct clk_bw_params dcn316_bw_params = { 257 .vram_type = Ddr4MemType, 258 .num_channels = 1, 259 .clk_table = { 260 .num_entries = 5, 261 }, 262 263}; 264 265static struct wm_table ddr4_wm_table = { 266 .entries = { 267 { 268 .wm_inst = WM_A, 269 .wm_type = WM_TYPE_PSTATE_CHG, 270 .pstate_latency_us = 11.72, 271 .sr_exit_time_us = 6.09, 272 .sr_enter_plus_exit_time_us = 7.14, 273 .valid = true, 274 }, 275 { 276 .wm_inst = WM_B, 277 .wm_type = WM_TYPE_PSTATE_CHG, 278 .pstate_latency_us = 11.72, 279 .sr_exit_time_us = 10.12, 280 .sr_enter_plus_exit_time_us = 11.48, 281 .valid = true, 282 }, 283 { 284 .wm_inst = WM_C, 285 .wm_type = WM_TYPE_PSTATE_CHG, 286 .pstate_latency_us = 11.72, 287 .sr_exit_time_us = 10.12, 288 .sr_enter_plus_exit_time_us = 11.48, 289 .valid = true, 290 }, 291 { 292 .wm_inst = WM_D, 293 .wm_type = WM_TYPE_PSTATE_CHG, 294 .pstate_latency_us = 11.72, 295 .sr_exit_time_us = 10.12, 296 .sr_enter_plus_exit_time_us = 11.48, 297 .valid = true, 298 }, 299 } 300}; 301 302static struct wm_table lpddr5_wm_table = { 303 .entries = { 304 { 305 .wm_inst = WM_A, 306 .wm_type = WM_TYPE_PSTATE_CHG, 307 .pstate_latency_us = 11.65333, 308 .sr_exit_time_us = 11.5, 309 .sr_enter_plus_exit_time_us = 14.5, 310 .valid = true, 311 }, 312 { 313 .wm_inst = WM_B, 314 .wm_type = WM_TYPE_PSTATE_CHG, 315 .pstate_latency_us = 11.65333, 316 .sr_exit_time_us = 11.5, 317 .sr_enter_plus_exit_time_us = 14.5, 318 .valid = true, 319 }, 320 { 321 .wm_inst = WM_C, 322 .wm_type = WM_TYPE_PSTATE_CHG, 323 .pstate_latency_us = 11.65333, 324 .sr_exit_time_us = 11.5, 325 .sr_enter_plus_exit_time_us = 14.5, 326 .valid = true, 327 }, 328 { 329 .wm_inst = WM_D, 330 .wm_type = WM_TYPE_PSTATE_CHG, 331 .pstate_latency_us = 11.65333, 332 .sr_exit_time_us = 11.5, 333 .sr_enter_plus_exit_time_us = 14.5, 334 .valid = true, 335 }, 336 } 337}; 338 339static DpmClocks_316_t dummy_clocks; 340 341static struct dcn316_watermarks dummy_wms = { 0 }; 342 343static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) 344{ 345 int i, num_valid_sets; 346 347 num_valid_sets = 0; 348 349 for (i = 0; i < WM_SET_COUNT; i++) { 350 /* skip empty entries, the smu array has no holes*/ 351 if (!bw_params->wm_table.entries[i].valid) 352 continue; 353 354 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 355 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 356 /* We will not select WM based on fclk, so leave it as unconstrained */ 357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 359 360 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 361 if (i == 0) 362 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 363 else { 364 /* add 1 to make it non-overlapping with next lvl */ 365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 367 } 368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 369 bw_params->clk_table.entries[i].dcfclk_mhz; 370 371 } else { 372 /* unconstrained for memory retraining */ 373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 375 376 /* Modify previous watermark range to cover up to max */ 377 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 378 } 379 num_valid_sets++; 380 } 381 382 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 383 384 /* modify the min and max to make sure we cover the whole range*/ 385 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 386 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 387 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 388 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 389 390 /* This is for writeback only, does not matter currently as no writeback support*/ 391 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 392 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 393 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 394 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 395 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 396} 397 398static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 399{ 400 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 401 struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr); 402 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; 403 404 if (!clk_mgr->smu_ver) 405 return; 406 407 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) 408 return; 409 410 memset(table, 0, sizeof(*table)); 411 412 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table); 413 414 dcn316_smu_set_dram_addr_high(clk_mgr, 415 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); 416 dcn316_smu_set_dram_addr_low(clk_mgr, 417 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); 418 dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr); 419} 420 421static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 422 struct dcn316_smu_dpm_clks *smu_dpm_clks) 423{ 424 DpmClocks_316_t *table = smu_dpm_clks->dpm_clks; 425 426 if (!clk_mgr->smu_ver) 427 return; 428 429 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 430 return; 431 432 memset(table, 0, sizeof(*table)); 433 434 dcn316_smu_set_dram_addr_high(clk_mgr, 435 smu_dpm_clks->mc_address.high_part); 436 dcn316_smu_set_dram_addr_low(clk_mgr, 437 smu_dpm_clks->mc_address.low_part); 438 dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 439} 440 441static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) 442{ 443 uint32_t max = 0; 444 int i; 445 446 for (i = 0; i < num_clocks; ++i) { 447 if (clocks[i] > max) 448 max = clocks[i]; 449 } 450 451 return max; 452} 453 454static unsigned int find_clk_for_voltage( 455 const DpmClocks_316_t *clock_table, 456 const uint32_t clocks[], 457 unsigned int voltage) 458{ 459 int i; 460 int max_voltage = 0; 461 int clock = 0; 462 463 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { 464 if (clock_table->SocVoltage[i] == voltage) { 465 return clocks[i]; 466 } else if (clock_table->SocVoltage[i] >= max_voltage && 467 clock_table->SocVoltage[i] < voltage) { 468 max_voltage = clock_table->SocVoltage[i]; 469 clock = clocks[i]; 470 } 471 } 472 473 ASSERT(clock); 474 return clock; 475} 476 477static void dcn316_clk_mgr_helper_populate_bw_params( 478 struct clk_mgr_internal *clk_mgr, 479 struct integrated_info *bios_info, 480 const DpmClocks_316_t *clock_table) 481{ 482 int i, j; 483 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 484 uint32_t max_dispclk = 0, max_dppclk = 0; 485 486 j = -1; 487 488 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); 489 490 /* Find lowest DPM, FCLK is filled in reverse order*/ 491 492 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) { 493 if (clock_table->DfPstateTable[i].FClk != 0) { 494 j = i; 495 break; 496 } 497 } 498 499 if (j == -1) { 500 /* clock table is all 0s, just use our own hardcode */ 501 ASSERT(0); 502 return; 503 } 504 505 bw_params->clk_table.num_entries = j + 1; 506 507 /* dispclk and dppclk can be max at any voltage, same number of levels for both */ 508 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && 509 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { 510 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); 511 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); 512 } else { 513 ASSERT(0); 514 } 515 516 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 517 int temp; 518 519 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; 520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; 521 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; 522 switch (clock_table->DfPstateTable[j].WckRatio) { 523 case WCK_RATIO_1_2: 524 bw_params->clk_table.entries[i].wck_ratio = 2; 525 break; 526 case WCK_RATIO_1_4: 527 bw_params->clk_table.entries[i].wck_ratio = 4; 528 break; 529 default: 530 bw_params->clk_table.entries[i].wck_ratio = 1; 531 } 532 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); 533 if (temp) 534 bw_params->clk_table.entries[i].dcfclk_mhz = temp; 535 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); 536 if (temp) 537 bw_params->clk_table.entries[i].socclk_mhz = temp; 538 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 539 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 540 } 541 542 bw_params->vram_type = bios_info->memory_type; 543 bw_params->num_channels = bios_info->ma_channel_number; 544 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; 545 546 for (i = 0; i < WM_SET_COUNT; i++) { 547 bw_params->wm_table.entries[i].wm_inst = i; 548 549 if (i >= bw_params->clk_table.num_entries) { 550 bw_params->wm_table.entries[i].valid = false; 551 continue; 552 } 553 554 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 555 bw_params->wm_table.entries[i].valid = true; 556 } 557} 558 559 560 561static struct clk_mgr_funcs dcn316_funcs = { 562 .enable_pme_wa = dcn316_enable_pme_wa, 563 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 564 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 565 .update_clocks = dcn316_update_clocks, 566 .init_clocks = dcn31_init_clocks, 567 .are_clock_states_equal = dcn31_are_clock_states_equal, 568 .notify_wm_ranges = dcn316_notify_wm_ranges 569}; 570extern struct clk_mgr_funcs dcn3_fpga_funcs; 571 572void dcn316_clk_mgr_construct( 573 struct dc_context *ctx, 574 struct clk_mgr_dcn316 *clk_mgr, 575 struct pp_smu_funcs *pp_smu, 576 struct dccg *dccg) 577{ 578 struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 }; 579 struct clk_log_info log_info = {0}; 580 581 clk_mgr->base.base.ctx = ctx; 582 clk_mgr->base.base.funcs = &dcn316_funcs; 583 584 clk_mgr->base.pp_smu = pp_smu; 585 586 clk_mgr->base.dccg = dccg; 587 clk_mgr->base.dfs_bypass_disp_clk = 0; 588 589 clk_mgr->base.dprefclk_ss_percentage = 0; 590 clk_mgr->base.dprefclk_ss_divider = 1000; 591 clk_mgr->base.ss_on_dprefclk = false; 592 clk_mgr->base.dfs_ref_freq_khz = 48000; 593 594 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( 595 clk_mgr->base.base.ctx, 596 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 597 sizeof(struct dcn316_watermarks), 598 &clk_mgr->smu_wm_set.mc_address.quad_part); 599 600 if (!clk_mgr->smu_wm_set.wm_set) { 601 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 602 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 603 } 604 ASSERT(clk_mgr->smu_wm_set.wm_set); 605 606 smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem( 607 clk_mgr->base.base.ctx, 608 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 609 sizeof(DpmClocks_316_t), 610 &smu_dpm_clks.mc_address.quad_part); 611 612 if (smu_dpm_clks.dpm_clks == NULL) { 613 smu_dpm_clks.dpm_clks = &dummy_clocks; 614 smu_dpm_clks.mc_address.quad_part = 0; 615 } 616 617 ASSERT(smu_dpm_clks.dpm_clks); 618 619 clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base); 620 621 if (clk_mgr->base.smu_ver > 0) 622 clk_mgr->base.smu_present = true; 623 624 // Skip this for now as it did not work on DCN315, renable during bring up 625 //clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 626 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; 627 628 /* in case we don't get a value from the register, use default */ 629 if (clk_mgr->base.base.dentist_vco_freq_khz == 0) 630 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */ 631 632 633 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 634 dcn316_bw_params.wm_table = lpddr5_wm_table; 635 } else { 636 dcn316_bw_params.wm_table = ddr4_wm_table; 637 } 638 /* Saved clocks configured at boot for debug purposes */ 639 dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 640 &clk_mgr->base.base, &log_info); 641 642 clk_mgr->base.base.dprefclk_khz = 600000; 643 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); 644 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 645 dce_clock_read_ss_info(&clk_mgr->base); 646 /*clk_mgr->base.dccg->ref_dtbclk_khz = 647 dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/ 648 649 clk_mgr->base.base.bw_params = &dcn316_bw_params; 650 651 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { 652 dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 653 654 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 655 dcn316_clk_mgr_helper_populate_bw_params( 656 &clk_mgr->base, 657 ctx->dc_bios->integrated_info, 658 smu_dpm_clks.dpm_clks); 659 } 660 } 661 662 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 663 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 664 smu_dpm_clks.dpm_clks); 665} 666 667void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 668{ 669 struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int); 670 671 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 672 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 673 clk_mgr->smu_wm_set.wm_set); 674} 675