1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef _CORE_TYPES_H_ 27#define _CORE_TYPES_H_ 28 29#include "dc.h" 30#include "dce_calcs.h" 31#include "dcn_calcs.h" 32#include "ddc_service_types.h" 33#include "dc_bios_types.h" 34#include "mem_input.h" 35#include "hubp.h" 36#include "mpc.h" 37#include "dwb.h" 38#include "mcif_wb.h" 39#include "panel_cntl.h" 40#include "dmub/inc/dmub_cmd.h" 41#include "pg_cntl.h" 42 43#define MAX_CLOCK_SOURCES 7 44#define MAX_SVP_PHANTOM_STREAMS 2 45#define MAX_SVP_PHANTOM_PLANES 2 46 47void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 48 uint32_t controller_id); 49 50#include "grph_object_id.h" 51#include "link_encoder.h" 52#include "stream_encoder.h" 53#include "clock_source.h" 54#include "audio.h" 55#include "dm_pp_smu.h" 56#include "dm_cp_psp.h" 57#include "link_hwss.h" 58 59/********** DAL Core*********************/ 60#include "transform.h" 61#include "dpp.h" 62 63struct resource_pool; 64struct dc_state; 65struct resource_context; 66struct clk_bw_params; 67 68struct resource_funcs { 69 enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 70 void (*destroy)(struct resource_pool **pool); 71 void (*link_init)(struct dc_link *link); 72 struct panel_cntl*(*panel_cntl_create)( 73 const struct panel_cntl_init_data *panel_cntl_init_data); 74 struct link_encoder *(*link_enc_create)( 75 struct dc_context *ctx, 76 const struct encoder_init_data *init); 77 /* Create a minimal link encoder object with no dc_link object 78 * associated with it. */ 79 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 80 81 bool (*validate_bandwidth)( 82 struct dc *dc, 83 struct dc_state *context, 84 bool fast_validate); 85 void (*calculate_wm_and_dlg)( 86 struct dc *dc, struct dc_state *context, 87 display_e2e_pipe_params_st *pipes, 88 int pipe_cnt, 89 int vlevel); 90 void (*update_soc_for_wm_a)( 91 struct dc *dc, struct dc_state *context); 92 93 /** 94 * @populate_dml_pipes - Populate pipe data struct 95 * 96 * Returns: 97 * Total of pipes available in the specific ASIC. 98 */ 99 int (*populate_dml_pipes)( 100 struct dc *dc, 101 struct dc_state *context, 102 display_e2e_pipe_params_st *pipes, 103 bool fast_validate); 104 105 /* 106 * Algorithm for assigning available link encoders to links. 107 * 108 * Update link_enc_assignments table and link_enc_avail list accordingly in 109 * struct resource_context. 110 */ 111 void (*link_encs_assign)( 112 struct dc *dc, 113 struct dc_state *state, 114 struct dc_stream_state *streams[], 115 uint8_t stream_count); 116 /* 117 * Unassign a link encoder from a stream. 118 * 119 * Update link_enc_assignments table and link_enc_avail list accordingly in 120 * struct resource_context. 121 */ 122 void (*link_enc_unassign)( 123 struct dc_state *state, 124 struct dc_stream_state *stream); 125 126 enum dc_status (*validate_global)( 127 struct dc *dc, 128 struct dc_state *context); 129 130 struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 131 const struct dc_state *cur_ctx, 132 struct dc_state *new_ctx, 133 const struct resource_pool *pool, 134 const struct pipe_ctx *opp_head_pipe); 135 136 struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( 137 const struct dc_state *cur_ctx, 138 struct dc_state *new_ctx, 139 const struct resource_pool *pool, 140 const struct pipe_ctx *otg_master); 141 142 void (*release_pipe)(struct dc_state *context, 143 struct pipe_ctx *pipe, 144 const struct resource_pool *pool); 145 146 enum dc_status (*validate_plane)( 147 const struct dc_plane_state *plane_state, 148 struct dc_caps *caps); 149 150 enum dc_status (*add_stream_to_ctx)( 151 struct dc *dc, 152 struct dc_state *new_ctx, 153 struct dc_stream_state *dc_stream); 154 155 enum dc_status (*remove_stream_from_ctx)( 156 struct dc *dc, 157 struct dc_state *new_ctx, 158 struct dc_stream_state *stream); 159 enum dc_status (*patch_unknown_plane_state)( 160 struct dc_plane_state *plane_state); 161 162 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 163 struct resource_context *res_ctx, 164 const struct resource_pool *pool, 165 struct dc_stream_state *stream); 166 void (*populate_dml_writeback_from_context)( 167 struct dc *dc, 168 struct resource_context *res_ctx, 169 display_e2e_pipe_params_st *pipes); 170 171 void (*set_mcif_arb_params)( 172 struct dc *dc, 173 struct dc_state *context, 174 display_e2e_pipe_params_st *pipes, 175 int pipe_cnt); 176 void (*update_bw_bounding_box)( 177 struct dc *dc, 178 struct clk_bw_params *bw_params); 179 bool (*acquire_post_bldn_3dlut)( 180 struct resource_context *res_ctx, 181 const struct resource_pool *pool, 182 int mpcc_id, 183 struct dc_3dlut **lut, 184 struct dc_transfer_func **shaper); 185 186 bool (*release_post_bldn_3dlut)( 187 struct resource_context *res_ctx, 188 const struct resource_pool *pool, 189 struct dc_3dlut **lut, 190 struct dc_transfer_func **shaper); 191 192 enum dc_status (*add_dsc_to_stream_resource)( 193 struct dc *dc, struct dc_state *state, 194 struct dc_stream_state *stream); 195 196 void (*add_phantom_pipes)( 197 struct dc *dc, 198 struct dc_state *context, 199 display_e2e_pipe_params_st *pipes, 200 unsigned int pipe_cnt, 201 unsigned int index); 202 203 void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 204 void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); 205}; 206 207struct audio_support{ 208 bool dp_audio; 209 bool hdmi_audio_on_dongle; 210 bool hdmi_audio_native; 211}; 212 213#define NO_UNDERLAY_PIPE -1 214 215struct resource_pool { 216 struct mem_input *mis[MAX_PIPES]; 217 struct hubp *hubps[MAX_PIPES]; 218 struct input_pixel_processor *ipps[MAX_PIPES]; 219 struct transform *transforms[MAX_PIPES]; 220 struct dpp *dpps[MAX_PIPES]; 221 struct output_pixel_processor *opps[MAX_PIPES]; 222 struct timing_generator *timing_generators[MAX_PIPES]; 223 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 224 struct hubbub *hubbub; 225 struct mpc *mpc; 226 struct pp_smu_funcs *pp_smu; 227 struct dce_aux *engines[MAX_PIPES]; 228 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 229 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 230 bool i2c_hw_buffer_in_use; 231 232 struct dwbc *dwbc[MAX_DWB_PIPES]; 233 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 234 struct { 235 unsigned int gsl_0:1; 236 unsigned int gsl_1:1; 237 unsigned int gsl_2:1; 238 } gsl_groups; 239 240 struct display_stream_compressor *dscs[MAX_PIPES]; 241 242 unsigned int pipe_count; 243 unsigned int underlay_pipe_index; 244 unsigned int stream_enc_count; 245 246 /* An array for accessing the link encoder objects that have been created. 247 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 248 */ 249 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 250 /* Number of DIG link encoder objects created - i.e. number of valid 251 * entries in link_encoders array. 252 */ 253 unsigned int dig_link_enc_count; 254 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 255 unsigned int usb4_dpia_count; 256 257 unsigned int hpo_dp_stream_enc_count; 258 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 259 unsigned int hpo_dp_link_enc_count; 260 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 261 struct dc_3dlut *mpc_lut[MAX_PIPES]; 262 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 263 264 struct { 265 unsigned int xtalin_clock_inKhz; 266 unsigned int dccg_ref_clock_inKhz; 267 unsigned int dchub_ref_clock_inKhz; 268 } ref_clocks; 269 unsigned int timing_generator_count; 270 unsigned int mpcc_count; 271 272 unsigned int writeback_pipe_count; 273 /* 274 * reserved clock source for DP 275 */ 276 struct clock_source *dp_clock_source; 277 278 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 279 unsigned int clk_src_count; 280 281 struct audio *audios[MAX_AUDIOS]; 282 unsigned int audio_count; 283 struct audio_support audio_support; 284 285 struct dccg *dccg; 286 struct pg_cntl *pg_cntl; 287 struct irq_service *irqs; 288 289 struct abm *abm; 290 struct dmcu *dmcu; 291 struct dmub_psr *psr; 292 293 struct dmub_replay *replay; 294 295 struct abm *multiple_abms[MAX_PIPES]; 296 297 const struct resource_funcs *funcs; 298 const struct resource_caps *res_cap; 299 300 struct ddc_service *oem_device; 301}; 302 303struct dcn_fe_bandwidth { 304 int dppclk_khz; 305 306}; 307 308/* Parameters needed to call set_disp_pattern_generator */ 309struct test_pattern_params { 310 enum controller_dp_test_pattern test_pattern; 311 enum controller_dp_color_space color_space; 312 enum dc_color_depth color_depth; 313 int width; 314 int height; 315 int offset; 316}; 317 318struct stream_resource { 319 struct output_pixel_processor *opp; 320 struct display_stream_compressor *dsc; 321 struct timing_generator *tg; 322 struct stream_encoder *stream_enc; 323 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 324 struct audio *audio; 325 326 struct pixel_clk_params pix_clk_params; 327 struct encoder_info_frame encoder_info_frame; 328 329 struct abm *abm; 330 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 331 * otherwise it's using group number 'gsl_group-1' 332 */ 333 uint8_t gsl_group; 334 335 struct test_pattern_params test_pattern_params; 336}; 337 338struct plane_resource { 339 struct scaler_data scl_data; 340 struct hubp *hubp; 341 struct mem_input *mi; 342 struct input_pixel_processor *ipp; 343 struct transform *xfm; 344 struct dpp *dpp; 345 uint8_t mpcc_inst; 346 347 struct dcn_fe_bandwidth bw; 348}; 349 350#define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 351#define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 352 353/* all mappable hardware resources used to enable a link */ 354struct link_resource { 355 struct hpo_dp_link_encoder *hpo_dp_link_enc; 356}; 357 358struct link_config { 359 struct dc_link_settings dp_link_settings; 360}; 361union pipe_update_flags { 362 struct { 363 uint32_t enable : 1; 364 uint32_t disable : 1; 365 uint32_t odm : 1; 366 uint32_t global_sync : 1; 367 uint32_t opp_changed : 1; 368 uint32_t tg_changed : 1; 369 uint32_t mpcc : 1; 370 uint32_t dppclk : 1; 371 uint32_t hubp_interdependent : 1; 372 uint32_t hubp_rq_dlg_ttu : 1; 373 uint32_t gamut_remap : 1; 374 uint32_t scaler : 1; 375 uint32_t viewport : 1; 376 uint32_t plane_changed : 1; 377 uint32_t det_size : 1; 378 uint32_t unbounded_req : 1; 379 uint32_t test_pattern_changed : 1; 380 } bits; 381 uint32_t raw; 382}; 383 384enum p_state_switch_method { 385 P_STATE_UNKNOWN = 0, 386 P_STATE_V_BLANK = 1, 387 P_STATE_FPO, 388 P_STATE_V_ACTIVE, 389 P_STATE_SUB_VP, 390 P_STATE_DRR_SUB_VP, 391 P_STATE_V_BLANK_SUB_VP 392}; 393 394struct pipe_ctx { 395 struct dc_plane_state *plane_state; 396 struct dc_stream_state *stream; 397 398 struct plane_resource plane_res; 399 400 /** 401 * @stream_res: Reference to DCN resource components such OPP and DSC. 402 */ 403 struct stream_resource stream_res; 404 struct link_resource link_res; 405 406 struct clock_source *clock_source; 407 408 struct pll_settings pll_settings; 409 410 /** 411 * @link_config: 412 * 413 * link config records software decision for what link config should be 414 * enabled given current link capability and stream during hw resource 415 * mapping. This is to decouple the dependency on link capability during 416 * dc commit or update. 417 */ 418 struct link_config link_config; 419 420 uint8_t pipe_idx; 421 uint8_t pipe_idx_syncd; 422 423 struct pipe_ctx *top_pipe; 424 struct pipe_ctx *bottom_pipe; 425 struct pipe_ctx *next_odm_pipe; 426 struct pipe_ctx *prev_odm_pipe; 427 428 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 429 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 430 struct _vcs_dpi_display_rq_regs_st rq_regs; 431 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 432 struct _vcs_dpi_display_rq_params_st dml_rq_param; 433 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 434 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 435 int det_buffer_size_kb; 436 bool unbounded_req; 437 unsigned int surface_size_in_mall_bytes; 438 439 struct dwbc *dwbc; 440 struct mcif_wb *mcif_wb; 441 union pipe_update_flags update_flags; 442 enum p_state_switch_method p_state_type; 443 struct tg_color visual_confirm_color; 444 bool has_vactive_margin; 445 /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ 446 uint8_t subvp_index; 447}; 448 449/* Data used for dynamic link encoder assignment. 450 * Tracks current and future assignments; available link encoders; 451 * and mode of operation (whether to use current or future assignments). 452 */ 453struct link_enc_cfg_context { 454 enum link_enc_cfg_mode mode; 455 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 456 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 457 struct link_enc_assignment transient_assignments[MAX_PIPES]; 458}; 459 460struct resource_context { 461 struct pipe_ctx pipe_ctx[MAX_PIPES]; 462 bool is_stream_enc_acquired[MAX_PIPES * 2]; 463 bool is_audio_acquired[MAX_PIPES]; 464 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 465 uint8_t dp_clock_source_ref_count; 466 bool is_dsc_acquired[MAX_PIPES]; 467 struct link_enc_cfg_context link_enc_cfg_ctx; 468 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 469 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 470 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 471 bool is_mpc_3dlut_acquired[MAX_PIPES]; 472 /* solely used for build scalar data in dml2 */ 473 struct pipe_ctx temp_pipe; 474}; 475 476struct dce_bw_output { 477 bool cpuc_state_change_enable; 478 bool cpup_state_change_enable; 479 bool stutter_mode_enable; 480 bool nbp_state_change_enable; 481 bool all_displays_in_sync; 482 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 483 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 484 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 485 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 486 int sclk_khz; 487 int sclk_deep_sleep_khz; 488 int yclk_khz; 489 int dispclk_khz; 490 int blackout_recovery_time_us; 491}; 492 493struct dcn_bw_writeback { 494 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 495}; 496 497struct dcn_bw_output { 498 struct dc_clocks clk; 499 struct dcn_watermark_set watermarks; 500 struct dcn_bw_writeback bw_writeback; 501 int compbuf_size_kb; 502 unsigned int mall_ss_size_bytes; 503 unsigned int mall_ss_psr_active_size_bytes; 504 unsigned int mall_subvp_size_bytes; 505 unsigned int legacy_svp_drr_stream_index; 506 bool legacy_svp_drr_stream_index_valid; 507}; 508 509union bw_output { 510 struct dcn_bw_output dcn; 511 struct dce_bw_output dce; 512}; 513 514struct bw_context { 515 union bw_output bw; 516 struct display_mode_lib dml; 517 struct dml2_context *dml2; 518}; 519 520struct dc_dmub_cmd { 521 union dmub_rb_cmd dmub_cmd; 522 enum dm_dmub_wait_type wait_type; 523}; 524 525struct dc_scratch_space { 526 /* used to temporarily backup plane states of a stream during 527 * dc update. The reason is that plane states are overwritten 528 * with surface updates in dc update. Once they are overwritten 529 * current state is no longer valid. We want to temporarily 530 * store current value in plane states so we can still recover 531 * a valid current state during dc update. 532 */ 533 struct dc_plane_state plane_states[MAX_SURFACE_NUM]; 534 struct dc_gamma gamma_correction[MAX_SURFACE_NUM]; 535 struct dc_transfer_func in_transfer_func[MAX_SURFACE_NUM]; 536 struct dc_3dlut lut3d_func[MAX_SURFACE_NUM]; 537 struct dc_transfer_func in_shaper_func[MAX_SURFACE_NUM]; 538 struct dc_transfer_func blend_tf[MAX_SURFACE_NUM]; 539 540 struct dc_stream_state stream_state; 541 struct dc_transfer_func out_transfer_func; 542}; 543 544/** 545 * struct dc_state - The full description of a state requested by users 546 */ 547struct dc_state { 548 /** 549 * @streams: Stream state properties 550 */ 551 struct dc_stream_state *streams[MAX_PIPES]; 552 553 /** 554 * @stream_status: Planes status on a given stream 555 */ 556 struct dc_stream_status stream_status[MAX_PIPES]; 557 /** 558 * @phantom_streams: Stream state properties for phantoms 559 */ 560 struct dc_stream_state *phantom_streams[MAX_PHANTOM_PIPES]; 561 /** 562 * @phantom_planes: Planes state properties for phantoms 563 */ 564 struct dc_plane_state *phantom_planes[MAX_PHANTOM_PIPES]; 565 566 /** 567 * @stream_count: Total of streams in use 568 */ 569 uint8_t stream_count; 570 uint8_t stream_mask; 571 572 /** 573 * @stream_count: Total phantom streams in use 574 */ 575 uint8_t phantom_stream_count; 576 /** 577 * @stream_count: Total phantom planes in use 578 */ 579 uint8_t phantom_plane_count; 580 /** 581 * @res_ctx: Persistent state of resources 582 */ 583 struct resource_context res_ctx; 584 585 /** 586 * @pp_display_cfg: PowerPlay clocks and settings 587 * Note: this is a big struct, do *not* put on stack! 588 */ 589 struct dm_pp_display_configuration pp_display_cfg; 590 591 /** 592 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 593 * Note: this is a big struct, do *not* put on stack! 594 */ 595 struct dcn_bw_internal_vars dcn_bw_vars; 596 597 struct clk_mgr *clk_mgr; 598 599 /** 600 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 601 * 602 * Each context must have its own instance of VBA, and in order to 603 * initialize and obtain IP and SOC, the base DML instance from DC is 604 * initially copied into every context. 605 */ 606 struct bw_context bw_ctx; 607 608 struct block_sequence block_sequence[50]; 609 unsigned int block_sequence_steps; 610 struct dc_dmub_cmd dc_dmub_cmd[10]; 611 unsigned int dmub_cmd_count; 612 613 /** 614 * @refcount: refcount reference 615 * 616 * Notice that dc_state is used around the code to capture the current 617 * context, so we need to pass it everywhere. That's why we want to use 618 * kref in this struct. 619 */ 620 struct kref refcount; 621 622 struct { 623 unsigned int stutter_period_us; 624 } perf_params; 625 626 627 struct dc_scratch_space scratch; 628}; 629 630struct replay_context { 631 /* ddc line */ 632 enum channel_id aux_inst; 633 /* Transmitter id */ 634 enum transmitter digbe_inst; 635 /* Engine Id is used for Dig Be source select */ 636 enum engine_id digfe_inst; 637 /* Controller Id used for Dig Fe source select */ 638 enum controller_id controllerId; 639 unsigned int line_time_in_ns; 640}; 641 642enum dc_replay_enable { 643 DC_REPLAY_DISABLE = 0, 644 DC_REPLAY_ENABLE = 1, 645}; 646 647struct dc_bounding_box_max_clk { 648 int max_dcfclk_mhz; 649 int max_dispclk_mhz; 650 int max_dppclk_mhz; 651 int max_phyclk_mhz; 652}; 653 654#endif /* _CORE_TYPES_H_ */ 655