1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26#ifndef DMUB_CMD_H 27#define DMUB_CMD_H 28 29#include <asm/byteorder.h> 30#include <linux/types.h> 31#include <linux/string.h> 32#include <linux/delay.h> 33 34#include "atomfirmware.h" 35 36//<DMUB_TYPES>================================================================== 37/* Basic type definitions. */ 38 39#define __forceinline inline 40 41/** 42 * Flag from driver to indicate that ABM should be disabled gradually 43 * by slowly reversing all backlight programming and pixel compensation. 44 */ 45#define SET_ABM_PIPE_GRADUALLY_DISABLE 0 46 47/** 48 * Flag from driver to indicate that ABM should be disabled immediately 49 * and undo all backlight programming and pixel compensation. 50 */ 51#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 52 53/** 54 * Flag from driver to indicate that ABM should be disabled immediately 55 * and keep the current backlight programming and pixel compensation. 56 */ 57#define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 58 59/** 60 * Flag from driver to set the current ABM pipe index or ABM operating level. 61 */ 62#define SET_ABM_PIPE_NORMAL 1 63 64/** 65 * Number of ambient light levels in ABM algorithm. 66 */ 67#define NUM_AMBI_LEVEL 5 68 69/** 70 * Number of operating/aggression levels in ABM algorithm. 71 */ 72#define NUM_AGGR_LEVEL 4 73 74/** 75 * Number of segments in the gamma curve. 76 */ 77#define NUM_POWER_FN_SEGS 8 78 79/** 80 * Number of segments in the backlight curve. 81 */ 82#define NUM_BL_CURVE_SEGS 16 83 84/* Maximum number of SubVP streams */ 85#define DMUB_MAX_SUBVP_STREAMS 2 86 87/* Define max FPO streams as 4 for now. Current implementation today 88 * only supports 1, but could be more in the future. Reduce array 89 * size to ensure the command size remains less than 64 bytes if 90 * adding new fields. 91 */ 92#define DMUB_MAX_FPO_STREAMS 4 93 94/* Maximum number of streams on any ASIC. */ 95#define DMUB_MAX_STREAMS 6 96 97/* Maximum number of planes on any ASIC. */ 98#define DMUB_MAX_PLANES 6 99 100/* Trace buffer offset for entry */ 101#define TRACE_BUFFER_ENTRY_OFFSET 16 102 103/** 104 * Maximum number of dirty rects supported by FW. 105 */ 106#define DMUB_MAX_DIRTY_RECTS 3 107 108/** 109 * 110 * PSR control version legacy 111 */ 112#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 113/** 114 * PSR control version with multi edp support 115 */ 116#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 117 118 119/** 120 * ABM control version legacy 121 */ 122#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 123 124/** 125 * ABM control version with multi edp support 126 */ 127#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 128 129/** 130 * Physical framebuffer address location, 64-bit. 131 */ 132#ifndef PHYSICAL_ADDRESS_LOC 133#define PHYSICAL_ADDRESS_LOC union large_integer 134#endif 135 136/** 137 * OS/FW agnostic memcpy 138 */ 139#ifndef dmub_memcpy 140#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 141#endif 142 143/** 144 * OS/FW agnostic memset 145 */ 146#ifndef dmub_memset 147#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 148#endif 149 150#if defined(__cplusplus) 151extern "C" { 152#endif 153 154/** 155 * OS/FW agnostic udelay 156 */ 157#ifndef dmub_udelay 158#define dmub_udelay(microseconds) udelay(microseconds) 159#endif 160 161#pragma pack(push, 1) 162#define ABM_NUM_OF_ACE_SEGMENTS 5 163 164union abm_flags { 165 struct { 166 /** 167 * @abm_enabled: Indicates if ABM is enabled. 168 */ 169 unsigned int abm_enabled : 1; 170 171 /** 172 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 173 */ 174 unsigned int disable_abm_requested : 1; 175 176 /** 177 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 178 */ 179 unsigned int disable_abm_immediately : 1; 180 181 /** 182 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 183 * to be disabled immediately and keep gain. 184 */ 185 unsigned int disable_abm_immediate_keep_gain : 1; 186 187 /** 188 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 189 */ 190 unsigned int fractional_pwm : 1; 191 192 /** 193 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 194 * of user backlight level. 195 */ 196 unsigned int abm_gradual_bl_change : 1; 197 } bitfields; 198 199 unsigned int u32All; 200}; 201 202struct abm_save_restore { 203 /** 204 * @flags: Misc. ABM flags. 205 */ 206 union abm_flags flags; 207 208 /** 209 * @pause: true: pause ABM and get state 210 * false: unpause ABM after setting state 211 */ 212 uint32_t pause; 213 214 /** 215 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 216 */ 217 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 218 219 /** 220 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 221 */ 222 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 223 224 /** 225 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 226 */ 227 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 228 229 230 /** 231 * @knee_threshold: Current x-position of ACE knee (u0.16). 232 */ 233 uint32_t knee_threshold; 234 /** 235 * @current_gain: Current backlight reduction (u16.16). 236 */ 237 uint32_t current_gain; 238 /** 239 * @curr_bl_level: Current actual backlight level converging to target backlight level. 240 */ 241 uint16_t curr_bl_level; 242 243 /** 244 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 245 */ 246 uint16_t curr_user_bl_level; 247 248}; 249 250/** 251 * union dmub_addr - DMUB physical/virtual 64-bit address. 252 */ 253union dmub_addr { 254 struct { 255 uint32_t low_part; /**< Lower 32 bits */ 256 uint32_t high_part; /**< Upper 32 bits */ 257 } u; /*<< Low/high bit access */ 258 uint64_t quad_part; /*<< 64 bit address */ 259}; 260#pragma pack(pop) 261 262/** 263 * Dirty rect definition. 264 */ 265struct dmub_rect { 266 /** 267 * Dirty rect x offset. 268 */ 269 uint32_t x; 270 271 /** 272 * Dirty rect y offset. 273 */ 274 uint32_t y; 275 276 /** 277 * Dirty rect width. 278 */ 279 uint32_t width; 280 281 /** 282 * Dirty rect height. 283 */ 284 uint32_t height; 285}; 286 287/** 288 * Flags that can be set by driver to change some PSR behaviour. 289 */ 290union dmub_psr_debug_flags { 291 /** 292 * Debug flags. 293 */ 294 struct { 295 /** 296 * Enable visual confirm in FW. 297 */ 298 uint32_t visual_confirm : 1; 299 300 /** 301 * Force all selective updates to bw full frame updates. 302 */ 303 uint32_t force_full_frame_update : 1; 304 305 /** 306 * Use HW Lock Mgr object to do HW locking in FW. 307 */ 308 uint32_t use_hw_lock_mgr : 1; 309 310 /** 311 * Use TPS3 signal when restore main link. 312 */ 313 uint32_t force_wakeup_by_tps3 : 1; 314 315 /** 316 * Back to back flip, therefore cannot power down PHY 317 */ 318 uint32_t back_to_back_flip : 1; 319 320 } bitfields; 321 322 /** 323 * Union for debug flags. 324 */ 325 uint32_t u32All; 326}; 327 328/** 329 * Flags that can be set by driver to change some Replay behaviour. 330 */ 331union replay_debug_flags { 332 struct { 333 /** 334 * 0x1 (bit 0) 335 * Enable visual confirm in FW. 336 */ 337 uint32_t visual_confirm : 1; 338 339 /** 340 * 0x2 (bit 1) 341 * @skip_crc: Set if need to skip CRC. 342 */ 343 uint32_t skip_crc : 1; 344 345 /** 346 * 0x4 (bit 2) 347 * @force_link_power_on: Force disable ALPM control 348 */ 349 uint32_t force_link_power_on : 1; 350 351 /** 352 * 0x8 (bit 3) 353 * @force_phy_power_on: Force phy power on 354 */ 355 uint32_t force_phy_power_on : 1; 356 357 /** 358 * 0x10 (bit 4) 359 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 360 */ 361 uint32_t timing_resync_disabled : 1; 362 363 /** 364 * 0x20 (bit 5) 365 * @skip_crtc_disabled: CRTC disable skipped 366 */ 367 uint32_t skip_crtc_disabled : 1; 368 369 /** 370 * 0x40 (bit 6) 371 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 372 */ 373 uint32_t force_defer_one_frame_update : 1; 374 375 /** 376 * 0x80 (bit 7) 377 * @disable_delay_alpm_on: Force disable delay alpm on 378 */ 379 uint32_t disable_delay_alpm_on : 1; 380 381 /** 382 * 0x100 (bit 8) 383 * @disable_desync_error_check: Force disable desync error check 384 */ 385 uint32_t disable_desync_error_check : 1; 386 387 /** 388 * 0x200 (bit 9) 389 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 390 */ 391 uint32_t force_self_update_when_abm_non_steady : 1; 392 393 /** 394 * 0x400 (bit 10) 395 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 396 * If we enter IPS2, the Visual confirm bar will change to yellow 397 */ 398 uint32_t enable_ips_visual_confirm : 1; 399 400 /** 401 * 0x800 (bit 11) 402 * @enable_ips_residency_profiling: Enable IPS residency profiling 403 */ 404 uint32_t enable_ips_residency_profiling : 1; 405 406 uint32_t reserved : 20; 407 } bitfields; 408 409 uint32_t u32All; 410}; 411 412union replay_hw_flags { 413 struct { 414 /** 415 * @allow_alpm_fw_standby_mode: To indicate whether the 416 * ALPM FW standby mode is allowed 417 */ 418 uint32_t allow_alpm_fw_standby_mode : 1; 419 420 /* 421 * @dsc_enable_status: DSC enable status in driver 422 */ 423 uint32_t dsc_enable_status : 1; 424 425 /** 426 * @fec_enable_status: receive fec enable/disable status from driver 427 */ 428 uint32_t fec_enable_status : 1; 429 430 /* 431 * @smu_optimizations_en: SMU power optimization. 432 * Only when active display is Replay capable and display enters Replay. 433 * Trigger interrupt to SMU to powerup/down. 434 */ 435 uint32_t smu_optimizations_en : 1; 436 437 /** 438 * @phy_power_state: Indicates current phy power state 439 */ 440 uint32_t phy_power_state : 1; 441 442 /** 443 * @link_power_state: Indicates current link power state 444 */ 445 uint32_t link_power_state : 1; 446 /** 447 * Use TPS3 signal when restore main link. 448 */ 449 uint32_t force_wakeup_by_tps3 : 1; 450 } bitfields; 451 452 uint32_t u32All; 453}; 454 455/** 456 * DMUB feature capabilities. 457 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 458 */ 459struct dmub_feature_caps { 460 /** 461 * Max PSR version supported by FW. 462 */ 463 uint8_t psr; 464 uint8_t fw_assisted_mclk_switch; 465 uint8_t reserved[4]; 466 uint8_t subvp_psr_support; 467 uint8_t gecc_enable; 468 uint8_t replay_supported; 469 uint8_t replay_reserved[3]; 470}; 471 472struct dmub_visual_confirm_color { 473 /** 474 * Maximum 10 bits color value 475 */ 476 uint16_t color_r_cr; 477 uint16_t color_g_y; 478 uint16_t color_b_cb; 479 uint16_t panel_inst; 480}; 481 482#if defined(__cplusplus) 483} 484#endif 485 486//============================================================================== 487//</DMUB_TYPES>================================================================= 488//============================================================================== 489//< DMUB_META>================================================================== 490//============================================================================== 491#pragma pack(push, 1) 492 493/* Magic value for identifying dmub_fw_meta_info */ 494#define DMUB_FW_META_MAGIC 0x444D5542 495 496/* Offset from the end of the file to the dmub_fw_meta_info */ 497#define DMUB_FW_META_OFFSET 0x24 498 499/** 500 * struct dmub_fw_meta_info - metadata associated with fw binary 501 * 502 * NOTE: This should be considered a stable API. Fields should 503 * not be repurposed or reordered. New fields should be 504 * added instead to extend the structure. 505 * 506 * @magic_value: magic value identifying DMUB firmware meta info 507 * @fw_region_size: size of the firmware state region 508 * @trace_buffer_size: size of the tracebuffer region 509 * @fw_version: the firmware version information 510 * @dal_fw: 1 if the firmware is DAL 511 * @shared_state_size: size of the shared state region in bytes 512 * @shared_state_features: number of shared state features 513 */ 514struct dmub_fw_meta_info { 515 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 516 uint32_t fw_region_size; /**< size of the firmware state region */ 517 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 518 uint32_t fw_version; /**< the firmware version information */ 519 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 520 uint8_t reserved[3]; /**< padding bits */ 521 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 522 uint16_t shared_state_features; /**< number of shared state features */ 523 uint16_t reserved2; /**< padding bytes */ 524}; 525 526/** 527 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 528 */ 529union dmub_fw_meta { 530 struct dmub_fw_meta_info info; /**< metadata info */ 531 uint8_t reserved[64]; /**< padding bits */ 532}; 533 534#pragma pack(pop) 535 536//============================================================================== 537//< DMUB Trace Buffer>================================================================ 538//============================================================================== 539/** 540 * dmub_trace_code_t - firmware trace code, 32-bits 541 */ 542typedef uint32_t dmub_trace_code_t; 543 544/** 545 * struct dmcub_trace_buf_entry - Firmware trace entry 546 */ 547struct dmcub_trace_buf_entry { 548 dmub_trace_code_t trace_code; /**< trace code for the event */ 549 uint32_t tick_count; /**< the tick count at time of trace */ 550 uint32_t param0; /**< trace defined parameter 0 */ 551 uint32_t param1; /**< trace defined parameter 1 */ 552}; 553 554//============================================================================== 555//< DMUB_STATUS>================================================================ 556//============================================================================== 557 558/** 559 * DMCUB scratch registers can be used to determine firmware status. 560 * Current scratch register usage is as follows: 561 * 562 * SCRATCH0: FW Boot Status register 563 * SCRATCH5: LVTMA Status Register 564 * SCRATCH15: FW Boot Options register 565 */ 566 567/** 568 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 569 */ 570union dmub_fw_boot_status { 571 struct { 572 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 573 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 574 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 575 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 576 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 577 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 578 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 579 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 580 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 581 } bits; /**< status bits */ 582 uint32_t all; /**< 32-bit access to status bits */ 583}; 584 585/** 586 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 587 */ 588enum dmub_fw_boot_status_bit { 589 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 590 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 591 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 592 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 593 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 594 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 595 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 596 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 597 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 598}; 599 600/* Register bit definition for SCRATCH5 */ 601union dmub_lvtma_status { 602 struct { 603 uint32_t psp_ok : 1; 604 uint32_t edp_on : 1; 605 uint32_t reserved : 30; 606 } bits; 607 uint32_t all; 608}; 609 610enum dmub_lvtma_status_bit { 611 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 612 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 613}; 614 615enum dmub_ips_disable_type { 616 DMUB_IPS_ENABLE = 0, 617 DMUB_IPS_DISABLE_ALL = 1, 618 DMUB_IPS_DISABLE_IPS1 = 2, 619 DMUB_IPS_DISABLE_IPS2 = 3, 620 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 621 DMUB_IPS_DISABLE_DYNAMIC = 5, 622}; 623 624#define DMUB_IPS1_ALLOW_MASK 0x00000001 625#define DMUB_IPS2_ALLOW_MASK 0x00000002 626#define DMUB_IPS1_COMMIT_MASK 0x00000004 627#define DMUB_IPS2_COMMIT_MASK 0x00000008 628 629/** 630 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 631 */ 632union dmub_fw_boot_options { 633 struct { 634 uint32_t pemu_env : 1; /**< 1 if PEMU */ 635 uint32_t fpga_env : 1; /**< 1 if FPGA */ 636 uint32_t optimized_init : 1; /**< 1 if optimized init */ 637 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 638 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 639 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 640 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 641 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 642 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 643 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 644 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 645 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 646 uint32_t power_optimization: 1; 647 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 648 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 649 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 650 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 651 uint32_t reserved0: 1; 652 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 653 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 654 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 655 uint32_t ips_disable: 3; /* options to disable ips support*/ 656 uint32_t reserved : 9; /**< reserved */ 657 } bits; /**< boot bits */ 658 uint32_t all; /**< 32-bit access to bits */ 659}; 660 661enum dmub_fw_boot_options_bit { 662 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 663 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 664 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 665}; 666 667//============================================================================== 668//< DMUB_SHARED_STATE>========================================================== 669//============================================================================== 670 671/** 672 * Shared firmware state between driver and firmware for lockless communication 673 * in situations where the inbox/outbox may be unavailable. 674 * 675 * Each structure *must* be at most 256-bytes in size. The layout allocation is 676 * described below: 677 * 678 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 679 */ 680 681/** 682 * enum dmub_shared_state_feature_id - List of shared state features. 683 */ 684enum dmub_shared_state_feature_id { 685 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 686 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 687 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 688 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 689}; 690 691/** 692 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 693 */ 694union dmub_shared_state_ips_fw_signals { 695 struct { 696 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 697 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 698 uint32_t reserved_bits : 30; /**< Reversed */ 699 } bits; 700 uint32_t all; 701}; 702 703/** 704 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 705 */ 706union dmub_shared_state_ips_driver_signals { 707 struct { 708 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 709 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 710 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 711 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 712 uint32_t reserved_bits : 28; /**< Reversed bits */ 713 } bits; 714 uint32_t all; 715}; 716 717/** 718 * IPS FW Version 719 */ 720#define DMUB_SHARED_STATE__IPS_FW_VERSION 1 721 722/** 723 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 724 */ 725struct dmub_shared_state_ips_fw { 726 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 727 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 728}; /* 248-bytes, fixed */ 729 730/** 731 * IPS Driver Version 732 */ 733#define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 734 735/** 736 * struct dmub_shared_state_ips_driver - Driver state for IPS. 737 */ 738struct dmub_shared_state_ips_driver { 739 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 740 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 741}; /* 248-bytes, fixed */ 742 743/** 744 * enum dmub_shared_state_feature_common - Generic payload. 745 */ 746struct dmub_shared_state_feature_common { 747 uint32_t padding[62]; 748}; /* 248-bytes, fixed */ 749 750/** 751 * enum dmub_shared_state_feature_header - Feature description. 752 */ 753struct dmub_shared_state_feature_header { 754 uint16_t id; /**< Feature ID */ 755 uint16_t version; /**< Feature version */ 756 uint32_t reserved; /**< Reserved bytes. */ 757}; /* 8 bytes, fixed */ 758 759/** 760 * struct dmub_shared_state_feature_block - Feature block. 761 */ 762struct dmub_shared_state_feature_block { 763 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 764 union dmub_shared_feature_state_union { 765 struct dmub_shared_state_feature_common common; /**< Generic data */ 766 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 767 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 768 } data; /**< Shared state data. */ 769}; /* 256-bytes, fixed */ 770 771/** 772 * Shared state size in bytes. 773 */ 774#define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 775 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 776 777//============================================================================== 778//</DMUB_STATUS>================================================================ 779//============================================================================== 780//< DMUB_VBIOS>================================================================= 781//============================================================================== 782 783/* 784 * enum dmub_cmd_vbios_type - VBIOS commands. 785 * 786 * Command IDs should be treated as stable ABI. 787 * Do not reuse or modify IDs. 788 */ 789enum dmub_cmd_vbios_type { 790 /** 791 * Configures the DIG encoder. 792 */ 793 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 794 /** 795 * Controls the PHY. 796 */ 797 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 798 /** 799 * Sets the pixel clock/symbol clock. 800 */ 801 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 802 /** 803 * Enables or disables power gating. 804 */ 805 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 806 /** 807 * Controls embedded panels. 808 */ 809 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 810 /** 811 * Query DP alt status on a transmitter. 812 */ 813 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 814 /** 815 * Controls domain power gating 816 */ 817 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 818}; 819 820//============================================================================== 821//</DMUB_VBIOS>================================================================= 822//============================================================================== 823//< DMUB_GPINT>================================================================= 824//============================================================================== 825 826/** 827 * The shifts and masks below may alternatively be used to format and read 828 * the command register bits. 829 */ 830 831#define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 832#define DMUB_GPINT_DATA_PARAM_SHIFT 0 833 834#define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 835#define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 836 837#define DMUB_GPINT_DATA_STATUS_MASK 0xF 838#define DMUB_GPINT_DATA_STATUS_SHIFT 28 839 840/** 841 * Command responses. 842 */ 843 844/** 845 * Return response for DMUB_GPINT__STOP_FW command. 846 */ 847#define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 848 849/** 850 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 851 */ 852union dmub_gpint_data_register { 853 struct { 854 uint32_t param : 16; /**< 16-bit parameter */ 855 uint32_t command_code : 12; /**< GPINT command */ 856 uint32_t status : 4; /**< Command status bit */ 857 } bits; /**< GPINT bit access */ 858 uint32_t all; /**< GPINT 32-bit access */ 859}; 860 861/* 862 * enum dmub_gpint_command - GPINT command to DMCUB FW 863 * 864 * Command IDs should be treated as stable ABI. 865 * Do not reuse or modify IDs. 866 */ 867enum dmub_gpint_command { 868 /** 869 * Invalid command, ignored. 870 */ 871 DMUB_GPINT__INVALID_COMMAND = 0, 872 /** 873 * DESC: Queries the firmware version. 874 * RETURN: Firmware version. 875 */ 876 DMUB_GPINT__GET_FW_VERSION = 1, 877 /** 878 * DESC: Halts the firmware. 879 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 880 */ 881 DMUB_GPINT__STOP_FW = 2, 882 /** 883 * DESC: Get PSR state from FW. 884 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 885 */ 886 DMUB_GPINT__GET_PSR_STATE = 7, 887 /** 888 * DESC: Notifies DMCUB of the currently active streams. 889 * ARGS: Stream mask, 1 bit per active stream index. 890 */ 891 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 892 /** 893 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 894 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 895 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 896 * RETURN: PSR residency in milli-percent. 897 */ 898 DMUB_GPINT__PSR_RESIDENCY = 9, 899 900 /** 901 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 902 */ 903 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 904 905 /** 906 * DESC: Get REPLAY state from FW. 907 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 908 */ 909 DMUB_GPINT__GET_REPLAY_STATE = 13, 910 911 /** 912 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 913 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 914 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 915 * RETURN: REPLAY residency in milli-percent. 916 */ 917 DMUB_GPINT__REPLAY_RESIDENCY = 14, 918 919 /** 920 * DESC: Updates the trace buffer lower 32-bit mask. 921 * ARGS: The new mask 922 * RETURN: Lower 32-bit mask. 923 */ 924 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 925 926 /** 927 * DESC: Updates the trace buffer mask bit0~bit15. 928 * ARGS: The new mask 929 * RETURN: Lower 32-bit mask. 930 */ 931 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 932 933 /** 934 * DESC: Updates the trace buffer mask bit16~bit31. 935 * ARGS: The new mask 936 * RETURN: Lower 32-bit mask. 937 */ 938 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 939 940 /** 941 * DESC: Updates the trace buffer mask bit32~bit47. 942 * ARGS: The new mask 943 * RETURN: Lower 32-bit mask. 944 */ 945 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 946 947 /** 948 * DESC: Updates the trace buffer mask bit48~bit63. 949 * ARGS: The new mask 950 * RETURN: Lower 32-bit mask. 951 */ 952 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 953 954 /** 955 * DESC: Read the trace buffer mask bi0~bit15. 956 */ 957 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 958 959 /** 960 * DESC: Read the trace buffer mask bit16~bit31. 961 */ 962 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 963 964 /** 965 * DESC: Read the trace buffer mask bi32~bit47. 966 */ 967 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 968 969 /** 970 * DESC: Updates the trace buffer mask bit32~bit63. 971 */ 972 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 973 974 /** 975 * DESC: Enable measurements for various task duration 976 * ARGS: 0 - Disable measurement 977 * 1 - Enable measurement 978 */ 979 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 980}; 981 982/** 983 * INBOX0 generic command definition 984 */ 985union dmub_inbox0_cmd_common { 986 struct { 987 uint32_t command_code: 8; /**< INBOX0 command code */ 988 uint32_t param: 24; /**< 24-bit parameter */ 989 } bits; 990 uint32_t all; 991}; 992 993/** 994 * INBOX0 hw_lock command definition 995 */ 996union dmub_inbox0_cmd_lock_hw { 997 struct { 998 uint32_t command_code: 8; 999 1000 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1001 uint32_t hw_lock_client: 2; 1002 1003 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1004 uint32_t otg_inst: 3; 1005 uint32_t opp_inst: 3; 1006 uint32_t dig_inst: 3; 1007 1008 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1009 uint32_t lock_pipe: 1; 1010 uint32_t lock_cursor: 1; 1011 uint32_t lock_dig: 1; 1012 uint32_t triple_buffer_lock: 1; 1013 1014 uint32_t lock: 1; /**< Lock */ 1015 uint32_t should_release: 1; /**< Release */ 1016 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1017 } bits; 1018 uint32_t all; 1019}; 1020 1021union dmub_inbox0_data_register { 1022 union dmub_inbox0_cmd_common inbox0_cmd_common; 1023 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1024}; 1025 1026enum dmub_inbox0_command { 1027 /** 1028 * DESC: Invalid command, ignored. 1029 */ 1030 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1031 /** 1032 * DESC: Notification to acquire/release HW lock 1033 * ARGS: 1034 */ 1035 DMUB_INBOX0_CMD__HW_LOCK = 1, 1036}; 1037//============================================================================== 1038//</DMUB_GPINT>================================================================= 1039//============================================================================== 1040//< DMUB_CMD>=================================================================== 1041//============================================================================== 1042 1043/** 1044 * Size in bytes of each DMUB command. 1045 */ 1046#define DMUB_RB_CMD_SIZE 64 1047 1048/** 1049 * Maximum number of items in the DMUB ringbuffer. 1050 */ 1051#define DMUB_RB_MAX_ENTRY 128 1052 1053/** 1054 * Ringbuffer size in bytes. 1055 */ 1056#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1057 1058/** 1059 * REG_SET mask for reg offload. 1060 */ 1061#define REG_SET_MASK 0xFFFF 1062 1063/* 1064 * enum dmub_cmd_type - DMUB inbox command. 1065 * 1066 * Command IDs should be treated as stable ABI. 1067 * Do not reuse or modify IDs. 1068 */ 1069enum dmub_cmd_type { 1070 /** 1071 * Invalid command. 1072 */ 1073 DMUB_CMD__NULL = 0, 1074 /** 1075 * Read modify write register sequence offload. 1076 */ 1077 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1078 /** 1079 * Field update register sequence offload. 1080 */ 1081 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1082 /** 1083 * Burst write sequence offload. 1084 */ 1085 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1086 /** 1087 * Reg wait sequence offload. 1088 */ 1089 DMUB_CMD__REG_REG_WAIT = 4, 1090 /** 1091 * Workaround to avoid HUBP underflow during NV12 playback. 1092 */ 1093 DMUB_CMD__PLAT_54186_WA = 5, 1094 /** 1095 * Command type used to query FW feature caps. 1096 */ 1097 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1098 /** 1099 * Command type used to get visual confirm color. 1100 */ 1101 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1102 /** 1103 * Command type used for all PSR commands. 1104 */ 1105 DMUB_CMD__PSR = 64, 1106 /** 1107 * Command type used for all MALL commands. 1108 */ 1109 DMUB_CMD__MALL = 65, 1110 /** 1111 * Command type used for all ABM commands. 1112 */ 1113 DMUB_CMD__ABM = 66, 1114 /** 1115 * Command type used to update dirty rects in FW. 1116 */ 1117 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1118 /** 1119 * Command type used to update cursor info in FW. 1120 */ 1121 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1122 /** 1123 * Command type used for HW locking in FW. 1124 */ 1125 DMUB_CMD__HW_LOCK = 69, 1126 /** 1127 * Command type used to access DP AUX. 1128 */ 1129 DMUB_CMD__DP_AUX_ACCESS = 70, 1130 /** 1131 * Command type used for OUTBOX1 notification enable 1132 */ 1133 DMUB_CMD__OUTBOX1_ENABLE = 71, 1134 1135 /** 1136 * Command type used for all idle optimization commands. 1137 */ 1138 DMUB_CMD__IDLE_OPT = 72, 1139 /** 1140 * Command type used for all clock manager commands. 1141 */ 1142 DMUB_CMD__CLK_MGR = 73, 1143 /** 1144 * Command type used for all panel control commands. 1145 */ 1146 DMUB_CMD__PANEL_CNTL = 74, 1147 1148 /** 1149 * Command type used for all CAB commands. 1150 */ 1151 DMUB_CMD__CAB_FOR_SS = 75, 1152 1153 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1154 1155 /** 1156 * Command type used for interfacing with DPIA. 1157 */ 1158 DMUB_CMD__DPIA = 77, 1159 /** 1160 * Command type used for EDID CEA parsing 1161 */ 1162 DMUB_CMD__EDID_CEA = 79, 1163 /** 1164 * Command type used for getting usbc cable ID 1165 */ 1166 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1167 /** 1168 * Command type used to query HPD state. 1169 */ 1170 DMUB_CMD__QUERY_HPD_STATE = 82, 1171 /** 1172 * Command type used for all VBIOS interface commands. 1173 */ 1174 /** 1175 * Command type used for all REPLAY commands. 1176 */ 1177 DMUB_CMD__REPLAY = 83, 1178 1179 /** 1180 * Command type used for all SECURE_DISPLAY commands. 1181 */ 1182 DMUB_CMD__SECURE_DISPLAY = 85, 1183 1184 /** 1185 * Command type used to set DPIA HPD interrupt state 1186 */ 1187 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1188 1189 DMUB_CMD__VBIOS = 128, 1190}; 1191 1192/** 1193 * enum dmub_out_cmd_type - DMUB outbox commands. 1194 */ 1195enum dmub_out_cmd_type { 1196 /** 1197 * Invalid outbox command, ignored. 1198 */ 1199 DMUB_OUT_CMD__NULL = 0, 1200 /** 1201 * Command type used for DP AUX Reply data notification 1202 */ 1203 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1204 /** 1205 * Command type used for DP HPD event notification 1206 */ 1207 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1208 /** 1209 * Command type used for SET_CONFIG Reply notification 1210 */ 1211 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1212 /** 1213 * Command type used for USB4 DPIA notification 1214 */ 1215 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1216}; 1217 1218/* DMUB_CMD__DPIA command sub-types. */ 1219enum dmub_cmd_dpia_type { 1220 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1221 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 1222 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1223}; 1224 1225/* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1226enum dmub_cmd_dpia_notification_type { 1227 DPIA_NOTIFY__BW_ALLOCATION = 0, 1228}; 1229 1230#pragma pack(push, 1) 1231 1232/** 1233 * struct dmub_cmd_header - Common command header fields. 1234 */ 1235struct dmub_cmd_header { 1236 unsigned int type : 8; /**< command type */ 1237 unsigned int sub_type : 8; /**< command sub type */ 1238 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1239 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1240 unsigned int reserved0 : 6; /**< reserved bits */ 1241 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1242 unsigned int reserved1 : 2; /**< reserved bits */ 1243}; 1244 1245/* 1246 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1247 * 1248 * 60 payload bytes can hold up to 5 sets of read modify writes, 1249 * each take 3 dwords. 1250 * 1251 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1252 * 1253 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1254 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1255 */ 1256struct dmub_cmd_read_modify_write_sequence { 1257 uint32_t addr; /**< register address */ 1258 uint32_t modify_mask; /**< modify mask */ 1259 uint32_t modify_value; /**< modify value */ 1260}; 1261 1262/** 1263 * Maximum number of ops in read modify write sequence. 1264 */ 1265#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1266 1267/** 1268 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1269 */ 1270struct dmub_rb_cmd_read_modify_write { 1271 struct dmub_cmd_header header; /**< command header */ 1272 /** 1273 * Read modify write sequence. 1274 */ 1275 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1276}; 1277 1278/* 1279 * Update a register with specified masks and values sequeunce 1280 * 1281 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1282 * 1283 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1284 * 1285 * 1286 * USE CASE: 1287 * 1. auto-increment register where additional read would update pointer and produce wrong result 1288 * 2. toggle a bit without read in the middle 1289 */ 1290 1291struct dmub_cmd_reg_field_update_sequence { 1292 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1293 uint32_t modify_value; /**< value to update with */ 1294}; 1295 1296/** 1297 * Maximum number of ops in field update sequence. 1298 */ 1299#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1300 1301/** 1302 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1303 */ 1304struct dmub_rb_cmd_reg_field_update_sequence { 1305 struct dmub_cmd_header header; /**< command header */ 1306 uint32_t addr; /**< register address */ 1307 /** 1308 * Field update sequence. 1309 */ 1310 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1311}; 1312 1313 1314/** 1315 * Maximum number of burst write values. 1316 */ 1317#define DMUB_BURST_WRITE_VALUES__MAX 14 1318 1319/* 1320 * struct dmub_rb_cmd_burst_write - Burst write 1321 * 1322 * support use case such as writing out LUTs. 1323 * 1324 * 60 payload bytes can hold up to 14 values to write to given address 1325 * 1326 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1327 */ 1328struct dmub_rb_cmd_burst_write { 1329 struct dmub_cmd_header header; /**< command header */ 1330 uint32_t addr; /**< register start address */ 1331 /** 1332 * Burst write register values. 1333 */ 1334 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1335}; 1336 1337/** 1338 * struct dmub_rb_cmd_common - Common command header 1339 */ 1340struct dmub_rb_cmd_common { 1341 struct dmub_cmd_header header; /**< command header */ 1342 /** 1343 * Padding to RB_CMD_SIZE 1344 */ 1345 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1346}; 1347 1348/** 1349 * struct dmub_cmd_reg_wait_data - Register wait data 1350 */ 1351struct dmub_cmd_reg_wait_data { 1352 uint32_t addr; /**< Register address */ 1353 uint32_t mask; /**< Mask for register bits */ 1354 uint32_t condition_field_value; /**< Value to wait for */ 1355 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1356}; 1357 1358/** 1359 * struct dmub_rb_cmd_reg_wait - Register wait command 1360 */ 1361struct dmub_rb_cmd_reg_wait { 1362 struct dmub_cmd_header header; /**< Command header */ 1363 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1364}; 1365 1366/** 1367 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1368 * 1369 * Reprograms surface parameters to avoid underflow. 1370 */ 1371struct dmub_cmd_PLAT_54186_wa { 1372 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1373 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1374 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1375 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1376 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1377 struct { 1378 uint32_t hubp_inst : 4; /**< HUBP instance */ 1379 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1380 uint32_t immediate :1; /**< Immediate flip */ 1381 uint32_t vmid : 4; /**< VMID */ 1382 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1383 uint32_t reserved : 21; /**< Reserved */ 1384 } flip_params; /**< Pageflip parameters */ 1385 uint32_t reserved[9]; /**< Reserved bits */ 1386}; 1387 1388/** 1389 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1390 */ 1391struct dmub_rb_cmd_PLAT_54186_wa { 1392 struct dmub_cmd_header header; /**< Command header */ 1393 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1394}; 1395 1396/** 1397 * enum dmub_cmd_mall_type - MALL commands 1398 */ 1399enum dmub_cmd_mall_type { 1400 /** 1401 * Allows display refresh from MALL. 1402 */ 1403 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1404 /** 1405 * Disallows display refresh from MALL. 1406 */ 1407 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1408 /** 1409 * Cursor copy for MALL. 1410 */ 1411 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1412 /** 1413 * Controls DF requests. 1414 */ 1415 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1416}; 1417 1418/** 1419 * struct dmub_rb_cmd_mall - MALL command data. 1420 */ 1421struct dmub_rb_cmd_mall { 1422 struct dmub_cmd_header header; /**< Common command header */ 1423 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1424 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1425 uint32_t tmr_delay; /**< Timer delay */ 1426 uint32_t tmr_scale; /**< Timer scale */ 1427 uint16_t cursor_width; /**< Cursor width in pixels */ 1428 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1429 uint16_t cursor_height; /**< Cursor height in pixels */ 1430 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1431 uint8_t debug_bits; /**< Debug bits */ 1432 1433 uint8_t reserved1; /**< Reserved bits */ 1434 uint8_t reserved2; /**< Reserved bits */ 1435}; 1436 1437/** 1438 * enum dmub_cmd_cab_type - CAB command data. 1439 */ 1440enum dmub_cmd_cab_type { 1441 /** 1442 * No idle optimizations (i.e. no CAB) 1443 */ 1444 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1445 /** 1446 * No DCN requests for memory 1447 */ 1448 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1449 /** 1450 * Fit surfaces in CAB (i.e. CAB enable) 1451 */ 1452 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1453 /** 1454 * Do not fit surfaces in CAB (i.e. no CAB) 1455 */ 1456 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1457}; 1458 1459/** 1460 * struct dmub_rb_cmd_cab - CAB command data. 1461 */ 1462struct dmub_rb_cmd_cab_for_ss { 1463 struct dmub_cmd_header header; 1464 uint8_t cab_alloc_ways; /* total number of ways */ 1465 uint8_t debug_bits; /* debug bits */ 1466}; 1467 1468/** 1469 * Enum for indicating which MCLK switch mode per pipe 1470 */ 1471enum mclk_switch_mode { 1472 NONE = 0, 1473 FPO = 1, 1474 SUBVP = 2, 1475 VBLANK = 3, 1476}; 1477 1478/* Per pipe struct which stores the MCLK switch mode 1479 * data to be sent to DMUB. 1480 * Named "v2" for now -- once FPO and SUBVP are fully merged 1481 * the type name can be updated 1482 */ 1483struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1484 union { 1485 struct { 1486 uint32_t pix_clk_100hz; 1487 uint16_t main_vblank_start; 1488 uint16_t main_vblank_end; 1489 uint16_t mall_region_lines; 1490 uint16_t prefetch_lines; 1491 uint16_t prefetch_to_mall_start_lines; 1492 uint16_t processing_delay_lines; 1493 uint16_t htotal; // required to calculate line time for multi-display cases 1494 uint16_t vtotal; 1495 uint8_t main_pipe_index; 1496 uint8_t phantom_pipe_index; 1497 /* Since the microschedule is calculated in terms of OTG lines, 1498 * include any scaling factors to make sure when we get accurate 1499 * conversion when programming MALL_START_LINE (which is in terms 1500 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1501 * is 1/2 (numerator = 1, denominator = 2). 1502 */ 1503 uint8_t scale_factor_numerator; 1504 uint8_t scale_factor_denominator; 1505 uint8_t is_drr; 1506 uint8_t main_split_pipe_index; 1507 uint8_t phantom_split_pipe_index; 1508 } subvp_data; 1509 1510 struct { 1511 uint32_t pix_clk_100hz; 1512 uint16_t vblank_start; 1513 uint16_t vblank_end; 1514 uint16_t vstartup_start; 1515 uint16_t vtotal; 1516 uint16_t htotal; 1517 uint8_t vblank_pipe_index; 1518 uint8_t padding[1]; 1519 struct { 1520 uint8_t drr_in_use; 1521 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1522 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1523 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1524 uint8_t use_ramping; // Use ramping or not 1525 uint8_t drr_vblank_start_margin; 1526 } drr_info; // DRR considered as part of SubVP + VBLANK case 1527 } vblank_data; 1528 } pipe_config; 1529 1530 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1531 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1532 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1533 */ 1534 uint8_t mode; // enum mclk_switch_mode 1535}; 1536 1537/** 1538 * Config data for Sub-VP and FPO 1539 * Named "v2" for now -- once FPO and SUBVP are fully merged 1540 * the type name can be updated 1541 */ 1542struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1543 uint16_t watermark_a_cache; 1544 uint8_t vertical_int_margin_us; 1545 uint8_t pstate_allow_width_us; 1546 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1547}; 1548 1549/** 1550 * DMUB rb command definition for Sub-VP and FPO 1551 * Named "v2" for now -- once FPO and SUBVP are fully merged 1552 * the type name can be updated 1553 */ 1554struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1555 struct dmub_cmd_header header; 1556 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1557}; 1558 1559/** 1560 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1561 */ 1562enum dmub_cmd_idle_opt_type { 1563 /** 1564 * DCN hardware restore. 1565 */ 1566 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1567 1568 /** 1569 * DCN hardware save. 1570 */ 1571 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 1572 1573 /** 1574 * DCN hardware notify idle. 1575 */ 1576 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 1577}; 1578 1579/** 1580 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1581 */ 1582struct dmub_rb_cmd_idle_opt_dcn_restore { 1583 struct dmub_cmd_header header; /**< header */ 1584}; 1585 1586/** 1587 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1588 */ 1589struct dmub_dcn_notify_idle_cntl_data { 1590 uint8_t driver_idle; 1591 uint8_t pad[1]; 1592}; 1593 1594/** 1595 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 1596 */ 1597struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 1598 struct dmub_cmd_header header; /**< header */ 1599 struct dmub_dcn_notify_idle_cntl_data cntl_data; 1600}; 1601 1602/** 1603 * struct dmub_clocks - Clock update notification. 1604 */ 1605struct dmub_clocks { 1606 uint32_t dispclk_khz; /**< dispclk kHz */ 1607 uint32_t dppclk_khz; /**< dppclk kHz */ 1608 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1609 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1610}; 1611 1612/** 1613 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1614 */ 1615enum dmub_cmd_clk_mgr_type { 1616 /** 1617 * Notify DMCUB of clock update. 1618 */ 1619 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1620}; 1621 1622/** 1623 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1624 */ 1625struct dmub_rb_cmd_clk_mgr_notify_clocks { 1626 struct dmub_cmd_header header; /**< header */ 1627 struct dmub_clocks clocks; /**< clock data */ 1628}; 1629 1630/** 1631 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1632 */ 1633struct dmub_cmd_digx_encoder_control_data { 1634 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1635}; 1636 1637/** 1638 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1639 */ 1640struct dmub_rb_cmd_digx_encoder_control { 1641 struct dmub_cmd_header header; /**< header */ 1642 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1643}; 1644 1645/** 1646 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1647 */ 1648struct dmub_cmd_set_pixel_clock_data { 1649 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1650}; 1651 1652/** 1653 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1654 */ 1655struct dmub_rb_cmd_set_pixel_clock { 1656 struct dmub_cmd_header header; /**< header */ 1657 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1658}; 1659 1660/** 1661 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1662 */ 1663struct dmub_cmd_enable_disp_power_gating_data { 1664 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1665}; 1666 1667/** 1668 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1669 */ 1670struct dmub_rb_cmd_enable_disp_power_gating { 1671 struct dmub_cmd_header header; /**< header */ 1672 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1673}; 1674 1675/** 1676 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1677 */ 1678struct dmub_dig_transmitter_control_data_v1_7 { 1679 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1680 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1681 union { 1682 uint8_t digmode; /**< enum atom_encode_mode_def */ 1683 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1684 } mode_laneset; 1685 uint8_t lanenum; /**< Number of lanes */ 1686 union { 1687 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1688 } symclk_units; 1689 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1690 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1691 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1692 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1693 uint8_t reserved1; /**< For future use */ 1694 uint8_t reserved2[3]; /**< For future use */ 1695 uint32_t reserved3[11]; /**< For future use */ 1696}; 1697 1698/** 1699 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1700 */ 1701union dmub_cmd_dig1_transmitter_control_data { 1702 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1703 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1704}; 1705 1706/** 1707 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1708 */ 1709struct dmub_rb_cmd_dig1_transmitter_control { 1710 struct dmub_cmd_header header; /**< header */ 1711 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1712}; 1713 1714/** 1715 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 1716 */ 1717struct dmub_rb_cmd_domain_control_data { 1718 uint8_t inst : 6; /**< DOMAIN instance to control */ 1719 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 1720 uint8_t reserved[3]; /**< Reserved for future use */ 1721}; 1722 1723/** 1724 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 1725 */ 1726struct dmub_rb_cmd_domain_control { 1727 struct dmub_cmd_header header; /**< header */ 1728 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 1729}; 1730 1731/** 1732 * DPIA tunnel command parameters. 1733 */ 1734struct dmub_cmd_dig_dpia_control_data { 1735 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1736 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1737 union { 1738 uint8_t digmode; /** enum atom_encode_mode_def */ 1739 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1740 } mode_laneset; 1741 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1742 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1743 uint8_t hpdsel; /** =0: HPD is not assigned */ 1744 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1745 uint8_t dpia_id; /** Index of DPIA */ 1746 uint8_t fec_rdy : 1; 1747 uint8_t reserved : 7; 1748 uint32_t reserved1; 1749}; 1750 1751/** 1752 * DMUB command for DPIA tunnel control. 1753 */ 1754struct dmub_rb_cmd_dig1_dpia_control { 1755 struct dmub_cmd_header header; 1756 struct dmub_cmd_dig_dpia_control_data dpia_control; 1757}; 1758 1759/** 1760 * SET_CONFIG Command Payload 1761 */ 1762struct set_config_cmd_payload { 1763 uint8_t msg_type; /* set config message type */ 1764 uint8_t msg_data; /* set config message data */ 1765}; 1766 1767/** 1768 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1769 */ 1770struct dmub_cmd_set_config_control_data { 1771 struct set_config_cmd_payload cmd_pkt; 1772 uint8_t instance; /* DPIA instance */ 1773 uint8_t immed_status; /* Immediate status returned in case of error */ 1774}; 1775 1776/** 1777 * DMUB command structure for SET_CONFIG command. 1778 */ 1779struct dmub_rb_cmd_set_config_access { 1780 struct dmub_cmd_header header; /* header */ 1781 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1782}; 1783 1784/** 1785 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1786 */ 1787struct dmub_cmd_mst_alloc_slots_control_data { 1788 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1789 uint8_t instance; /* DPIA instance */ 1790 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1791 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1792}; 1793 1794/** 1795 * DMUB command structure for SET_ command. 1796 */ 1797struct dmub_rb_cmd_set_mst_alloc_slots { 1798 struct dmub_cmd_header header; /* header */ 1799 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1800}; 1801 1802/** 1803 * DMUB command structure for DPIA HPD int enable control. 1804 */ 1805struct dmub_rb_cmd_dpia_hpd_int_enable { 1806 struct dmub_cmd_header header; /* header */ 1807 uint32_t enable; /* dpia hpd interrupt enable */ 1808}; 1809 1810/** 1811 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1812 */ 1813struct dmub_rb_cmd_dpphy_init { 1814 struct dmub_cmd_header header; /**< header */ 1815 uint8_t reserved[60]; /**< reserved bits */ 1816}; 1817 1818/** 1819 * enum dp_aux_request_action - DP AUX request command listing. 1820 * 1821 * 4 AUX request command bits are shifted to high nibble. 1822 */ 1823enum dp_aux_request_action { 1824 /** I2C-over-AUX write request */ 1825 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1826 /** I2C-over-AUX read request */ 1827 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1828 /** I2C-over-AUX write status request */ 1829 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1830 /** I2C-over-AUX write request with MOT=1 */ 1831 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1832 /** I2C-over-AUX read request with MOT=1 */ 1833 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1834 /** I2C-over-AUX write status request with MOT=1 */ 1835 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1836 /** Native AUX write request */ 1837 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1838 /** Native AUX read request */ 1839 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1840}; 1841 1842/** 1843 * enum aux_return_code_type - DP AUX process return code listing. 1844 */ 1845enum aux_return_code_type { 1846 /** AUX process succeeded */ 1847 AUX_RET_SUCCESS = 0, 1848 /** AUX process failed with unknown reason */ 1849 AUX_RET_ERROR_UNKNOWN, 1850 /** AUX process completed with invalid reply */ 1851 AUX_RET_ERROR_INVALID_REPLY, 1852 /** AUX process timed out */ 1853 AUX_RET_ERROR_TIMEOUT, 1854 /** HPD was low during AUX process */ 1855 AUX_RET_ERROR_HPD_DISCON, 1856 /** Failed to acquire AUX engine */ 1857 AUX_RET_ERROR_ENGINE_ACQUIRE, 1858 /** AUX request not supported */ 1859 AUX_RET_ERROR_INVALID_OPERATION, 1860 /** AUX process not available */ 1861 AUX_RET_ERROR_PROTOCOL_ERROR, 1862}; 1863 1864/** 1865 * enum aux_channel_type - DP AUX channel type listing. 1866 */ 1867enum aux_channel_type { 1868 /** AUX thru Legacy DP AUX */ 1869 AUX_CHANNEL_LEGACY_DDC, 1870 /** AUX thru DPIA DP tunneling */ 1871 AUX_CHANNEL_DPIA 1872}; 1873 1874/** 1875 * struct aux_transaction_parameters - DP AUX request transaction data 1876 */ 1877struct aux_transaction_parameters { 1878 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1879 uint8_t action; /**< enum dp_aux_request_action */ 1880 uint8_t length; /**< DP AUX request data length */ 1881 uint8_t reserved; /**< For future use */ 1882 uint32_t address; /**< DP AUX address */ 1883 uint8_t data[16]; /**< DP AUX write data */ 1884}; 1885 1886/** 1887 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1888 */ 1889struct dmub_cmd_dp_aux_control_data { 1890 uint8_t instance; /**< AUX instance or DPIA instance */ 1891 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1892 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1893 uint8_t reserved0; /**< For future use */ 1894 uint16_t timeout; /**< timeout time in us */ 1895 uint16_t reserved1; /**< For future use */ 1896 enum aux_channel_type type; /**< enum aux_channel_type */ 1897 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1898}; 1899 1900/** 1901 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1902 */ 1903struct dmub_rb_cmd_dp_aux_access { 1904 /** 1905 * Command header. 1906 */ 1907 struct dmub_cmd_header header; 1908 /** 1909 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1910 */ 1911 struct dmub_cmd_dp_aux_control_data aux_control; 1912}; 1913 1914/** 1915 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1916 */ 1917struct dmub_rb_cmd_outbox1_enable { 1918 /** 1919 * Command header. 1920 */ 1921 struct dmub_cmd_header header; 1922 /** 1923 * enable: 0x0 -> disable outbox1 notification (default value) 1924 * 0x1 -> enable outbox1 notification 1925 */ 1926 uint32_t enable; 1927}; 1928 1929/* DP AUX Reply command - OutBox Cmd */ 1930/** 1931 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1932 */ 1933struct aux_reply_data { 1934 /** 1935 * Aux cmd 1936 */ 1937 uint8_t command; 1938 /** 1939 * Aux reply data length (max: 16 bytes) 1940 */ 1941 uint8_t length; 1942 /** 1943 * Alignment only 1944 */ 1945 uint8_t pad[2]; 1946 /** 1947 * Aux reply data 1948 */ 1949 uint8_t data[16]; 1950}; 1951 1952/** 1953 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1954 */ 1955struct aux_reply_control_data { 1956 /** 1957 * Reserved for future use 1958 */ 1959 uint32_t handle; 1960 /** 1961 * Aux Instance 1962 */ 1963 uint8_t instance; 1964 /** 1965 * Aux transaction result: definition in enum aux_return_code_type 1966 */ 1967 uint8_t result; 1968 /** 1969 * Alignment only 1970 */ 1971 uint16_t pad; 1972}; 1973 1974/** 1975 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1976 */ 1977struct dmub_rb_cmd_dp_aux_reply { 1978 /** 1979 * Command header. 1980 */ 1981 struct dmub_cmd_header header; 1982 /** 1983 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1984 */ 1985 struct aux_reply_control_data control; 1986 /** 1987 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1988 */ 1989 struct aux_reply_data reply_data; 1990}; 1991 1992/* DP HPD Notify command - OutBox Cmd */ 1993/** 1994 * DP HPD Type 1995 */ 1996enum dp_hpd_type { 1997 /** 1998 * Normal DP HPD 1999 */ 2000 DP_HPD = 0, 2001 /** 2002 * DP HPD short pulse 2003 */ 2004 DP_IRQ 2005}; 2006 2007/** 2008 * DP HPD Status 2009 */ 2010enum dp_hpd_status { 2011 /** 2012 * DP_HPD status low 2013 */ 2014 DP_HPD_UNPLUG = 0, 2015 /** 2016 * DP_HPD status high 2017 */ 2018 DP_HPD_PLUG 2019}; 2020 2021/** 2022 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2023 */ 2024struct dp_hpd_data { 2025 /** 2026 * DP HPD instance 2027 */ 2028 uint8_t instance; 2029 /** 2030 * HPD type 2031 */ 2032 uint8_t hpd_type; 2033 /** 2034 * HPD status: only for type: DP_HPD to indicate status 2035 */ 2036 uint8_t hpd_status; 2037 /** 2038 * Alignment only 2039 */ 2040 uint8_t pad; 2041}; 2042 2043/** 2044 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2045 */ 2046struct dmub_rb_cmd_dp_hpd_notify { 2047 /** 2048 * Command header. 2049 */ 2050 struct dmub_cmd_header header; 2051 /** 2052 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2053 */ 2054 struct dp_hpd_data hpd_data; 2055}; 2056 2057/** 2058 * Definition of a SET_CONFIG reply from DPOA. 2059 */ 2060enum set_config_status { 2061 SET_CONFIG_PENDING = 0, 2062 SET_CONFIG_ACK_RECEIVED, 2063 SET_CONFIG_RX_TIMEOUT, 2064 SET_CONFIG_UNKNOWN_ERROR, 2065}; 2066 2067/** 2068 * Definition of a set_config reply 2069 */ 2070struct set_config_reply_control_data { 2071 uint8_t instance; /* DPIA Instance */ 2072 uint8_t status; /* Set Config reply */ 2073 uint16_t pad; /* Alignment */ 2074}; 2075 2076/** 2077 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2078 */ 2079struct dmub_rb_cmd_dp_set_config_reply { 2080 struct dmub_cmd_header header; 2081 struct set_config_reply_control_data set_config_reply_control; 2082}; 2083 2084/** 2085 * Definition of a DPIA notification header 2086 */ 2087struct dpia_notification_header { 2088 uint8_t instance; /**< DPIA Instance */ 2089 uint8_t reserved[3]; 2090 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2091}; 2092 2093/** 2094 * Definition of the common data struct of DPIA notification 2095 */ 2096struct dpia_notification_common { 2097 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2098 - sizeof(struct dpia_notification_header)]; 2099}; 2100 2101/** 2102 * Definition of a DPIA notification data 2103 */ 2104struct dpia_bw_allocation_notify_data { 2105 union { 2106 struct { 2107 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2108 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2109 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2110 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2111 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2112 uint16_t reserved: 11; /**< Reserved */ 2113 } bits; 2114 2115 uint16_t flags; 2116 }; 2117 2118 uint8_t cm_id; /**< CM ID */ 2119 uint8_t group_id; /**< Group ID */ 2120 uint8_t granularity; /**< BW Allocation Granularity */ 2121 uint8_t estimated_bw; /**< Estimated_BW */ 2122 uint8_t allocated_bw; /**< Allocated_BW */ 2123 uint8_t reserved; 2124}; 2125 2126/** 2127 * union dpia_notify_data_type - DPIA Notification in Outbox command 2128 */ 2129union dpia_notification_data { 2130 /** 2131 * DPIA Notification for common data struct 2132 */ 2133 struct dpia_notification_common common_data; 2134 2135 /** 2136 * DPIA Notification for DP BW Allocation support 2137 */ 2138 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2139}; 2140 2141/** 2142 * Definition of a DPIA notification payload 2143 */ 2144struct dpia_notification_payload { 2145 struct dpia_notification_header header; 2146 union dpia_notification_data data; /**< DPIA notification payload data */ 2147}; 2148 2149/** 2150 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2151 */ 2152struct dmub_rb_cmd_dpia_notification { 2153 struct dmub_cmd_header header; /**< DPIA notification header */ 2154 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2155}; 2156 2157/** 2158 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2159 */ 2160struct dmub_cmd_hpd_state_query_data { 2161 uint8_t instance; /**< HPD instance or DPIA instance */ 2162 uint8_t result; /**< For returning HPD state */ 2163 uint16_t pad; /** < Alignment */ 2164 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2165 enum aux_return_code_type status; /**< for returning the status of command */ 2166}; 2167 2168/** 2169 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2170 */ 2171struct dmub_rb_cmd_query_hpd_state { 2172 /** 2173 * Command header. 2174 */ 2175 struct dmub_cmd_header header; 2176 /** 2177 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2178 */ 2179 struct dmub_cmd_hpd_state_query_data data; 2180}; 2181 2182/* 2183 * Command IDs should be treated as stable ABI. 2184 * Do not reuse or modify IDs. 2185 */ 2186 2187/** 2188 * PSR command sub-types. 2189 */ 2190enum dmub_cmd_psr_type { 2191 /** 2192 * Set PSR version support. 2193 */ 2194 DMUB_CMD__PSR_SET_VERSION = 0, 2195 /** 2196 * Copy driver-calculated parameters to PSR state. 2197 */ 2198 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2199 /** 2200 * Enable PSR. 2201 */ 2202 DMUB_CMD__PSR_ENABLE = 2, 2203 2204 /** 2205 * Disable PSR. 2206 */ 2207 DMUB_CMD__PSR_DISABLE = 3, 2208 2209 /** 2210 * Set PSR level. 2211 * PSR level is a 16-bit value dicated by driver that 2212 * will enable/disable different functionality. 2213 */ 2214 DMUB_CMD__PSR_SET_LEVEL = 4, 2215 2216 /** 2217 * Forces PSR enabled until an explicit PSR disable call. 2218 */ 2219 DMUB_CMD__PSR_FORCE_STATIC = 5, 2220 /** 2221 * Set vtotal in psr active for FreeSync PSR. 2222 */ 2223 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2224 /** 2225 * Set PSR power option 2226 */ 2227 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2228}; 2229 2230enum dmub_cmd_fams_type { 2231 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2232 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2233 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2234 /** 2235 * For SubVP set manual trigger in FW because it 2236 * triggers DRR_UPDATE_PENDING which SubVP relies 2237 * on (for any SubVP cases that use a DRR display) 2238 */ 2239 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2240}; 2241 2242/** 2243 * PSR versions. 2244 */ 2245enum psr_version { 2246 /** 2247 * PSR version 1. 2248 */ 2249 PSR_VERSION_1 = 0, 2250 /** 2251 * Freesync PSR SU. 2252 */ 2253 PSR_VERSION_SU_1 = 1, 2254 /** 2255 * PSR not supported. 2256 */ 2257 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2258}; 2259 2260/** 2261 * PHY Link rate for DP. 2262 */ 2263enum phy_link_rate { 2264 /** 2265 * not supported. 2266 */ 2267 PHY_RATE_UNKNOWN = 0, 2268 /** 2269 * Rate_1 (RBR) - 1.62 Gbps/Lane 2270 */ 2271 PHY_RATE_162 = 1, 2272 /** 2273 * Rate_2 - 2.16 Gbps/Lane 2274 */ 2275 PHY_RATE_216 = 2, 2276 /** 2277 * Rate_3 - 2.43 Gbps/Lane 2278 */ 2279 PHY_RATE_243 = 3, 2280 /** 2281 * Rate_4 (HBR) - 2.70 Gbps/Lane 2282 */ 2283 PHY_RATE_270 = 4, 2284 /** 2285 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2286 */ 2287 PHY_RATE_324 = 5, 2288 /** 2289 * Rate_6 - 4.32 Gbps/Lane 2290 */ 2291 PHY_RATE_432 = 6, 2292 /** 2293 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2294 */ 2295 PHY_RATE_540 = 7, 2296 /** 2297 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2298 */ 2299 PHY_RATE_810 = 8, 2300 /** 2301 * UHBR10 - 10.0 Gbps/Lane 2302 */ 2303 PHY_RATE_1000 = 9, 2304 /** 2305 * UHBR13.5 - 13.5 Gbps/Lane 2306 */ 2307 PHY_RATE_1350 = 10, 2308 /** 2309 * UHBR10 - 20.0 Gbps/Lane 2310 */ 2311 PHY_RATE_2000 = 11, 2312}; 2313 2314/** 2315 * enum dmub_phy_fsm_state - PHY FSM states. 2316 * PHY FSM state to transit to during PSR enable/disable. 2317 */ 2318enum dmub_phy_fsm_state { 2319 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2320 DMUB_PHY_FSM_RESET, 2321 DMUB_PHY_FSM_RESET_RELEASED, 2322 DMUB_PHY_FSM_SRAM_LOAD_DONE, 2323 DMUB_PHY_FSM_INITIALIZED, 2324 DMUB_PHY_FSM_CALIBRATED, 2325 DMUB_PHY_FSM_CALIBRATED_LP, 2326 DMUB_PHY_FSM_CALIBRATED_PG, 2327 DMUB_PHY_FSM_POWER_DOWN, 2328 DMUB_PHY_FSM_PLL_EN, 2329 DMUB_PHY_FSM_TX_EN, 2330 DMUB_PHY_FSM_FAST_LP, 2331 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 2332 DMUB_PHY_FSM_P2_PLL_OFF_PG, 2333 DMUB_PHY_FSM_P2_PLL_OFF, 2334 DMUB_PHY_FSM_P2_PLL_ON, 2335}; 2336 2337/** 2338 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2339 */ 2340struct dmub_cmd_psr_copy_settings_data { 2341 /** 2342 * Flags that can be set by driver to change some PSR behaviour. 2343 */ 2344 union dmub_psr_debug_flags debug; 2345 /** 2346 * 16-bit value dicated by driver that will enable/disable different functionality. 2347 */ 2348 uint16_t psr_level; 2349 /** 2350 * DPP HW instance. 2351 */ 2352 uint8_t dpp_inst; 2353 /** 2354 * MPCC HW instance. 2355 * Not used in dmub fw, 2356 * dmub fw will get active opp by reading odm registers. 2357 */ 2358 uint8_t mpcc_inst; 2359 /** 2360 * OPP HW instance. 2361 * Not used in dmub fw, 2362 * dmub fw will get active opp by reading odm registers. 2363 */ 2364 uint8_t opp_inst; 2365 /** 2366 * OTG HW instance. 2367 */ 2368 uint8_t otg_inst; 2369 /** 2370 * DIG FE HW instance. 2371 */ 2372 uint8_t digfe_inst; 2373 /** 2374 * DIG BE HW instance. 2375 */ 2376 uint8_t digbe_inst; 2377 /** 2378 * DP PHY HW instance. 2379 */ 2380 uint8_t dpphy_inst; 2381 /** 2382 * AUX HW instance. 2383 */ 2384 uint8_t aux_inst; 2385 /** 2386 * Determines if SMU optimzations are enabled/disabled. 2387 */ 2388 uint8_t smu_optimizations_en; 2389 /** 2390 * Unused. 2391 * TODO: Remove. 2392 */ 2393 uint8_t frame_delay; 2394 /** 2395 * If RFB setup time is greater than the total VBLANK time, 2396 * it is not possible for the sink to capture the video frame 2397 * in the same frame the SDP is sent. In this case, 2398 * the frame capture indication bit should be set and an extra 2399 * static frame should be transmitted to the sink. 2400 */ 2401 uint8_t frame_cap_ind; 2402 /** 2403 * Granularity of Y offset supported by sink. 2404 */ 2405 uint8_t su_y_granularity; 2406 /** 2407 * Indicates whether sink should start capturing 2408 * immediately following active scan line, 2409 * or starting with the 2nd active scan line. 2410 */ 2411 uint8_t line_capture_indication; 2412 /** 2413 * Multi-display optimizations are implemented on certain ASICs. 2414 */ 2415 uint8_t multi_disp_optimizations_en; 2416 /** 2417 * The last possible line SDP may be transmitted without violating 2418 * the RFB setup time or entering the active video frame. 2419 */ 2420 uint16_t init_sdp_deadline; 2421 /** 2422 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 2423 */ 2424 uint8_t rate_control_caps ; 2425 /* 2426 * Force PSRSU always doing full frame update 2427 */ 2428 uint8_t force_ffu_mode; 2429 /** 2430 * Length of each horizontal line in us. 2431 */ 2432 uint32_t line_time_in_us; 2433 /** 2434 * FEC enable status in driver 2435 */ 2436 uint8_t fec_enable_status; 2437 /** 2438 * FEC re-enable delay when PSR exit. 2439 * unit is 100us, range form 0~255(0xFF). 2440 */ 2441 uint8_t fec_enable_delay_in100us; 2442 /** 2443 * PSR control version. 2444 */ 2445 uint8_t cmd_version; 2446 /** 2447 * Panel Instance. 2448 * Panel instance to identify which psr_state to use 2449 * Currently the support is only for 0 or 1 2450 */ 2451 uint8_t panel_inst; 2452 /* 2453 * DSC enable status in driver 2454 */ 2455 uint8_t dsc_enable_status; 2456 /* 2457 * Use FSM state for PSR power up/down 2458 */ 2459 uint8_t use_phy_fsm; 2460 /** 2461 * frame delay for frame re-lock 2462 */ 2463 uint8_t relock_delay_frame_cnt; 2464 /** 2465 * Explicit padding to 4 byte boundary. 2466 */ 2467 uint8_t pad3; 2468 /** 2469 * DSC Slice height. 2470 */ 2471 uint16_t dsc_slice_height; 2472 /** 2473 * Some panels request main link off before xth vertical line 2474 */ 2475 uint16_t poweroff_before_vertical_line; 2476}; 2477 2478/** 2479 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 2480 */ 2481struct dmub_rb_cmd_psr_copy_settings { 2482 /** 2483 * Command header. 2484 */ 2485 struct dmub_cmd_header header; 2486 /** 2487 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 2488 */ 2489 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 2490}; 2491 2492/** 2493 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 2494 */ 2495struct dmub_cmd_psr_set_level_data { 2496 /** 2497 * 16-bit value dicated by driver that will enable/disable different functionality. 2498 */ 2499 uint16_t psr_level; 2500 /** 2501 * PSR control version. 2502 */ 2503 uint8_t cmd_version; 2504 /** 2505 * Panel Instance. 2506 * Panel instance to identify which psr_state to use 2507 * Currently the support is only for 0 or 1 2508 */ 2509 uint8_t panel_inst; 2510}; 2511 2512/** 2513 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2514 */ 2515struct dmub_rb_cmd_psr_set_level { 2516 /** 2517 * Command header. 2518 */ 2519 struct dmub_cmd_header header; 2520 /** 2521 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 2522 */ 2523 struct dmub_cmd_psr_set_level_data psr_set_level_data; 2524}; 2525 2526struct dmub_rb_cmd_psr_enable_data { 2527 /** 2528 * PSR control version. 2529 */ 2530 uint8_t cmd_version; 2531 /** 2532 * Panel Instance. 2533 * Panel instance to identify which psr_state to use 2534 * Currently the support is only for 0 or 1 2535 */ 2536 uint8_t panel_inst; 2537 /** 2538 * Phy state to enter. 2539 * Values to use are defined in dmub_phy_fsm_state 2540 */ 2541 uint8_t phy_fsm_state; 2542 /** 2543 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 2544 * Set this using enum phy_link_rate. 2545 * This does not support HDMI/DP2 for now. 2546 */ 2547 uint8_t phy_rate; 2548}; 2549 2550/** 2551 * Definition of a DMUB_CMD__PSR_ENABLE command. 2552 * PSR enable/disable is controlled using the sub_type. 2553 */ 2554struct dmub_rb_cmd_psr_enable { 2555 /** 2556 * Command header. 2557 */ 2558 struct dmub_cmd_header header; 2559 2560 struct dmub_rb_cmd_psr_enable_data data; 2561}; 2562 2563/** 2564 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2565 */ 2566struct dmub_cmd_psr_set_version_data { 2567 /** 2568 * PSR version that FW should implement. 2569 */ 2570 enum psr_version version; 2571 /** 2572 * PSR control version. 2573 */ 2574 uint8_t cmd_version; 2575 /** 2576 * Panel Instance. 2577 * Panel instance to identify which psr_state to use 2578 * Currently the support is only for 0 or 1 2579 */ 2580 uint8_t panel_inst; 2581 /** 2582 * Explicit padding to 4 byte boundary. 2583 */ 2584 uint8_t pad[2]; 2585}; 2586 2587/** 2588 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2589 */ 2590struct dmub_rb_cmd_psr_set_version { 2591 /** 2592 * Command header. 2593 */ 2594 struct dmub_cmd_header header; 2595 /** 2596 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2597 */ 2598 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2599}; 2600 2601struct dmub_cmd_psr_force_static_data { 2602 /** 2603 * PSR control version. 2604 */ 2605 uint8_t cmd_version; 2606 /** 2607 * Panel Instance. 2608 * Panel instance to identify which psr_state to use 2609 * Currently the support is only for 0 or 1 2610 */ 2611 uint8_t panel_inst; 2612 /** 2613 * Explicit padding to 4 byte boundary. 2614 */ 2615 uint8_t pad[2]; 2616}; 2617 2618/** 2619 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2620 */ 2621struct dmub_rb_cmd_psr_force_static { 2622 /** 2623 * Command header. 2624 */ 2625 struct dmub_cmd_header header; 2626 /** 2627 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2628 */ 2629 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2630}; 2631 2632/** 2633 * PSR SU debug flags. 2634 */ 2635union dmub_psr_su_debug_flags { 2636 /** 2637 * PSR SU debug flags. 2638 */ 2639 struct { 2640 /** 2641 * Update dirty rect in SW only. 2642 */ 2643 uint8_t update_dirty_rect_only : 1; 2644 /** 2645 * Reset the cursor/plane state before processing the call. 2646 */ 2647 uint8_t reset_state : 1; 2648 } bitfields; 2649 2650 /** 2651 * Union for debug flags. 2652 */ 2653 uint32_t u32All; 2654}; 2655 2656/** 2657 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2658 * This triggers a selective update for PSR SU. 2659 */ 2660struct dmub_cmd_update_dirty_rect_data { 2661 /** 2662 * Dirty rects from OS. 2663 */ 2664 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2665 /** 2666 * PSR SU debug flags. 2667 */ 2668 union dmub_psr_su_debug_flags debug_flags; 2669 /** 2670 * OTG HW instance. 2671 */ 2672 uint8_t pipe_idx; 2673 /** 2674 * Number of dirty rects. 2675 */ 2676 uint8_t dirty_rect_count; 2677 /** 2678 * PSR control version. 2679 */ 2680 uint8_t cmd_version; 2681 /** 2682 * Panel Instance. 2683 * Panel instance to identify which psr_state to use 2684 * Currently the support is only for 0 or 1 2685 */ 2686 uint8_t panel_inst; 2687}; 2688 2689/** 2690 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2691 */ 2692struct dmub_rb_cmd_update_dirty_rect { 2693 /** 2694 * Command header. 2695 */ 2696 struct dmub_cmd_header header; 2697 /** 2698 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2699 */ 2700 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2701}; 2702 2703/** 2704 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2705 */ 2706union dmub_reg_cursor_control_cfg { 2707 struct { 2708 uint32_t cur_enable: 1; 2709 uint32_t reser0: 3; 2710 uint32_t cur_2x_magnify: 1; 2711 uint32_t reser1: 3; 2712 uint32_t mode: 3; 2713 uint32_t reser2: 5; 2714 uint32_t pitch: 2; 2715 uint32_t reser3: 6; 2716 uint32_t line_per_chunk: 5; 2717 uint32_t reser4: 3; 2718 } bits; 2719 uint32_t raw; 2720}; 2721struct dmub_cursor_position_cache_hubp { 2722 union dmub_reg_cursor_control_cfg cur_ctl; 2723 union dmub_reg_position_cfg { 2724 struct { 2725 uint32_t cur_x_pos: 16; 2726 uint32_t cur_y_pos: 16; 2727 } bits; 2728 uint32_t raw; 2729 } position; 2730 union dmub_reg_hot_spot_cfg { 2731 struct { 2732 uint32_t hot_x: 16; 2733 uint32_t hot_y: 16; 2734 } bits; 2735 uint32_t raw; 2736 } hot_spot; 2737 union dmub_reg_dst_offset_cfg { 2738 struct { 2739 uint32_t dst_x_offset: 13; 2740 uint32_t reserved: 19; 2741 } bits; 2742 uint32_t raw; 2743 } dst_offset; 2744}; 2745 2746union dmub_reg_cur0_control_cfg { 2747 struct { 2748 uint32_t cur0_enable: 1; 2749 uint32_t expansion_mode: 1; 2750 uint32_t reser0: 1; 2751 uint32_t cur0_rom_en: 1; 2752 uint32_t mode: 3; 2753 uint32_t reserved: 25; 2754 } bits; 2755 uint32_t raw; 2756}; 2757struct dmub_cursor_position_cache_dpp { 2758 union dmub_reg_cur0_control_cfg cur0_ctl; 2759}; 2760struct dmub_cursor_position_cfg { 2761 struct dmub_cursor_position_cache_hubp pHubp; 2762 struct dmub_cursor_position_cache_dpp pDpp; 2763 uint8_t pipe_idx; 2764 /* 2765 * Padding is required. To be 4 Bytes Aligned. 2766 */ 2767 uint8_t padding[3]; 2768}; 2769 2770struct dmub_cursor_attribute_cache_hubp { 2771 uint32_t SURFACE_ADDR_HIGH; 2772 uint32_t SURFACE_ADDR; 2773 union dmub_reg_cursor_control_cfg cur_ctl; 2774 union dmub_reg_cursor_size_cfg { 2775 struct { 2776 uint32_t width: 16; 2777 uint32_t height: 16; 2778 } bits; 2779 uint32_t raw; 2780 } size; 2781 union dmub_reg_cursor_settings_cfg { 2782 struct { 2783 uint32_t dst_y_offset: 8; 2784 uint32_t chunk_hdl_adjust: 2; 2785 uint32_t reserved: 22; 2786 } bits; 2787 uint32_t raw; 2788 } settings; 2789}; 2790struct dmub_cursor_attribute_cache_dpp { 2791 union dmub_reg_cur0_control_cfg cur0_ctl; 2792}; 2793struct dmub_cursor_attributes_cfg { 2794 struct dmub_cursor_attribute_cache_hubp aHubp; 2795 struct dmub_cursor_attribute_cache_dpp aDpp; 2796}; 2797 2798struct dmub_cmd_update_cursor_payload0 { 2799 /** 2800 * Cursor dirty rects. 2801 */ 2802 struct dmub_rect cursor_rect; 2803 /** 2804 * PSR SU debug flags. 2805 */ 2806 union dmub_psr_su_debug_flags debug_flags; 2807 /** 2808 * Cursor enable/disable. 2809 */ 2810 uint8_t enable; 2811 /** 2812 * OTG HW instance. 2813 */ 2814 uint8_t pipe_idx; 2815 /** 2816 * PSR control version. 2817 */ 2818 uint8_t cmd_version; 2819 /** 2820 * Panel Instance. 2821 * Panel instance to identify which psr_state to use 2822 * Currently the support is only for 0 or 1 2823 */ 2824 uint8_t panel_inst; 2825 /** 2826 * Cursor Position Register. 2827 * Registers contains Hubp & Dpp modules 2828 */ 2829 struct dmub_cursor_position_cfg position_cfg; 2830}; 2831 2832struct dmub_cmd_update_cursor_payload1 { 2833 struct dmub_cursor_attributes_cfg attribute_cfg; 2834}; 2835 2836union dmub_cmd_update_cursor_info_data { 2837 struct dmub_cmd_update_cursor_payload0 payload0; 2838 struct dmub_cmd_update_cursor_payload1 payload1; 2839}; 2840/** 2841 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2842 */ 2843struct dmub_rb_cmd_update_cursor_info { 2844 /** 2845 * Command header. 2846 */ 2847 struct dmub_cmd_header header; 2848 /** 2849 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2850 */ 2851 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2852}; 2853 2854/** 2855 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2856 */ 2857struct dmub_cmd_psr_set_vtotal_data { 2858 /** 2859 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2860 */ 2861 uint16_t psr_vtotal_idle; 2862 /** 2863 * PSR control version. 2864 */ 2865 uint8_t cmd_version; 2866 /** 2867 * Panel Instance. 2868 * Panel instance to identify which psr_state to use 2869 * Currently the support is only for 0 or 1 2870 */ 2871 uint8_t panel_inst; 2872 /* 2873 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2874 */ 2875 uint16_t psr_vtotal_su; 2876 /** 2877 * Explicit padding to 4 byte boundary. 2878 */ 2879 uint8_t pad2[2]; 2880}; 2881 2882/** 2883 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2884 */ 2885struct dmub_rb_cmd_psr_set_vtotal { 2886 /** 2887 * Command header. 2888 */ 2889 struct dmub_cmd_header header; 2890 /** 2891 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2892 */ 2893 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2894}; 2895 2896/** 2897 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2898 */ 2899struct dmub_cmd_psr_set_power_opt_data { 2900 /** 2901 * PSR control version. 2902 */ 2903 uint8_t cmd_version; 2904 /** 2905 * Panel Instance. 2906 * Panel instance to identify which psr_state to use 2907 * Currently the support is only for 0 or 1 2908 */ 2909 uint8_t panel_inst; 2910 /** 2911 * Explicit padding to 4 byte boundary. 2912 */ 2913 uint8_t pad[2]; 2914 /** 2915 * PSR power option 2916 */ 2917 uint32_t power_opt; 2918}; 2919 2920/** 2921 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2922 */ 2923struct dmub_rb_cmd_psr_set_power_opt { 2924 /** 2925 * Command header. 2926 */ 2927 struct dmub_cmd_header header; 2928 /** 2929 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2930 */ 2931 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2932}; 2933 2934#define REPLAY_RESIDENCY_MODE_SHIFT (0) 2935#define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 2936 2937#define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2938# define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 2939# define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 2940# define REPLAY_RESIDENCY_MODE_IPS 0x10 2941 2942#define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2943# define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2944# define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 2945 2946enum replay_state { 2947 REPLAY_STATE_0 = 0x0, 2948 REPLAY_STATE_1 = 0x10, 2949 REPLAY_STATE_1A = 0x11, 2950 REPLAY_STATE_2 = 0x20, 2951 REPLAY_STATE_3 = 0x30, 2952 REPLAY_STATE_3INIT = 0x31, 2953 REPLAY_STATE_4 = 0x40, 2954 REPLAY_STATE_4A = 0x41, 2955 REPLAY_STATE_4B = 0x42, 2956 REPLAY_STATE_4C = 0x43, 2957 REPLAY_STATE_4D = 0x44, 2958 REPLAY_STATE_4B_LOCKED = 0x4A, 2959 REPLAY_STATE_4C_UNLOCKED = 0x4B, 2960 REPLAY_STATE_5 = 0x50, 2961 REPLAY_STATE_5A = 0x51, 2962 REPLAY_STATE_5B = 0x52, 2963 REPLAY_STATE_5A_LOCKED = 0x5A, 2964 REPLAY_STATE_5B_UNLOCKED = 0x5B, 2965 REPLAY_STATE_6 = 0x60, 2966 REPLAY_STATE_6A = 0x61, 2967 REPLAY_STATE_6B = 0x62, 2968 REPLAY_STATE_INVALID = 0xFF, 2969}; 2970 2971/** 2972 * Replay command sub-types. 2973 */ 2974enum dmub_cmd_replay_type { 2975 /** 2976 * Copy driver-calculated parameters to REPLAY state. 2977 */ 2978 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 2979 /** 2980 * Enable REPLAY. 2981 */ 2982 DMUB_CMD__REPLAY_ENABLE = 1, 2983 /** 2984 * Set Replay power option. 2985 */ 2986 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 2987 /** 2988 * Set coasting vtotal. 2989 */ 2990 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 2991 /** 2992 * Set power opt and coasting vtotal. 2993 */ 2994 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 2995 /** 2996 * Set disabled iiming sync. 2997 */ 2998 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 2999 /** 3000 * Set Residency Frameupdate Timer. 3001 */ 3002 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3003 /** 3004 * Set pseudo vtotal 3005 */ 3006 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3007}; 3008 3009/** 3010 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3011 */ 3012struct dmub_cmd_replay_copy_settings_data { 3013 /** 3014 * Flags that can be set by driver to change some replay behaviour. 3015 */ 3016 union replay_debug_flags debug; 3017 3018 /** 3019 * @flags: Flags used to determine feature functionality. 3020 */ 3021 union replay_hw_flags flags; 3022 3023 /** 3024 * DPP HW instance. 3025 */ 3026 uint8_t dpp_inst; 3027 /** 3028 * OTG HW instance. 3029 */ 3030 uint8_t otg_inst; 3031 /** 3032 * DIG FE HW instance. 3033 */ 3034 uint8_t digfe_inst; 3035 /** 3036 * DIG BE HW instance. 3037 */ 3038 uint8_t digbe_inst; 3039 /** 3040 * AUX HW instance. 3041 */ 3042 uint8_t aux_inst; 3043 /** 3044 * Panel Instance. 3045 * Panel isntance to identify which psr_state to use 3046 * Currently the support is only for 0 or 1 3047 */ 3048 uint8_t panel_inst; 3049 /** 3050 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3051 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3052 */ 3053 uint8_t pixel_deviation_per_line; 3054 /** 3055 * @max_deviation_line: The max number of deviation line that can keep the timing 3056 * synchronized between the Source and Sink during Replay normal sleep mode. 3057 */ 3058 uint8_t max_deviation_line; 3059 /** 3060 * Length of each horizontal line in ns. 3061 */ 3062 uint32_t line_time_in_ns; 3063 /** 3064 * PHY instance. 3065 */ 3066 uint8_t dpphy_inst; 3067 /** 3068 * Determines if SMU optimzations are enabled/disabled. 3069 */ 3070 uint8_t smu_optimizations_en; 3071 /** 3072 * Determines if timing sync are enabled/disabled. 3073 */ 3074 uint8_t replay_timing_sync_supported; 3075 /* 3076 * Use FSM state for Replay power up/down 3077 */ 3078 uint8_t use_phy_fsm; 3079}; 3080 3081/** 3082 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3083 */ 3084struct dmub_rb_cmd_replay_copy_settings { 3085 /** 3086 * Command header. 3087 */ 3088 struct dmub_cmd_header header; 3089 /** 3090 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3091 */ 3092 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3093}; 3094 3095/** 3096 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3097 */ 3098enum replay_enable { 3099 /** 3100 * Disable REPLAY. 3101 */ 3102 REPLAY_DISABLE = 0, 3103 /** 3104 * Enable REPLAY. 3105 */ 3106 REPLAY_ENABLE = 1, 3107}; 3108 3109/** 3110 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3111 */ 3112struct dmub_rb_cmd_replay_enable_data { 3113 /** 3114 * Replay enable or disable. 3115 */ 3116 uint8_t enable; 3117 /** 3118 * Panel Instance. 3119 * Panel isntance to identify which replay_state to use 3120 * Currently the support is only for 0 or 1 3121 */ 3122 uint8_t panel_inst; 3123 /** 3124 * Phy state to enter. 3125 * Values to use are defined in dmub_phy_fsm_state 3126 */ 3127 uint8_t phy_fsm_state; 3128 /** 3129 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3130 * Set this using enum phy_link_rate. 3131 * This does not support HDMI/DP2 for now. 3132 */ 3133 uint8_t phy_rate; 3134}; 3135 3136/** 3137 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3138 * Replay enable/disable is controlled using action in data. 3139 */ 3140struct dmub_rb_cmd_replay_enable { 3141 /** 3142 * Command header. 3143 */ 3144 struct dmub_cmd_header header; 3145 3146 struct dmub_rb_cmd_replay_enable_data data; 3147}; 3148 3149/** 3150 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3151 */ 3152struct dmub_cmd_replay_set_power_opt_data { 3153 /** 3154 * Panel Instance. 3155 * Panel isntance to identify which replay_state to use 3156 * Currently the support is only for 0 or 1 3157 */ 3158 uint8_t panel_inst; 3159 /** 3160 * Explicit padding to 4 byte boundary. 3161 */ 3162 uint8_t pad[3]; 3163 /** 3164 * REPLAY power option 3165 */ 3166 uint32_t power_opt; 3167}; 3168 3169/** 3170 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3171 */ 3172struct dmub_cmd_replay_set_timing_sync_data { 3173 /** 3174 * Panel Instance. 3175 * Panel isntance to identify which replay_state to use 3176 * Currently the support is only for 0 or 1 3177 */ 3178 uint8_t panel_inst; 3179 /** 3180 * REPLAY set_timing_sync 3181 */ 3182 uint8_t timing_sync_supported; 3183 /** 3184 * Explicit padding to 4 byte boundary. 3185 */ 3186 uint8_t pad[2]; 3187}; 3188 3189/** 3190 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3191 */ 3192struct dmub_cmd_replay_set_pseudo_vtotal { 3193 /** 3194 * Panel Instance. 3195 * Panel isntance to identify which replay_state to use 3196 * Currently the support is only for 0 or 1 3197 */ 3198 uint8_t panel_inst; 3199 /** 3200 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3201 */ 3202 uint16_t vtotal; 3203 /** 3204 * Explicit padding to 4 byte boundary. 3205 */ 3206 uint8_t pad; 3207}; 3208 3209/** 3210 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3211 */ 3212struct dmub_rb_cmd_replay_set_power_opt { 3213 /** 3214 * Command header. 3215 */ 3216 struct dmub_cmd_header header; 3217 /** 3218 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3219 */ 3220 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3221}; 3222 3223/** 3224 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3225 */ 3226struct dmub_cmd_replay_set_coasting_vtotal_data { 3227 /** 3228 * 16-bit value dicated by driver that indicates the coasting vtotal. 3229 */ 3230 uint16_t coasting_vtotal; 3231 /** 3232 * REPLAY control version. 3233 */ 3234 uint8_t cmd_version; 3235 /** 3236 * Panel Instance. 3237 * Panel isntance to identify which replay_state to use 3238 * Currently the support is only for 0 or 1 3239 */ 3240 uint8_t panel_inst; 3241 /** 3242 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 3243 */ 3244 uint16_t coasting_vtotal_high; 3245 /** 3246 * Explicit padding to 4 byte boundary. 3247 */ 3248 uint8_t pad[2]; 3249}; 3250 3251/** 3252 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3253 */ 3254struct dmub_rb_cmd_replay_set_coasting_vtotal { 3255 /** 3256 * Command header. 3257 */ 3258 struct dmub_cmd_header header; 3259 /** 3260 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3261 */ 3262 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3263}; 3264 3265/** 3266 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 3267 */ 3268struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 3269 /** 3270 * Command header. 3271 */ 3272 struct dmub_cmd_header header; 3273 /** 3274 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3275 */ 3276 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3277 /** 3278 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 3279 */ 3280 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 3281}; 3282 3283/** 3284 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3285 */ 3286struct dmub_rb_cmd_replay_set_timing_sync { 3287 /** 3288 * Command header. 3289 */ 3290 struct dmub_cmd_header header; 3291 /** 3292 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3293 */ 3294 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 3295}; 3296 3297/** 3298 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3299 */ 3300struct dmub_rb_cmd_replay_set_pseudo_vtotal { 3301 /** 3302 * Command header. 3303 */ 3304 struct dmub_cmd_header header; 3305 /** 3306 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3307 */ 3308 struct dmub_cmd_replay_set_pseudo_vtotal data; 3309}; 3310 3311/** 3312 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 3313 */ 3314struct dmub_cmd_replay_frameupdate_timer_data { 3315 /** 3316 * Panel Instance. 3317 * Panel isntance to identify which replay_state to use 3318 * Currently the support is only for 0 or 1 3319 */ 3320 uint8_t panel_inst; 3321 /** 3322 * Replay Frameupdate Timer Enable or not 3323 */ 3324 uint8_t enable; 3325 /** 3326 * REPLAY force reflash frame update number 3327 */ 3328 uint16_t frameupdate_count; 3329}; 3330/** 3331 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 3332 */ 3333struct dmub_rb_cmd_replay_set_frameupdate_timer { 3334 /** 3335 * Command header. 3336 */ 3337 struct dmub_cmd_header header; 3338 /** 3339 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3340 */ 3341 struct dmub_cmd_replay_frameupdate_timer_data data; 3342}; 3343 3344/** 3345 * Definition union of replay command set 3346 */ 3347union dmub_replay_cmd_set { 3348 /** 3349 * Panel Instance. 3350 * Panel isntance to identify which replay_state to use 3351 * Currently the support is only for 0 or 1 3352 */ 3353 uint8_t panel_inst; 3354 /** 3355 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 3356 */ 3357 struct dmub_cmd_replay_set_timing_sync_data sync_data; 3358 /** 3359 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 3360 */ 3361 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 3362 /** 3363 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 3364 */ 3365 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 3366}; 3367 3368/** 3369 * Set of HW components that can be locked. 3370 * 3371 * Note: If updating with more HW components, fields 3372 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3373 */ 3374union dmub_hw_lock_flags { 3375 /** 3376 * Set of HW components that can be locked. 3377 */ 3378 struct { 3379 /** 3380 * Lock/unlock OTG master update lock. 3381 */ 3382 uint8_t lock_pipe : 1; 3383 /** 3384 * Lock/unlock cursor. 3385 */ 3386 uint8_t lock_cursor : 1; 3387 /** 3388 * Lock/unlock global update lock. 3389 */ 3390 uint8_t lock_dig : 1; 3391 /** 3392 * Triple buffer lock requires additional hw programming to usual OTG master lock. 3393 */ 3394 uint8_t triple_buffer_lock : 1; 3395 } bits; 3396 3397 /** 3398 * Union for HW Lock flags. 3399 */ 3400 uint8_t u8All; 3401}; 3402 3403/** 3404 * Instances of HW to be locked. 3405 * 3406 * Note: If updating with more HW components, fields 3407 * in dmub_inbox0_cmd_lock_hw must be updated to match. 3408 */ 3409struct dmub_hw_lock_inst_flags { 3410 /** 3411 * OTG HW instance for OTG master update lock. 3412 */ 3413 uint8_t otg_inst; 3414 /** 3415 * OPP instance for cursor lock. 3416 */ 3417 uint8_t opp_inst; 3418 /** 3419 * OTG HW instance for global update lock. 3420 * TODO: Remove, and re-use otg_inst. 3421 */ 3422 uint8_t dig_inst; 3423 /** 3424 * Explicit pad to 4 byte boundary. 3425 */ 3426 uint8_t pad; 3427}; 3428 3429/** 3430 * Clients that can acquire the HW Lock Manager. 3431 * 3432 * Note: If updating with more clients, fields in 3433 * dmub_inbox0_cmd_lock_hw must be updated to match. 3434 */ 3435enum hw_lock_client { 3436 /** 3437 * Driver is the client of HW Lock Manager. 3438 */ 3439 HW_LOCK_CLIENT_DRIVER = 0, 3440 /** 3441 * PSR SU is the client of HW Lock Manager. 3442 */ 3443 HW_LOCK_CLIENT_PSR_SU = 1, 3444 HW_LOCK_CLIENT_SUBVP = 3, 3445 /** 3446 * Replay is the client of HW Lock Manager. 3447 */ 3448 HW_LOCK_CLIENT_REPLAY = 4, 3449 /** 3450 * Invalid client. 3451 */ 3452 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 3453}; 3454 3455/** 3456 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3457 */ 3458struct dmub_cmd_lock_hw_data { 3459 /** 3460 * Specifies the client accessing HW Lock Manager. 3461 */ 3462 enum hw_lock_client client; 3463 /** 3464 * HW instances to be locked. 3465 */ 3466 struct dmub_hw_lock_inst_flags inst_flags; 3467 /** 3468 * Which components to be locked. 3469 */ 3470 union dmub_hw_lock_flags hw_locks; 3471 /** 3472 * Specifies lock/unlock. 3473 */ 3474 uint8_t lock; 3475 /** 3476 * HW can be unlocked separately from releasing the HW Lock Mgr. 3477 * This flag is set if the client wishes to release the object. 3478 */ 3479 uint8_t should_release; 3480 /** 3481 * Explicit padding to 4 byte boundary. 3482 */ 3483 uint8_t pad; 3484}; 3485 3486/** 3487 * Definition of a DMUB_CMD__HW_LOCK command. 3488 * Command is used by driver and FW. 3489 */ 3490struct dmub_rb_cmd_lock_hw { 3491 /** 3492 * Command header. 3493 */ 3494 struct dmub_cmd_header header; 3495 /** 3496 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 3497 */ 3498 struct dmub_cmd_lock_hw_data lock_hw_data; 3499}; 3500 3501/** 3502 * ABM command sub-types. 3503 */ 3504enum dmub_cmd_abm_type { 3505 /** 3506 * Initialize parameters for ABM algorithm. 3507 * Data is passed through an indirect buffer. 3508 */ 3509 DMUB_CMD__ABM_INIT_CONFIG = 0, 3510 /** 3511 * Set OTG and panel HW instance. 3512 */ 3513 DMUB_CMD__ABM_SET_PIPE = 1, 3514 /** 3515 * Set user requested backklight level. 3516 */ 3517 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 3518 /** 3519 * Set ABM operating/aggression level. 3520 */ 3521 DMUB_CMD__ABM_SET_LEVEL = 3, 3522 /** 3523 * Set ambient light level. 3524 */ 3525 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 3526 /** 3527 * Enable/disable fractional duty cycle for backlight PWM. 3528 */ 3529 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 3530 3531 /** 3532 * unregister vertical interrupt after steady state is reached 3533 */ 3534 DMUB_CMD__ABM_PAUSE = 6, 3535 3536 /** 3537 * Save and Restore ABM state. On save we save parameters, and 3538 * on restore we update state with passed in data. 3539 */ 3540 DMUB_CMD__ABM_SAVE_RESTORE = 7, 3541}; 3542 3543/** 3544 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 3545 * Requirements: 3546 * - Padded explicitly to 32-bit boundary. 3547 * - Must ensure this structure matches the one on driver-side, 3548 * otherwise it won't be aligned. 3549 */ 3550struct abm_config_table { 3551 /** 3552 * Gamma curve thresholds, used for crgb conversion. 3553 */ 3554 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 3555 /** 3556 * Gamma curve offsets, used for crgb conversion. 3557 */ 3558 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 3559 /** 3560 * Gamma curve slopes, used for crgb conversion. 3561 */ 3562 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 3563 /** 3564 * Custom backlight curve thresholds. 3565 */ 3566 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 3567 /** 3568 * Custom backlight curve offsets. 3569 */ 3570 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 3571 /** 3572 * Ambient light thresholds. 3573 */ 3574 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 3575 /** 3576 * Minimum programmable backlight. 3577 */ 3578 uint16_t min_abm_backlight; // 122B 3579 /** 3580 * Minimum reduction values. 3581 */ 3582 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 3583 /** 3584 * Maximum reduction values. 3585 */ 3586 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 3587 /** 3588 * Bright positive gain. 3589 */ 3590 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 3591 /** 3592 * Dark negative gain. 3593 */ 3594 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 3595 /** 3596 * Hybrid factor. 3597 */ 3598 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 3599 /** 3600 * Contrast factor. 3601 */ 3602 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 3603 /** 3604 * Deviation gain. 3605 */ 3606 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 3607 /** 3608 * Minimum knee. 3609 */ 3610 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 3611 /** 3612 * Maximum knee. 3613 */ 3614 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 3615 /** 3616 * Unused. 3617 */ 3618 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 3619 /** 3620 * Explicit padding to 4 byte boundary. 3621 */ 3622 uint8_t pad3[3]; // 229B 3623 /** 3624 * Backlight ramp reduction. 3625 */ 3626 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 3627 /** 3628 * Backlight ramp start. 3629 */ 3630 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 3631}; 3632 3633/** 3634 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3635 */ 3636struct dmub_cmd_abm_set_pipe_data { 3637 /** 3638 * OTG HW instance. 3639 */ 3640 uint8_t otg_inst; 3641 3642 /** 3643 * Panel Control HW instance. 3644 */ 3645 uint8_t panel_inst; 3646 3647 /** 3648 * Controls how ABM will interpret a set pipe or set level command. 3649 */ 3650 uint8_t set_pipe_option; 3651 3652 /** 3653 * Unused. 3654 * TODO: Remove. 3655 */ 3656 uint8_t ramping_boundary; 3657 3658 /** 3659 * PwrSeq HW Instance. 3660 */ 3661 uint8_t pwrseq_inst; 3662 3663 /** 3664 * Explicit padding to 4 byte boundary. 3665 */ 3666 uint8_t pad[3]; 3667}; 3668 3669/** 3670 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3671 */ 3672struct dmub_rb_cmd_abm_set_pipe { 3673 /** 3674 * Command header. 3675 */ 3676 struct dmub_cmd_header header; 3677 3678 /** 3679 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 3680 */ 3681 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 3682}; 3683 3684/** 3685 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3686 */ 3687struct dmub_cmd_abm_set_backlight_data { 3688 /** 3689 * Number of frames to ramp to backlight user level. 3690 */ 3691 uint32_t frame_ramp; 3692 3693 /** 3694 * Requested backlight level from user. 3695 */ 3696 uint32_t backlight_user_level; 3697 3698 /** 3699 * ABM control version. 3700 */ 3701 uint8_t version; 3702 3703 /** 3704 * Panel Control HW instance mask. 3705 * Bit 0 is Panel Control HW instance 0. 3706 * Bit 1 is Panel Control HW instance 1. 3707 */ 3708 uint8_t panel_mask; 3709 3710 /** 3711 * Explicit padding to 4 byte boundary. 3712 */ 3713 uint8_t pad[2]; 3714}; 3715 3716/** 3717 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3718 */ 3719struct dmub_rb_cmd_abm_set_backlight { 3720 /** 3721 * Command header. 3722 */ 3723 struct dmub_cmd_header header; 3724 3725 /** 3726 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 3727 */ 3728 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 3729}; 3730 3731/** 3732 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3733 */ 3734struct dmub_cmd_abm_set_level_data { 3735 /** 3736 * Set current ABM operating/aggression level. 3737 */ 3738 uint32_t level; 3739 3740 /** 3741 * ABM control version. 3742 */ 3743 uint8_t version; 3744 3745 /** 3746 * Panel Control HW instance mask. 3747 * Bit 0 is Panel Control HW instance 0. 3748 * Bit 1 is Panel Control HW instance 1. 3749 */ 3750 uint8_t panel_mask; 3751 3752 /** 3753 * Explicit padding to 4 byte boundary. 3754 */ 3755 uint8_t pad[2]; 3756}; 3757 3758/** 3759 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3760 */ 3761struct dmub_rb_cmd_abm_set_level { 3762 /** 3763 * Command header. 3764 */ 3765 struct dmub_cmd_header header; 3766 3767 /** 3768 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 3769 */ 3770 struct dmub_cmd_abm_set_level_data abm_set_level_data; 3771}; 3772 3773/** 3774 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3775 */ 3776struct dmub_cmd_abm_set_ambient_level_data { 3777 /** 3778 * Ambient light sensor reading from OS. 3779 */ 3780 uint32_t ambient_lux; 3781 3782 /** 3783 * ABM control version. 3784 */ 3785 uint8_t version; 3786 3787 /** 3788 * Panel Control HW instance mask. 3789 * Bit 0 is Panel Control HW instance 0. 3790 * Bit 1 is Panel Control HW instance 1. 3791 */ 3792 uint8_t panel_mask; 3793 3794 /** 3795 * Explicit padding to 4 byte boundary. 3796 */ 3797 uint8_t pad[2]; 3798}; 3799 3800/** 3801 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3802 */ 3803struct dmub_rb_cmd_abm_set_ambient_level { 3804 /** 3805 * Command header. 3806 */ 3807 struct dmub_cmd_header header; 3808 3809 /** 3810 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3811 */ 3812 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 3813}; 3814 3815/** 3816 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3817 */ 3818struct dmub_cmd_abm_set_pwm_frac_data { 3819 /** 3820 * Enable/disable fractional duty cycle for backlight PWM. 3821 * TODO: Convert to uint8_t. 3822 */ 3823 uint32_t fractional_pwm; 3824 3825 /** 3826 * ABM control version. 3827 */ 3828 uint8_t version; 3829 3830 /** 3831 * Panel Control HW instance mask. 3832 * Bit 0 is Panel Control HW instance 0. 3833 * Bit 1 is Panel Control HW instance 1. 3834 */ 3835 uint8_t panel_mask; 3836 3837 /** 3838 * Explicit padding to 4 byte boundary. 3839 */ 3840 uint8_t pad[2]; 3841}; 3842 3843/** 3844 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3845 */ 3846struct dmub_rb_cmd_abm_set_pwm_frac { 3847 /** 3848 * Command header. 3849 */ 3850 struct dmub_cmd_header header; 3851 3852 /** 3853 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 3854 */ 3855 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 3856}; 3857 3858/** 3859 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3860 */ 3861struct dmub_cmd_abm_init_config_data { 3862 /** 3863 * Location of indirect buffer used to pass init data to ABM. 3864 */ 3865 union dmub_addr src; 3866 3867 /** 3868 * Indirect buffer length. 3869 */ 3870 uint16_t bytes; 3871 3872 3873 /** 3874 * ABM control version. 3875 */ 3876 uint8_t version; 3877 3878 /** 3879 * Panel Control HW instance mask. 3880 * Bit 0 is Panel Control HW instance 0. 3881 * Bit 1 is Panel Control HW instance 1. 3882 */ 3883 uint8_t panel_mask; 3884 3885 /** 3886 * Explicit padding to 4 byte boundary. 3887 */ 3888 uint8_t pad[2]; 3889}; 3890 3891/** 3892 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3893 */ 3894struct dmub_rb_cmd_abm_init_config { 3895 /** 3896 * Command header. 3897 */ 3898 struct dmub_cmd_header header; 3899 3900 /** 3901 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3902 */ 3903 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3904}; 3905 3906/** 3907 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3908 */ 3909 3910struct dmub_cmd_abm_pause_data { 3911 3912 /** 3913 * Panel Control HW instance mask. 3914 * Bit 0 is Panel Control HW instance 0. 3915 * Bit 1 is Panel Control HW instance 1. 3916 */ 3917 uint8_t panel_mask; 3918 3919 /** 3920 * OTG hw instance 3921 */ 3922 uint8_t otg_inst; 3923 3924 /** 3925 * Enable or disable ABM pause 3926 */ 3927 uint8_t enable; 3928 3929 /** 3930 * Explicit padding to 4 byte boundary. 3931 */ 3932 uint8_t pad[1]; 3933}; 3934 3935/** 3936 * Definition of a DMUB_CMD__ABM_PAUSE command. 3937 */ 3938struct dmub_rb_cmd_abm_pause { 3939 /** 3940 * Command header. 3941 */ 3942 struct dmub_cmd_header header; 3943 3944 /** 3945 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 3946 */ 3947 struct dmub_cmd_abm_pause_data abm_pause_data; 3948}; 3949 3950/** 3951 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 3952 */ 3953struct dmub_rb_cmd_abm_save_restore { 3954 /** 3955 * Command header. 3956 */ 3957 struct dmub_cmd_header header; 3958 3959 /** 3960 * OTG hw instance 3961 */ 3962 uint8_t otg_inst; 3963 3964 /** 3965 * Enable or disable ABM pause 3966 */ 3967 uint8_t freeze; 3968 3969 /** 3970 * Explicit padding to 4 byte boundary. 3971 */ 3972 uint8_t debug; 3973 3974 /** 3975 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 3976 */ 3977 struct dmub_cmd_abm_init_config_data abm_init_config_data; 3978}; 3979 3980/** 3981 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 3982 */ 3983struct dmub_cmd_query_feature_caps_data { 3984 /** 3985 * DMUB feature capabilities. 3986 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 3987 */ 3988 struct dmub_feature_caps feature_caps; 3989}; 3990 3991/** 3992 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3993 */ 3994struct dmub_rb_cmd_query_feature_caps { 3995 /** 3996 * Command header. 3997 */ 3998 struct dmub_cmd_header header; 3999 /** 4000 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 4001 */ 4002 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 4003}; 4004 4005/** 4006 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4007 */ 4008struct dmub_cmd_visual_confirm_color_data { 4009 /** 4010 * DMUB visual confirm color 4011 */ 4012 struct dmub_visual_confirm_color visual_confirm_color; 4013}; 4014 4015/** 4016 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4017 */ 4018struct dmub_rb_cmd_get_visual_confirm_color { 4019 /** 4020 * Command header. 4021 */ 4022 struct dmub_cmd_header header; 4023 /** 4024 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4025 */ 4026 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 4027}; 4028 4029/** 4030 * enum dmub_cmd_panel_cntl_type - Panel control command. 4031 */ 4032enum dmub_cmd_panel_cntl_type { 4033 /** 4034 * Initializes embedded panel hardware blocks. 4035 */ 4036 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 4037 /** 4038 * Queries backlight info for the embedded panel. 4039 */ 4040 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 4041}; 4042 4043/** 4044 * struct dmub_cmd_panel_cntl_data - Panel control data. 4045 */ 4046struct dmub_cmd_panel_cntl_data { 4047 uint32_t pwrseq_inst; /**< pwrseq instance */ 4048 uint32_t current_backlight; /* in/out */ 4049 uint32_t bl_pwm_cntl; /* in/out */ 4050 uint32_t bl_pwm_period_cntl; /* in/out */ 4051 uint32_t bl_pwm_ref_div1; /* in/out */ 4052 uint8_t is_backlight_on : 1; /* in/out */ 4053 uint8_t is_powered_on : 1; /* in/out */ 4054 uint8_t padding[3]; 4055 uint32_t bl_pwm_ref_div2; /* in/out */ 4056 uint8_t reserved[4]; 4057}; 4058 4059/** 4060 * struct dmub_rb_cmd_panel_cntl - Panel control command. 4061 */ 4062struct dmub_rb_cmd_panel_cntl { 4063 struct dmub_cmd_header header; /**< header */ 4064 struct dmub_cmd_panel_cntl_data data; /**< payload */ 4065}; 4066 4067struct dmub_optc_state { 4068 uint32_t v_total_max; 4069 uint32_t v_total_min; 4070 uint32_t tg_inst; 4071}; 4072 4073struct dmub_rb_cmd_drr_update { 4074 struct dmub_cmd_header header; 4075 struct dmub_optc_state dmub_optc_state_req; 4076}; 4077 4078struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 4079 uint32_t pix_clk_100hz; 4080 uint8_t max_ramp_step; 4081 uint8_t pipes; 4082 uint8_t min_refresh_in_hz; 4083 uint8_t pipe_count; 4084 uint8_t pipe_index[4]; 4085}; 4086 4087struct dmub_cmd_fw_assisted_mclk_switch_config { 4088 uint8_t fams_enabled; 4089 uint8_t visual_confirm_enabled; 4090 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 4091 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 4092}; 4093 4094struct dmub_rb_cmd_fw_assisted_mclk_switch { 4095 struct dmub_cmd_header header; 4096 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 4097}; 4098 4099/** 4100 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4101 */ 4102struct dmub_cmd_lvtma_control_data { 4103 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 4104 uint8_t bypass_panel_control_wait; 4105 uint8_t reserved_0[2]; /**< For future use */ 4106 uint8_t pwrseq_inst; /**< LVTMA control instance */ 4107 uint8_t reserved_1[3]; /**< For future use */ 4108}; 4109 4110/** 4111 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4112 */ 4113struct dmub_rb_cmd_lvtma_control { 4114 /** 4115 * Command header. 4116 */ 4117 struct dmub_cmd_header header; 4118 /** 4119 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4120 */ 4121 struct dmub_cmd_lvtma_control_data data; 4122}; 4123 4124/** 4125 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4126 */ 4127struct dmub_rb_cmd_transmitter_query_dp_alt_data { 4128 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 4129 uint8_t is_usb; /**< is phy is usb */ 4130 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 4131 uint8_t is_dp4; /**< is dp in 4 lane */ 4132}; 4133 4134/** 4135 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4136 */ 4137struct dmub_rb_cmd_transmitter_query_dp_alt { 4138 struct dmub_cmd_header header; /**< header */ 4139 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 4140}; 4141 4142/** 4143 * Maximum number of bytes a chunk sent to DMUB for parsing 4144 */ 4145#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 4146 4147/** 4148 * Represent a chunk of CEA blocks sent to DMUB for parsing 4149 */ 4150struct dmub_cmd_send_edid_cea { 4151 uint16_t offset; /**< offset into the CEA block */ 4152 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 4153 uint16_t cea_total_length; /**< total length of the CEA block */ 4154 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 4155 uint8_t pad[3]; /**< padding and for future expansion */ 4156}; 4157 4158/** 4159 * Result of VSDB parsing from CEA block 4160 */ 4161struct dmub_cmd_edid_cea_amd_vsdb { 4162 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 4163 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 4164 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 4165 uint16_t min_frame_rate; /**< Maximum frame rate */ 4166 uint16_t max_frame_rate; /**< Minimum frame rate */ 4167}; 4168 4169/** 4170 * Result of sending a CEA chunk 4171 */ 4172struct dmub_cmd_edid_cea_ack { 4173 uint16_t offset; /**< offset of the chunk into the CEA block */ 4174 uint8_t success; /**< 1 if this sending of chunk succeeded */ 4175 uint8_t pad; /**< padding and for future expansion */ 4176}; 4177 4178/** 4179 * Specify whether the result is an ACK/NACK or the parsing has finished 4180 */ 4181enum dmub_cmd_edid_cea_reply_type { 4182 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 4183 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 4184}; 4185 4186/** 4187 * Definition of a DMUB_CMD__EDID_CEA command. 4188 */ 4189struct dmub_rb_cmd_edid_cea { 4190 struct dmub_cmd_header header; /**< Command header */ 4191 union dmub_cmd_edid_cea_data { 4192 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 4193 struct dmub_cmd_edid_cea_output { /**< output with results */ 4194 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 4195 union { 4196 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 4197 struct dmub_cmd_edid_cea_ack ack; 4198 }; 4199 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 4200 } data; /**< Command data */ 4201 4202}; 4203 4204/** 4205 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 4206 */ 4207struct dmub_cmd_cable_id_input { 4208 uint8_t phy_inst; /**< phy inst for cable id data */ 4209}; 4210 4211/** 4212 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 4213 */ 4214struct dmub_cmd_cable_id_output { 4215 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 4216 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 4217 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 4218 uint8_t RESERVED :2; /**< reserved means not defined */ 4219}; 4220 4221/** 4222 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 4223 */ 4224struct dmub_rb_cmd_get_usbc_cable_id { 4225 struct dmub_cmd_header header; /**< Command header */ 4226 /** 4227 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 4228 */ 4229 union dmub_cmd_cable_id_data { 4230 struct dmub_cmd_cable_id_input input; /**< Input */ 4231 struct dmub_cmd_cable_id_output output; /**< Output */ 4232 uint8_t output_raw; /**< Raw data output */ 4233 } data; 4234}; 4235 4236/** 4237 * Command type of a DMUB_CMD__SECURE_DISPLAY command 4238 */ 4239enum dmub_cmd_secure_display_type { 4240 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 4241 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 4242 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 4243}; 4244 4245/** 4246 * Definition of a DMUB_CMD__SECURE_DISPLAY command 4247 */ 4248struct dmub_rb_cmd_secure_display { 4249 struct dmub_cmd_header header; 4250 /** 4251 * Data passed from driver to dmub firmware. 4252 */ 4253 struct dmub_cmd_roi_info { 4254 uint16_t x_start; 4255 uint16_t x_end; 4256 uint16_t y_start; 4257 uint16_t y_end; 4258 uint8_t otg_id; 4259 uint8_t phy_id; 4260 } roi_info; 4261}; 4262 4263/** 4264 * union dmub_rb_cmd - DMUB inbox command. 4265 */ 4266union dmub_rb_cmd { 4267 /** 4268 * Elements shared with all commands. 4269 */ 4270 struct dmub_rb_cmd_common cmd_common; 4271 /** 4272 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 4273 */ 4274 struct dmub_rb_cmd_read_modify_write read_modify_write; 4275 /** 4276 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 4277 */ 4278 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 4279 /** 4280 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 4281 */ 4282 struct dmub_rb_cmd_burst_write burst_write; 4283 /** 4284 * Definition of a DMUB_CMD__REG_REG_WAIT command. 4285 */ 4286 struct dmub_rb_cmd_reg_wait reg_wait; 4287 /** 4288 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 4289 */ 4290 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 4291 /** 4292 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 4293 */ 4294 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 4295 /** 4296 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 4297 */ 4298 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 4299 /** 4300 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 4301 */ 4302 struct dmub_rb_cmd_dpphy_init dpphy_init; 4303 /** 4304 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 4305 */ 4306 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 4307 /** 4308 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 4309 */ 4310 struct dmub_rb_cmd_domain_control domain_control; 4311 /** 4312 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 4313 */ 4314 struct dmub_rb_cmd_psr_set_version psr_set_version; 4315 /** 4316 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 4317 */ 4318 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 4319 /** 4320 * Definition of a DMUB_CMD__PSR_ENABLE command. 4321 */ 4322 struct dmub_rb_cmd_psr_enable psr_enable; 4323 /** 4324 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 4325 */ 4326 struct dmub_rb_cmd_psr_set_level psr_set_level; 4327 /** 4328 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 4329 */ 4330 struct dmub_rb_cmd_psr_force_static psr_force_static; 4331 /** 4332 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 4333 */ 4334 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 4335 /** 4336 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 4337 */ 4338 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 4339 /** 4340 * Definition of a DMUB_CMD__HW_LOCK command. 4341 * Command is used by driver and FW. 4342 */ 4343 struct dmub_rb_cmd_lock_hw lock_hw; 4344 /** 4345 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 4346 */ 4347 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 4348 /** 4349 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 4350 */ 4351 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 4352 /** 4353 * Definition of a DMUB_CMD__PLAT_54186_WA command. 4354 */ 4355 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 4356 /** 4357 * Definition of a DMUB_CMD__MALL command. 4358 */ 4359 struct dmub_rb_cmd_mall mall; 4360 4361 /** 4362 * Definition of a DMUB_CMD__CAB command. 4363 */ 4364 struct dmub_rb_cmd_cab_for_ss cab; 4365 4366 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 4367 4368 /** 4369 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 4370 */ 4371 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 4372 4373 /** 4374 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 4375 */ 4376 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 4377 4378 /** 4379 * Definition of DMUB_CMD__PANEL_CNTL commands. 4380 */ 4381 struct dmub_rb_cmd_panel_cntl panel_cntl; 4382 4383 /** 4384 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4385 */ 4386 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 4387 4388 /** 4389 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4390 */ 4391 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 4392 4393 /** 4394 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4395 */ 4396 struct dmub_rb_cmd_abm_set_level abm_set_level; 4397 4398 /** 4399 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4400 */ 4401 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 4402 4403 /** 4404 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4405 */ 4406 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 4407 4408 /** 4409 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4410 */ 4411 struct dmub_rb_cmd_abm_init_config abm_init_config; 4412 4413 /** 4414 * Definition of a DMUB_CMD__ABM_PAUSE command. 4415 */ 4416 struct dmub_rb_cmd_abm_pause abm_pause; 4417 4418 /** 4419 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 4420 */ 4421 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 4422 4423 /** 4424 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 4425 */ 4426 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 4427 4428 /** 4429 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 4430 */ 4431 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 4432 4433 /** 4434 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 4435 */ 4436 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 4437 4438 /** 4439 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 4440 */ 4441 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 4442 struct dmub_rb_cmd_drr_update drr_update; 4443 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 4444 4445 /** 4446 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 4447 */ 4448 struct dmub_rb_cmd_lvtma_control lvtma_control; 4449 /** 4450 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 4451 */ 4452 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 4453 /** 4454 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 4455 */ 4456 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 4457 /** 4458 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 4459 */ 4460 struct dmub_rb_cmd_set_config_access set_config_access; 4461 /** 4462 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 4463 */ 4464 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 4465 /** 4466 * Definition of a DMUB_CMD__EDID_CEA command. 4467 */ 4468 struct dmub_rb_cmd_edid_cea edid_cea; 4469 /** 4470 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 4471 */ 4472 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 4473 4474 /** 4475 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 4476 */ 4477 struct dmub_rb_cmd_query_hpd_state query_hpd; 4478 /** 4479 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 4480 */ 4481 struct dmub_rb_cmd_secure_display secure_display; 4482 4483 /** 4484 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 4485 */ 4486 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 4487 /** 4488 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 4489 */ 4490 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 4491 /* 4492 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4493 */ 4494 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 4495 /** 4496 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4497 */ 4498 struct dmub_rb_cmd_replay_enable replay_enable; 4499 /** 4500 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4501 */ 4502 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 4503 /** 4504 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4505 */ 4506 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 4507 /** 4508 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4509 */ 4510 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 4511 4512 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 4513 /** 4514 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4515 */ 4516 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 4517 /** 4518 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4519 */ 4520 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 4521}; 4522 4523/** 4524 * union dmub_rb_out_cmd - Outbox command 4525 */ 4526union dmub_rb_out_cmd { 4527 /** 4528 * Parameters common to every command. 4529 */ 4530 struct dmub_rb_cmd_common cmd_common; 4531 /** 4532 * AUX reply command. 4533 */ 4534 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 4535 /** 4536 * HPD notify command. 4537 */ 4538 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 4539 /** 4540 * SET_CONFIG reply command. 4541 */ 4542 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 4543 /** 4544 * DPIA notification command. 4545 */ 4546 struct dmub_rb_cmd_dpia_notification dpia_notification; 4547}; 4548#pragma pack(pop) 4549 4550 4551//============================================================================== 4552//</DMUB_CMD>=================================================================== 4553//============================================================================== 4554//< DMUB_RB>==================================================================== 4555//============================================================================== 4556 4557#if defined(__cplusplus) 4558extern "C" { 4559#endif 4560 4561/** 4562 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 4563 */ 4564struct dmub_rb_init_params { 4565 void *ctx; /**< Caller provided context pointer */ 4566 void *base_address; /**< CPU base address for ring's data */ 4567 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4568 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 4569 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 4570}; 4571 4572/** 4573 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 4574 */ 4575struct dmub_rb { 4576 void *base_address; /**< CPU address for the ring's data */ 4577 uint32_t rptr; /**< Read pointer for consumer in bytes */ 4578 uint32_t wrpt; /**< Write pointer for producer in bytes */ 4579 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 4580 4581 void *ctx; /**< Caller provided context pointer */ 4582 void *dmub; /**< Pointer to the DMUB interface */ 4583}; 4584 4585/** 4586 * @brief Checks if the ringbuffer is empty. 4587 * 4588 * @param rb DMUB Ringbuffer 4589 * @return true if empty 4590 * @return false otherwise 4591 */ 4592static inline bool dmub_rb_empty(struct dmub_rb *rb) 4593{ 4594 return (rb->wrpt == rb->rptr); 4595} 4596 4597/** 4598 * @brief Checks if the ringbuffer is full 4599 * 4600 * @param rb DMUB Ringbuffer 4601 * @return true if full 4602 * @return false otherwise 4603 */ 4604static inline bool dmub_rb_full(struct dmub_rb *rb) 4605{ 4606 uint32_t data_count; 4607 4608 if (rb->wrpt >= rb->rptr) 4609 data_count = rb->wrpt - rb->rptr; 4610 else 4611 data_count = rb->capacity - (rb->rptr - rb->wrpt); 4612 4613 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 4614} 4615 4616/** 4617 * @brief Pushes a command into the ringbuffer 4618 * 4619 * @param rb DMUB ringbuffer 4620 * @param cmd The command to push 4621 * @return true if the ringbuffer was not full 4622 * @return false otherwise 4623 */ 4624static inline bool dmub_rb_push_front(struct dmub_rb *rb, 4625 const union dmub_rb_cmd *cmd) 4626{ 4627 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 4628 const uint64_t *src = (const uint64_t *)cmd; 4629 uint8_t i; 4630 4631 if (dmub_rb_full(rb)) 4632 return false; 4633 4634 // copying data 4635 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4636 *dst++ = *src++; 4637 4638 rb->wrpt += DMUB_RB_CMD_SIZE; 4639 4640 if (rb->wrpt >= rb->capacity) 4641 rb->wrpt %= rb->capacity; 4642 4643 return true; 4644} 4645 4646/** 4647 * @brief Pushes a command into the DMUB outbox ringbuffer 4648 * 4649 * @param rb DMUB outbox ringbuffer 4650 * @param cmd Outbox command 4651 * @return true if not full 4652 * @return false otherwise 4653 */ 4654static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 4655 const union dmub_rb_out_cmd *cmd) 4656{ 4657 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 4658 const uint8_t *src = (const uint8_t *)cmd; 4659 4660 if (dmub_rb_full(rb)) 4661 return false; 4662 4663 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 4664 4665 rb->wrpt += DMUB_RB_CMD_SIZE; 4666 4667 if (rb->wrpt >= rb->capacity) 4668 rb->wrpt %= rb->capacity; 4669 4670 return true; 4671} 4672 4673/** 4674 * @brief Returns the next unprocessed command in the ringbuffer. 4675 * 4676 * @param rb DMUB ringbuffer 4677 * @param cmd The command to return 4678 * @return true if not empty 4679 * @return false otherwise 4680 */ 4681static inline bool dmub_rb_front(struct dmub_rb *rb, 4682 union dmub_rb_cmd **cmd) 4683{ 4684 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 4685 4686 if (dmub_rb_empty(rb)) 4687 return false; 4688 4689 *cmd = (union dmub_rb_cmd *)rb_cmd; 4690 4691 return true; 4692} 4693 4694/** 4695 * @brief Determines the next ringbuffer offset. 4696 * 4697 * @param rb DMUB inbox ringbuffer 4698 * @param num_cmds Number of commands 4699 * @param next_rptr The next offset in the ringbuffer 4700 */ 4701static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 4702 uint32_t num_cmds, 4703 uint32_t *next_rptr) 4704{ 4705 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 4706 4707 if (*next_rptr >= rb->capacity) 4708 *next_rptr %= rb->capacity; 4709} 4710 4711/** 4712 * @brief Returns a pointer to a command in the inbox. 4713 * 4714 * @param rb DMUB inbox ringbuffer 4715 * @param cmd The inbox command to return 4716 * @param rptr The ringbuffer offset 4717 * @return true if not empty 4718 * @return false otherwise 4719 */ 4720static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 4721 union dmub_rb_cmd **cmd, 4722 uint32_t rptr) 4723{ 4724 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 4725 4726 if (dmub_rb_empty(rb)) 4727 return false; 4728 4729 *cmd = (union dmub_rb_cmd *)rb_cmd; 4730 4731 return true; 4732} 4733 4734/** 4735 * @brief Returns the next unprocessed command in the outbox. 4736 * 4737 * @param rb DMUB outbox ringbuffer 4738 * @param cmd The outbox command to return 4739 * @return true if not empty 4740 * @return false otherwise 4741 */ 4742static inline bool dmub_rb_out_front(struct dmub_rb *rb, 4743 union dmub_rb_out_cmd *cmd) 4744{ 4745 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 4746 uint64_t *dst = (uint64_t *)cmd; 4747 uint8_t i; 4748 4749 if (dmub_rb_empty(rb)) 4750 return false; 4751 4752 // copying data 4753 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4754 *dst++ = *src++; 4755 4756 return true; 4757} 4758 4759/** 4760 * @brief Removes the front entry in the ringbuffer. 4761 * 4762 * @param rb DMUB ringbuffer 4763 * @return true if the command was removed 4764 * @return false if there were no commands 4765 */ 4766static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 4767{ 4768 if (dmub_rb_empty(rb)) 4769 return false; 4770 4771 rb->rptr += DMUB_RB_CMD_SIZE; 4772 4773 if (rb->rptr >= rb->capacity) 4774 rb->rptr %= rb->capacity; 4775 4776 return true; 4777} 4778 4779/** 4780 * @brief Flushes commands in the ringbuffer to framebuffer memory. 4781 * 4782 * Avoids a race condition where DMCUB accesses memory while 4783 * there are still writes in flight to framebuffer. 4784 * 4785 * @param rb DMUB ringbuffer 4786 */ 4787static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 4788{ 4789 uint32_t rptr = rb->rptr; 4790 uint32_t wptr = rb->wrpt; 4791 4792 while (rptr != wptr) { 4793 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 4794 uint8_t i; 4795 4796 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 4797 (void)READ_ONCE(*data++); 4798 4799 rptr += DMUB_RB_CMD_SIZE; 4800 if (rptr >= rb->capacity) 4801 rptr %= rb->capacity; 4802 } 4803} 4804 4805/** 4806 * @brief Initializes a DMCUB ringbuffer 4807 * 4808 * @param rb DMUB ringbuffer 4809 * @param init_params initial configuration for the ringbuffer 4810 */ 4811static inline void dmub_rb_init(struct dmub_rb *rb, 4812 struct dmub_rb_init_params *init_params) 4813{ 4814 rb->base_address = init_params->base_address; 4815 rb->capacity = init_params->capacity; 4816 rb->rptr = init_params->read_ptr; 4817 rb->wrpt = init_params->write_ptr; 4818} 4819 4820/** 4821 * @brief Copies output data from in/out commands into the given command. 4822 * 4823 * @param rb DMUB ringbuffer 4824 * @param cmd Command to copy data into 4825 */ 4826static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 4827 union dmub_rb_cmd *cmd) 4828{ 4829 // Copy rb entry back into command 4830 uint8_t *rd_ptr = (rb->rptr == 0) ? 4831 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 4832 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 4833 4834 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 4835} 4836 4837#if defined(__cplusplus) 4838} 4839#endif 4840 4841//============================================================================== 4842//</DMUB_RB>==================================================================== 4843//============================================================================== 4844#endif /* _DMUB_CMD_H_ */ 4845