Searched refs:mcr (Results 26 - 50 of 168) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/drivers/pci/
H A Dfixups-se7751.c39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr; local
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/
H A Dproc-sa1100.S44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
58 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
62 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
112 mcr p1
[all...]
H A Dproc-arm740.S42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
55 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
63 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
65 mcr p15, 0, r0, c6, c3 @ disable area 3~7
66 mcr p15, 0, r0, c6, c4
67 mcr p15, 0, r0, c6, c5
68 mcr p15, 0, r0, c6, c6
69 mcr p15, 0, r0, c6, c7
72 mcr p1
[all...]
H A Dproc-xsc3.S72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
138 mcr p14, 0, r0, c7, c0, 0 @ go to idle
187 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
214 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
219 mcr p1
[all...]
H A Dcache-v4wb.S68 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
85 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
107 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
108 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
154 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
155 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
160 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
161 mcr p15, 0, ip, c7, c10, 4 @ drain WB
182 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
186 mcr p1
[all...]
H A Dproc-feroceon.S81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
148 2: mcr p1
[all...]
H A Dcache-v4wt.S62 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
80 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
113 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
147 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-arm720.S60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
106 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
108 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
121 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
123 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
149 mcr p1
[all...]
H A Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
120 mcr p15, 0, r1, c1, c0, 1
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
148 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
149 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
155 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p1
[all...]
H A Dcache-v4.S33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
107 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
H A Dcache-v7.S45 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
64 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
75 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
98 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable
100 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
169 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
171 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
178 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable
180 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
212 mcr p1
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c64xx/
H A Dsleep.S118 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
119 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
120 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
121 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
122 @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
123 @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
128 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
129 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
130 mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
131 mcr p1
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/minidlna/zlib-1.2.8/contrib/minizip/
H A Dmake_vms.com20 $ mcr []minizip test minizip_info.txt
21 $ mcr []miniunz -l test.zip
23 $ mcr []miniunz test.zip
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/openssl-1.0.2h/test/
H A Dtestgen.com30 $ mcr 'exe_dir'openssl no-rsa
46 $ mcr 'exe_dir'openssl req -config test.cnf 'req_new' -out testreq.pem
53 $ mcr 'exe_dir'openssl req -config test.cnf -verify -in testreq.pem -noout
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/timemachine/openssl-0.9.8e/test/
H A Dtestgen.com26 $ mcr 'exe_dir'openssl no-rsa
40 $ mcr 'exe_dir'openssl req -config test.cnf 'req_new' -out testreq.pem
47 $ mcr 'exe_dir'openssl req -config test.cnf -verify -in testreq.pem -noout
H A Dtestss.com8 $ reqcmd := mcr 'exe_dir'openssl req
9 $ x509cmd := mcr 'exe_dir'openssl x509 'digest'
10 $ verifycmd := mcr 'exe_dir'openssl verify
29 $ mcr 'exe_dir'openssl no-rsa
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/openssl/test/
H A Dtestgen.com30 $ mcr 'exe_dir'openssl no-rsa
46 $ mcr 'exe_dir'openssl req -config test.cnf 'req_new' -out testreq.pem
53 $ mcr 'exe_dir'openssl req -config test.cnf -verify -in testreq.pem -noout
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/zlib-1.2.7/contrib/minizip/
H A Dmake_vms.com20 $ mcr []minizip test minizip_info.txt
21 $ mcr []miniunz -l test.zip
23 $ mcr []miniunz test.zip
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/mtd/nand/
H A Dtxx9ndfmc.c120 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local
122 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
125 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
158 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local
160 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
161 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
162 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
164 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
166 mcr &= ~TXX9_NDFMCR_CS_MASK;
167 mcr |
194 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local
232 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/boot/compressed/
H A Dhead.S28 mcr p14, 0, \ch, c0, c5, 0
36 mcr p14, 0, \ch, c0, c5, 0
42 mcr p14, 0, \ch, c8, c0, 0
48 mcr p14, 0, \ch, c1, c0, 0
358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
362 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
363 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
367 mcr p1
[all...]
H A Dhead-xscale.S26 mcr p15, 0, r0, c7, c10, 4 @ drain WB
27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
33 mcr p15, 0, r0, c1, c0, 0
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dsleep24xx.S52 mov r0, #0 @ clear for mcr setup
53 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
61 mov r3, #0x0 @ clear for mcr call
62 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
70 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-sa1100/
H A Dsleep.S60 mcr p15, 0, r1, c15, c2, 2
170 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
171 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache
172 mcr p15, 0, r1, c9, c0, 0 @ invalidate RB
173 mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB
175 mcr p15, 0, r4, c3, c0, 0 @ domain ID
176 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
177 mcr p15, 0, r6, c13, c0, 0 @ PID
182 mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, caches, etc.
194 mcr p1
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pxa/
H A Dsleep.S92 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
111 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
112 mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
113 mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
114 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
116 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
117 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
118 mcr p15, 0, r5, c13, c0, 0 @ PID
119 mcr p15, 0, r6, c3, c0, 0 @ domain ID
120 mcr p1
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/boards/mach-hp6xx/
H A Dpm.c42 u16 frqcr, mcr; local
65 mcr = __raw_readw(MCR);
66 __raw_writew(mcr & ~MCR_RFSH, MCR);
77 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);

Completed in 152 milliseconds

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