1/* 2 * TXx9 NAND flash memory controller driver 3 * Based on RBTX49xx patch from CELF patch archive. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * (C) Copyright TOSHIBA CORPORATION 2004-2007 10 * All Rights Reserved. 11 */ 12#include <linux/init.h> 13#include <linux/slab.h> 14#include <linux/module.h> 15#include <linux/platform_device.h> 16#include <linux/delay.h> 17#include <linux/mtd/mtd.h> 18#include <linux/mtd/nand.h> 19#include <linux/mtd/nand_ecc.h> 20#include <linux/mtd/partitions.h> 21#include <linux/io.h> 22#include <asm/txx9/ndfmc.h> 23 24/* TXX9 NDFMC Registers */ 25#define TXX9_NDFDTR 0x00 26#define TXX9_NDFMCR 0x04 27#define TXX9_NDFSR 0x08 28#define TXX9_NDFISR 0x0c 29#define TXX9_NDFIMR 0x10 30#define TXX9_NDFSPR 0x14 31#define TXX9_NDFRSTR 0x18 /* not TX4939 */ 32 33/* NDFMCR : NDFMC Mode Control */ 34#define TXX9_NDFMCR_WE 0x80 35#define TXX9_NDFMCR_ECC_ALL 0x60 36#define TXX9_NDFMCR_ECC_RESET 0x60 37#define TXX9_NDFMCR_ECC_READ 0x40 38#define TXX9_NDFMCR_ECC_ON 0x20 39#define TXX9_NDFMCR_ECC_OFF 0x00 40#define TXX9_NDFMCR_CE 0x10 41#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */ 42#define TXX9_NDFMCR_ALE 0x02 43#define TXX9_NDFMCR_CLE 0x01 44/* TX4939 only */ 45#define TXX9_NDFMCR_X16 0x0400 46#define TXX9_NDFMCR_DMAREQ_MASK 0x0300 47#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000 48#define TXX9_NDFMCR_DMAREQ_128 0x0100 49#define TXX9_NDFMCR_DMAREQ_256 0x0200 50#define TXX9_NDFMCR_DMAREQ_512 0x0300 51#define TXX9_NDFMCR_CS_MASK 0x0c 52#define TXX9_NDFMCR_CS(ch) ((ch) << 2) 53 54/* NDFMCR : NDFMC Status */ 55#define TXX9_NDFSR_BUSY 0x80 56/* TX4939 only */ 57#define TXX9_NDFSR_DMARUN 0x40 58 59/* NDFMCR : NDFMC Reset */ 60#define TXX9_NDFRSTR_RST 0x01 61 62struct txx9ndfmc_priv { 63 struct platform_device *dev; 64 struct nand_chip chip; 65 struct mtd_info mtd; 66 int cs; 67 const char *mtdname; 68}; 69 70#define MAX_TXX9NDFMC_DEV 4 71struct txx9ndfmc_drvdata { 72 struct mtd_info *mtds[MAX_TXX9NDFMC_DEV]; 73 void __iomem *base; 74 unsigned char hold; /* in gbusclock */ 75 unsigned char spw; /* in gbusclock */ 76 struct nand_hw_control hw_control; 77#ifdef CONFIG_MTD_PARTITIONS 78 struct mtd_partition *parts[MAX_TXX9NDFMC_DEV]; 79#endif 80}; 81 82static struct platform_device *mtd_to_platdev(struct mtd_info *mtd) 83{ 84 struct nand_chip *chip = mtd->priv; 85 struct txx9ndfmc_priv *txx9_priv = chip->priv; 86 return txx9_priv->dev; 87} 88 89static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) 90{ 91 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 92 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; 93 94 return drvdata->base + (reg << plat->shift); 95} 96 97static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) 98{ 99 return __raw_readl(ndregaddr(dev, reg)); 100} 101 102static void txx9ndfmc_write(struct platform_device *dev, 103 u32 val, unsigned int reg) 104{ 105 __raw_writel(val, ndregaddr(dev, reg)); 106} 107 108static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd) 109{ 110 struct platform_device *dev = mtd_to_platdev(mtd); 111 112 return txx9ndfmc_read(dev, TXX9_NDFDTR); 113} 114 115static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, 116 int len) 117{ 118 struct platform_device *dev = mtd_to_platdev(mtd); 119 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 120 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 121 122 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); 123 while (len--) 124 __raw_writel(*buf++, ndfdtr); 125 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 126} 127 128static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 129{ 130 struct platform_device *dev = mtd_to_platdev(mtd); 131 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 132 133 while (len--) 134 *buf++ = __raw_readl(ndfdtr); 135} 136 137static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, 138 int len) 139{ 140 struct platform_device *dev = mtd_to_platdev(mtd); 141 void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); 142 143 while (len--) 144 if (*buf++ != (uint8_t)__raw_readl(ndfdtr)) 145 return -EFAULT; 146 return 0; 147} 148 149static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd, 150 unsigned int ctrl) 151{ 152 struct nand_chip *chip = mtd->priv; 153 struct txx9ndfmc_priv *txx9_priv = chip->priv; 154 struct platform_device *dev = txx9_priv->dev; 155 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; 156 157 if (ctrl & NAND_CTRL_CHANGE) { 158 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 159 160 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); 161 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; 162 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; 163 /* TXX9_NDFMCR_CE bit is 0:high 1:low */ 164 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; 165 if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) { 166 mcr &= ~TXX9_NDFMCR_CS_MASK; 167 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); 168 } 169 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 170 } 171 if (cmd != NAND_CMD_NONE) 172 txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR); 173 if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) { 174 /* dummy write to update external latch */ 175 if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE) 176 txx9ndfmc_write(dev, 0, TXX9_NDFDTR); 177 } 178 mmiowb(); 179} 180 181static int txx9ndfmc_dev_ready(struct mtd_info *mtd) 182{ 183 struct platform_device *dev = mtd_to_platdev(mtd); 184 185 return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY); 186} 187 188static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, 189 uint8_t *ecc_code) 190{ 191 struct platform_device *dev = mtd_to_platdev(mtd); 192 struct nand_chip *chip = mtd->priv; 193 int eccbytes; 194 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 195 196 mcr &= ~TXX9_NDFMCR_ECC_ALL; 197 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 198 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); 199 for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) { 200 ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR); 201 ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR); 202 ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR); 203 ecc_code += 3; 204 } 205 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 206 return 0; 207} 208 209static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf, 210 unsigned char *read_ecc, unsigned char *calc_ecc) 211{ 212 struct nand_chip *chip = mtd->priv; 213 int eccsize; 214 int corrected = 0; 215 int stat; 216 217 for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) { 218 stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256); 219 if (stat < 0) 220 return stat; 221 corrected += stat; 222 buf += 256; 223 read_ecc += 3; 224 calc_ecc += 3; 225 } 226 return corrected; 227} 228 229static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode) 230{ 231 struct platform_device *dev = mtd_to_platdev(mtd); 232 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); 233 234 mcr &= ~TXX9_NDFMCR_ECC_ALL; 235 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); 236 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); 237 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); 238} 239 240static void txx9ndfmc_initialize(struct platform_device *dev) 241{ 242 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; 243 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 244 int tmout = 100; 245 246 if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR) 247 ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */ 248 else { 249 /* reset NDFMC */ 250 txx9ndfmc_write(dev, 251 txx9ndfmc_read(dev, TXX9_NDFRSTR) | 252 TXX9_NDFRSTR_RST, 253 TXX9_NDFRSTR); 254 while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) { 255 if (--tmout == 0) { 256 dev_err(&dev->dev, "reset failed.\n"); 257 break; 258 } 259 udelay(1); 260 } 261 } 262 /* setup Hold Time, Strobe Pulse Width */ 263 txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR); 264 txx9ndfmc_write(dev, 265 (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ? 266 TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR); 267} 268 269#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \ 270 DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000) 271 272static int txx9ndfmc_nand_scan(struct mtd_info *mtd) 273{ 274 struct nand_chip *chip = mtd->priv; 275 int ret; 276 277 ret = nand_scan_ident(mtd, 1, NULL); 278 if (!ret) { 279 if (mtd->writesize >= 512) { 280 chip->ecc.size = mtd->writesize; 281 chip->ecc.bytes = 3 * (mtd->writesize / 256); 282 } 283 ret = nand_scan_tail(mtd); 284 } 285 return ret; 286} 287 288static int __init txx9ndfmc_probe(struct platform_device *dev) 289{ 290 struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; 291#ifdef CONFIG_MTD_PARTITIONS 292 static const char *probes[] = { "cmdlinepart", NULL }; 293#endif 294 int hold, spw; 295 int i; 296 struct txx9ndfmc_drvdata *drvdata; 297 unsigned long gbusclk = plat->gbus_clock; 298 struct resource *res; 299 300 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 301 if (!res) 302 return -ENODEV; 303 drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); 304 if (!drvdata) 305 return -ENOMEM; 306 if (!devm_request_mem_region(&dev->dev, res->start, 307 resource_size(res), dev_name(&dev->dev))) 308 return -EBUSY; 309 drvdata->base = devm_ioremap(&dev->dev, res->start, 310 resource_size(res)); 311 if (!drvdata->base) 312 return -EBUSY; 313 314 hold = plat->hold ?: 20; /* tDH */ 315 spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */ 316 317 hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold); 318 spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw); 319 if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) 320 hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */ 321 spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */ 322 hold = clamp(hold, 1, 15); 323 drvdata->hold = hold; 324 spw = clamp(spw, 1, 15); 325 drvdata->spw = spw; 326 dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", 327 (gbusclk + 500000) / 1000000, hold, spw); 328 329 spin_lock_init(&drvdata->hw_control.lock); 330 init_waitqueue_head(&drvdata->hw_control.wq); 331 332 platform_set_drvdata(dev, drvdata); 333 txx9ndfmc_initialize(dev); 334 335 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 336 struct txx9ndfmc_priv *txx9_priv; 337 struct nand_chip *chip; 338 struct mtd_info *mtd; 339#ifdef CONFIG_MTD_PARTITIONS 340 int nr_parts; 341#endif 342 343 if (!(plat->ch_mask & (1 << i))) 344 continue; 345 txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), 346 GFP_KERNEL); 347 if (!txx9_priv) { 348 dev_err(&dev->dev, "Unable to allocate " 349 "TXx9 NDFMC MTD device structure.\n"); 350 continue; 351 } 352 chip = &txx9_priv->chip; 353 mtd = &txx9_priv->mtd; 354 mtd->owner = THIS_MODULE; 355 356 mtd->priv = chip; 357 358 chip->read_byte = txx9ndfmc_read_byte; 359 chip->read_buf = txx9ndfmc_read_buf; 360 chip->write_buf = txx9ndfmc_write_buf; 361 chip->verify_buf = txx9ndfmc_verify_buf; 362 chip->cmd_ctrl = txx9ndfmc_cmd_ctrl; 363 chip->dev_ready = txx9ndfmc_dev_ready; 364 chip->ecc.calculate = txx9ndfmc_calculate_ecc; 365 chip->ecc.correct = txx9ndfmc_correct_data; 366 chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 367 chip->ecc.mode = NAND_ECC_HW; 368 /* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */ 369 chip->ecc.size = 256; 370 chip->ecc.bytes = 3; 371 chip->chip_delay = 100; 372 chip->controller = &drvdata->hw_control; 373 374 chip->priv = txx9_priv; 375 txx9_priv->dev = dev; 376 377 if (plat->ch_mask != 1) { 378 txx9_priv->cs = i; 379 txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u", 380 dev_name(&dev->dev), i); 381 } else { 382 txx9_priv->cs = -1; 383 txx9_priv->mtdname = kstrdup(dev_name(&dev->dev), 384 GFP_KERNEL); 385 } 386 if (!txx9_priv->mtdname) { 387 kfree(txx9_priv); 388 dev_err(&dev->dev, "Unable to allocate MTD name.\n"); 389 continue; 390 } 391 if (plat->wide_mask & (1 << i)) 392 chip->options |= NAND_BUSWIDTH_16; 393 394 if (txx9ndfmc_nand_scan(mtd)) { 395 kfree(txx9_priv->mtdname); 396 kfree(txx9_priv); 397 continue; 398 } 399 mtd->name = txx9_priv->mtdname; 400 401#ifdef CONFIG_MTD_PARTITIONS 402 nr_parts = parse_mtd_partitions(mtd, probes, 403 &drvdata->parts[i], 0); 404 if (nr_parts > 0) 405 add_mtd_partitions(mtd, drvdata->parts[i], nr_parts); 406#endif 407 add_mtd_device(mtd); 408 drvdata->mtds[i] = mtd; 409 } 410 411 return 0; 412} 413 414static int __exit txx9ndfmc_remove(struct platform_device *dev) 415{ 416 struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); 417 int i; 418 419 platform_set_drvdata(dev, NULL); 420 if (!drvdata) 421 return 0; 422 for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { 423 struct mtd_info *mtd = drvdata->mtds[i]; 424 struct nand_chip *chip; 425 struct txx9ndfmc_priv *txx9_priv; 426 427 if (!mtd) 428 continue; 429 chip = mtd->priv; 430 txx9_priv = chip->priv; 431 432 nand_release(mtd); 433#ifdef CONFIG_MTD_PARTITIONS 434 kfree(drvdata->parts[i]); 435#endif 436 kfree(txx9_priv->mtdname); 437 kfree(txx9_priv); 438 } 439 return 0; 440} 441 442#ifdef CONFIG_PM 443static int txx9ndfmc_resume(struct platform_device *dev) 444{ 445 if (platform_get_drvdata(dev)) 446 txx9ndfmc_initialize(dev); 447 return 0; 448} 449#else 450#define txx9ndfmc_resume NULL 451#endif 452 453static struct platform_driver txx9ndfmc_driver = { 454 .remove = __exit_p(txx9ndfmc_remove), 455 .resume = txx9ndfmc_resume, 456 .driver = { 457 .name = "txx9ndfmc", 458 .owner = THIS_MODULE, 459 }, 460}; 461 462static int __init txx9ndfmc_init(void) 463{ 464 return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe); 465} 466 467static void __exit txx9ndfmc_exit(void) 468{ 469 platform_driver_unregister(&txx9ndfmc_driver); 470} 471 472module_init(txx9ndfmc_init); 473module_exit(txx9ndfmc_exit); 474 475MODULE_LICENSE("GPL"); 476MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver"); 477MODULE_ALIAS("platform:txx9ndfmc"); 478