Lines Matching refs:mcr
92 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
111 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
112 mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
113 mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
114 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
116 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
117 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
118 mcr p15, 0, r5, c13, c0, 0 @ PID
119 mcr p15, 0, r6, c3, c0, 0 @ domain ID
120 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
121 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
274 mcr p14, 0, r0, c6, c0, 0
288 mcr p14, 0, r0, c6, c0, 0
312 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
339 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
340 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
342 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
343 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
344 mcr p15, 0, r5, c13, c0, 0 @ PID
345 mcr p15, 0, r6, c3, c0, 0 @ domain ID
346 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
347 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
352 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
354 @ Let us ensure we jump to resume_after_mmu only when the mcr above