1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/linkage.h> 12 13/* 14 * Debugging stuff 15 * 16 * Note that these macros must not contain any code which is not 17 * 100% relocatable. Any attempt to do so will result in a crash. 18 * Please select one of the following when turning on debugging. 19 */ 20#ifdef DEBUG 21 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb, tmp 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm 30#elif defined(CONFIG_CPU_V7) 31 .macro loadsp, rb, tmp 32 .endm 33 .macro writeb, ch, rb 34wait: mrc p14, 0, pc, c0, c1, 0 35 bcs wait 36 mcr p14, 0, \ch, c0, c5, 0 37 .endm 38#elif defined(CONFIG_CPU_XSCALE) 39 .macro loadsp, rb, tmp 40 .endm 41 .macro writeb, ch, rb 42 mcr p14, 0, \ch, c8, c0, 0 43 .endm 44#else 45 .macro loadsp, rb, tmp 46 .endm 47 .macro writeb, ch, rb 48 mcr p14, 0, \ch, c1, c0, 0 49 .endm 50#endif 51 52#else 53 54#include <mach/debug-macro.S> 55 56 .macro writeb, ch, rb 57 senduart \ch, \rb 58 .endm 59 60#if defined(CONFIG_ARCH_SA1100) 61 .macro loadsp, rb, tmp 62 mov \rb, #0x80000000 @ physical base address 63#ifdef CONFIG_DEBUG_LL_SER3 64 add \rb, \rb, #0x00050000 @ Ser3 65#else 66 add \rb, \rb, #0x00010000 @ Ser1 67#endif 68 .endm 69#elif defined(CONFIG_ARCH_S3C2410) 70 .macro loadsp, rb, tmp 71 mov \rb, #0x50000000 72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 73 .endm 74#else 75 .macro loadsp, rb, tmp 76 addruart \rb, \tmp 77 .endm 78#endif 79#endif 80#endif 81 82 .macro kputc,val 83 mov r0, \val 84 bl putc 85 .endm 86 87 .macro kphex,val,len 88 mov r0, \val 89 mov r1, #\len 90 bl phex 91 .endm 92 93 .macro debug_reloc_start 94#ifdef DEBUG 95 kputc #'\n' 96 kphex r6, 8 /* processor id */ 97 kputc #':' 98 kphex r7, 8 /* architecture id */ 99#ifdef CONFIG_CPU_CP15 100 kputc #':' 101 mrc p15, 0, r0, c1, c0 102 kphex r0, 8 /* control reg */ 103#endif 104 kputc #'\n' 105 kphex r5, 8 /* decompressed kernel start */ 106 kputc #'-' 107 kphex r9, 8 /* decompressed kernel end */ 108 kputc #'>' 109 kphex r4, 8 /* kernel execution address */ 110 kputc #'\n' 111#endif 112 .endm 113 114 .macro debug_reloc_end 115#ifdef DEBUG 116 kphex r5, 8 /* end of kernel */ 117 kputc #'\n' 118 mov r0, r4 119 bl memdump /* dump 256 bytes at start of kernel */ 120#endif 121 .endm 122 123 .section ".start", #alloc, #execinstr 124/* 125 * sort out different calling conventions 126 */ 127 .align 128start: 129 .type start,#function 130 .rept 8 131 mov r0, r0 132 .endr 133 134 b 1f 135 .word 0x016f2818 @ Magic numbers to help the loader 136 .word start @ absolute load/run zImage address 137 .word _edata @ zImage end address 1381: mov r7, r1 @ save architecture ID 139 mov r8, r2 @ save atags pointer 140 141#ifndef __ARM_ARCH_2__ 142 /* 143 * Booting from Angel - need to enter SVC mode and disable 144 * FIQs/IRQs (numeric definitions from angel arm.h source). 145 * We only do this if we were in user mode on entry. 146 */ 147 mrs r2, cpsr @ get current mode 148 tst r2, #3 @ not user? 149 bne not_angel 150 mov r0, #0x17 @ angel_SWIreason_EnterSVC 151 ARM( swi 0x123456 ) @ angel_SWI_ARM 152 THUMB( svc 0xab ) @ angel_SWI_THUMB 153not_angel: 154 mrs r2, cpsr @ turn off interrupts to 155 orr r2, r2, #0xc0 @ prevent angel from running 156 msr cpsr_c, r2 157#else 158 teqp pc, #0x0c000003 @ turn off interrupts 159#endif 160 161 /* 162 * Note that some cache flushing and other stuff may 163 * be needed here - is there an Angel SWI call for this? 164 */ 165 166 /* 167 * some architecture specific code can be inserted 168 * by the linker here, but it should preserve r7, r8, and r9. 169 */ 170 171 .text 172 adr r0, LC0 173 ldmia r0, {r1, r2, r3, r5, r6, r11, ip} 174 ldr sp, [r0, #28] 175#ifdef CONFIG_AUTO_ZRELADDR 176 @ determine final kernel image address 177 and r4, pc, #0xf8000000 178 add r4, r4, #TEXT_OFFSET 179#else 180 ldr r4, =zreladdr 181#endif 182 subs r0, r0, r1 @ calculate the delta offset 183 184 @ if delta is zero, we are 185 beq not_relocated @ running at the address we 186 @ were linked at. 187 188 /* 189 * We're running at a different address. We need to fix 190 * up various pointers: 191 * r5 - zImage base address (_start) 192 * r6 - size of decompressed image 193 * r11 - GOT start 194 * ip - GOT end 195 */ 196 add r5, r5, r0 197 add r11, r11, r0 198 add ip, ip, r0 199 200#ifndef CONFIG_ZBOOT_ROM 201 /* 202 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, 203 * we need to fix up pointers into the BSS region. 204 * r2 - BSS start 205 * r3 - BSS end 206 * sp - stack pointer 207 */ 208 add r2, r2, r0 209 add r3, r3, r0 210 add sp, sp, r0 211 212 /* 213 * Relocate all entries in the GOT table. 214 */ 2151: ldr r1, [r11, #0] @ relocate entries in the GOT 216 add r1, r1, r0 @ table. This fixes up the 217 str r1, [r11], #4 @ C references. 218 cmp r11, ip 219 blo 1b 220#else 221 222 /* 223 * Relocate entries in the GOT table. We only relocate 224 * the entries that are outside the (relocated) BSS region. 225 */ 2261: ldr r1, [r11, #0] @ relocate entries in the GOT 227 cmp r1, r2 @ entry < bss_start || 228 cmphs r3, r1 @ _end < entry 229 addlo r1, r1, r0 @ table. This fixes up the 230 str r1, [r11], #4 @ C references. 231 cmp r11, ip 232 blo 1b 233#endif 234 235not_relocated: mov r0, #0 2361: str r0, [r2], #4 @ clear bss 237 str r0, [r2], #4 238 str r0, [r2], #4 239 str r0, [r2], #4 240 cmp r2, r3 241 blo 1b 242 243 /* 244 * The C runtime environment should now be setup 245 * sufficiently. Turn the cache on, set up some 246 * pointers, and start decompressing. 247 */ 248 bl cache_on 249 250 mov r1, sp @ malloc space above stack 251 add r2, sp, #0x10000 @ 64k max 252 253/* 254 * Check to see if we will overwrite ourselves. 255 * r4 = final kernel address 256 * r5 = start of this image 257 * r6 = size of decompressed image 258 * r2 = end of malloc space (and therefore this image) 259 * We basically want: 260 * r4 >= r2 -> OK 261 * r4 + image length <= r5 -> OK 262 */ 263 cmp r4, r2 264 bhs wont_overwrite 265 add r0, r4, r6 266 cmp r0, r5 267 bls wont_overwrite 268 269 mov r5, r2 @ decompress after malloc space 270 mov r0, r5 271 mov r3, r7 272 bl decompress_kernel 273 274 add r0, r0, #127 + 128 @ alignment + stack 275 bic r0, r0, #127 @ align the kernel length 276/* 277 * r0 = decompressed kernel length 278 * r1-r3 = unused 279 * r4 = kernel execution address 280 * r5 = decompressed kernel start 281 * r7 = architecture ID 282 * r8 = atags pointer 283 * r9-r12,r14 = corrupted 284 */ 285 add r1, r5, r0 @ end of decompressed kernel 286 adr r2, reloc_start 287 ldr r3, LC1 288 add r3, r2, r3 2891: ldmia r2!, {r9 - r12, r14} @ copy relocation code 290 stmia r1!, {r9 - r12, r14} 291 ldmia r2!, {r9 - r12, r14} 292 stmia r1!, {r9 - r12, r14} 293 cmp r2, r3 294 blo 1b 295 mov sp, r1 296 add sp, sp, #128 @ relocate the stack 297 298 bl cache_clean_flush 299 ARM( add pc, r5, r0 ) @ call relocation code 300 THUMB( add r12, r5, r0 ) 301 THUMB( mov pc, r12 ) @ call relocation code 302 303/* 304 * We're not in danger of overwriting ourselves. Do this the simple way. 305 * 306 * r4 = kernel execution address 307 * r7 = architecture ID 308 */ 309wont_overwrite: mov r0, r4 310 mov r3, r7 311 bl decompress_kernel 312 b call_kernel 313 314 .align 2 315 .type LC0, #object 316LC0: .word LC0 @ r1 317 .word __bss_start @ r2 318 .word _end @ r3 319 .word _start @ r5 320 .word _image_size @ r6 321 .word _got_start @ r11 322 .word _got_end @ ip 323 .word user_stack_end @ sp 324LC1: .word reloc_end - reloc_start 325 .size LC0, . - LC0 326 327#ifdef CONFIG_ARCH_RPC 328 .globl params 329params: ldr r0, =0x10000100 @ params_phys for RPC 330 mov pc, lr 331 .ltorg 332 .align 333#endif 334 335/* 336 * Turn on the cache. We need to setup some page tables so that we 337 * can have both the I and D caches on. 338 * 339 * We place the page tables 16k down from the kernel execution address, 340 * and we hope that nothing else is using it. If we're using it, we 341 * will go pop! 342 * 343 * On entry, 344 * r4 = kernel execution address 345 * r7 = architecture number 346 * r8 = atags pointer 347 * On exit, 348 * r0, r1, r2, r3, r9, r10, r12 corrupted 349 * This routine must preserve: 350 * r4, r5, r6, r7, r8 351 */ 352 .align 5 353cache_on: mov r3, #8 @ cache_on function 354 b call_cache_fn 355 356__armv4_mpu_cache_on: 357 mov r0, #0x3f @ 4G, the whole 358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 359 mcr p15, 0, r0, c6, c7, 1 360 361 mov r0, #0x80 @ PR7 362 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 363 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 365 366 mov r0, #0xc000 367 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 368 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 369 370 mov r0, #0 371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 374 mrc p15, 0, r0, c1, c0, 0 @ read control reg 375 @ ...I .... ..D. WC.M 376 orr r0, r0, #0x002d @ .... .... ..1. 11.1 377 orr r0, r0, #0x1000 @ ...1 .... .... .... 378 379 mcr p15, 0, r0, c1, c0, 0 @ write control reg 380 381 mov r0, #0 382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 384 mov pc, lr 385 386__armv3_mpu_cache_on: 387 mov r0, #0x3f @ 4G, the whole 388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 389 390 mov r0, #0x80 @ PR7 391 mcr p15, 0, r0, c2, c0, 0 @ cache on 392 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 393 394 mov r0, #0xc000 395 mcr p15, 0, r0, c5, c0, 0 @ access permission 396 397 mov r0, #0 398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 399 /* 400 * ?? ARMv3 MMU does not allow reading the control register, 401 * does this really work on ARMv3 MPU? 402 */ 403 mrc p15, 0, r0, c1, c0, 0 @ read control reg 404 @ .... .... .... WC.M 405 orr r0, r0, #0x000d @ .... .... .... 11.1 406 /* ?? this overwrites the value constructed above? */ 407 mov r0, #0 408 mcr p15, 0, r0, c1, c0, 0 @ write control reg 409 410 /* ?? invalidate for the second time? */ 411 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 412 mov pc, lr 413 414__setup_mmu: sub r3, r4, #16384 @ Page directory size 415 bic r3, r3, #0xff @ Align the pointer 416 bic r3, r3, #0x3f00 417/* 418 * Initialise the page tables, turning on the cacheable and bufferable 419 * bits for the RAM area only. 420 */ 421 mov r0, r3 422 mov r9, r0, lsr #18 423 mov r9, r9, lsl #18 @ start of RAM 424 add r10, r9, #0x10000000 @ a reasonable RAM size 425 mov r1, #0x12 426 orr r1, r1, #3 << 10 427 add r2, r3, #16384 4281: cmp r1, r9 @ if virt > start of RAM 429 orrhs r1, r1, #0x0c @ set cacheable, bufferable 430 cmp r1, r10 @ if virt > end of RAM 431 bichs r1, r1, #0x0c @ clear cacheable, bufferable 432 str r1, [r0], #4 @ 1:1 mapping 433 add r1, r1, #1048576 434 teq r0, r2 435 bne 1b 436/* 437 * If ever we are running from Flash, then we surely want the cache 438 * to be enabled also for our execution instance... We map 2MB of it 439 * so there is no map overlap problem for up to 1 MB compressed kernel. 440 * If the execution is in RAM then we would only be duplicating the above. 441 */ 442 mov r1, #0x1e 443 orr r1, r1, #3 << 10 444 mov r2, pc, lsr #20 445 orr r1, r1, r2, lsl #20 446 add r0, r3, r2, lsl #2 447 str r1, [r0], #4 448 add r1, r1, #1048576 449 str r1, [r0] 450 mov pc, lr 451ENDPROC(__setup_mmu) 452 453__armv4_mmu_cache_on: 454 mov r12, lr 455#ifdef CONFIG_MMU 456 bl __setup_mmu 457 mov r0, #0 458 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 459 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 460 mrc p15, 0, r0, c1, c0, 0 @ read control reg 461 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 462 orr r0, r0, #0x0030 463#ifdef CONFIG_CPU_ENDIAN_BE8 464 orr r0, r0, #1 << 25 @ big-endian page tables 465#endif 466 bl __common_mmu_cache_on 467 mov r0, #0 468 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 469#endif 470 mov pc, r12 471 472__armv7_mmu_cache_on: 473 mov r12, lr 474#ifdef CONFIG_MMU 475 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 476 tst r11, #0xf @ VMSA 477 blne __setup_mmu 478 mov r0, #0 479 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 480 tst r11, #0xf @ VMSA 481 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 482 dsb @ Barriers 483 isb 484#endif 485 mrc p15, 0, r0, c1, c0, 0 @ read control reg 486 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 487 orr r0, r0, #0x003c @ write buffer 488#ifdef CONFIG_MMU 489#ifdef CONFIG_CPU_ENDIAN_BE8 490 orr r0, r0, #1 << 25 @ big-endian page tables 491#endif 492 orrne r0, r0, #1 @ MMU enabled 493 movne r1, #-1 494 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 495 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 496#endif 497 mcr p15, 0, r0, c1, c0, 0 @ load control register 498 mrc p15, 0, r0, c1, c0, 0 @ and read it back 499 mov r0, #0 500 mcr p15, 0, r0, c7, c5, 4 @ ISB 501 mov pc, r12 502 503__fa526_cache_on: 504 mov r12, lr 505 bl __setup_mmu 506 mov r0, #0 507 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache 508 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 509 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 510 mrc p15, 0, r0, c1, c0, 0 @ read control reg 511 orr r0, r0, #0x1000 @ I-cache enable 512 bl __common_mmu_cache_on 513 mov r0, #0 514 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 515 mov pc, r12 516 517__arm6_mmu_cache_on: 518 mov r12, lr 519 bl __setup_mmu 520 mov r0, #0 521 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 522 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 523 mov r0, #0x30 524 bl __common_mmu_cache_on 525 mov r0, #0 526 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 527 mov pc, r12 528 529__common_mmu_cache_on: 530#ifndef CONFIG_THUMB2_KERNEL 531#ifndef DEBUG 532 orr r0, r0, #0x000d @ Write buffer, mmu 533#endif 534 mov r1, #-1 535 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 536 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 537 b 1f 538 .align 5 @ cache line aligned 5391: mcr p15, 0, r0, c1, c0, 0 @ load control register 540 mrc p15, 0, r0, c1, c0, 0 @ and read it back to 541 sub pc, lr, r0, lsr #32 @ properly flush pipeline 542#endif 543 544/* 545 * All code following this line is relocatable. It is relocated by 546 * the above code to the end of the decompressed kernel image and 547 * executed there. During this time, we have no stacks. 548 * 549 * r0 = decompressed kernel length 550 * r1-r3 = unused 551 * r4 = kernel execution address 552 * r5 = decompressed kernel start 553 * r7 = architecture ID 554 * r8 = atags pointer 555 * r9-r12,r14 = corrupted 556 */ 557 .align 5 558reloc_start: add r9, r5, r0 559 sub r9, r9, #128 @ do not copy the stack 560 debug_reloc_start 561 mov r1, r4 5621: 563 .rept 4 564 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel 565 stmia r1!, {r0, r2, r3, r10 - r12, r14} 566 .endr 567 568 cmp r5, r9 569 blo 1b 570 mov sp, r1 571 add sp, sp, #128 @ relocate the stack 572 debug_reloc_end 573 574call_kernel: bl cache_clean_flush 575 bl cache_off 576 mov r0, #0 @ must be zero 577 mov r1, r7 @ restore architecture number 578 mov r2, r8 @ restore atags pointer 579 mov pc, r4 @ call kernel 580 581/* 582 * Here follow the relocatable cache support functions for the 583 * various processors. This is a generic hook for locating an 584 * entry and jumping to an instruction at the specified offset 585 * from the start of the block. Please note this is all position 586 * independent code. 587 * 588 * r1 = corrupted 589 * r2 = corrupted 590 * r3 = block offset 591 * r9 = corrupted 592 * r12 = corrupted 593 */ 594 595call_cache_fn: adr r12, proc_types 596#ifdef CONFIG_CPU_CP15 597 mrc p15, 0, r9, c0, c0 @ get processor ID 598#else 599 ldr r9, =CONFIG_PROCESSOR_ID 600#endif 6011: ldr r1, [r12, #0] @ get value 602 ldr r2, [r12, #4] @ get mask 603 eor r1, r1, r9 @ (real ^ match) 604 tst r1, r2 @ & mask 605 ARM( addeq pc, r12, r3 ) @ call cache function 606 THUMB( addeq r12, r3 ) 607 THUMB( moveq pc, r12 ) @ call cache function 608 add r12, r12, #4*5 609 b 1b 610 611/* 612 * Table for cache operations. This is basically: 613 * - CPU ID match 614 * - CPU ID mask 615 * - 'cache on' method instruction 616 * - 'cache off' method instruction 617 * - 'cache flush' method instruction 618 * 619 * We match an entry using: ((real_id ^ match) & mask) == 0 620 * 621 * Writethrough caches generally only need 'on' and 'off' 622 * methods. Writeback caches _must_ have the flush method 623 * defined. 624 */ 625 .align 2 626 .type proc_types,#object 627proc_types: 628 .word 0x41560600 @ ARM6/610 629 .word 0xffffffe0 630 W(b) __arm6_mmu_cache_off @ works, but slow 631 W(b) __arm6_mmu_cache_off 632 mov pc, lr 633 THUMB( nop ) 634@ b __arm6_mmu_cache_on @ untested 635@ b __arm6_mmu_cache_off 636@ b __armv3_mmu_cache_flush 637 638 .word 0x00000000 @ old ARM ID 639 .word 0x0000f000 640 mov pc, lr 641 THUMB( nop ) 642 mov pc, lr 643 THUMB( nop ) 644 mov pc, lr 645 THUMB( nop ) 646 647 .word 0x41007000 @ ARM7/710 648 .word 0xfff8fe00 649 W(b) __arm7_mmu_cache_off 650 W(b) __arm7_mmu_cache_off 651 mov pc, lr 652 THUMB( nop ) 653 654 .word 0x41807200 @ ARM720T (writethrough) 655 .word 0xffffff00 656 W(b) __armv4_mmu_cache_on 657 W(b) __armv4_mmu_cache_off 658 mov pc, lr 659 THUMB( nop ) 660 661 .word 0x41007400 @ ARM74x 662 .word 0xff00ff00 663 W(b) __armv3_mpu_cache_on 664 W(b) __armv3_mpu_cache_off 665 W(b) __armv3_mpu_cache_flush 666 667 .word 0x41009400 @ ARM94x 668 .word 0xff00ff00 669 W(b) __armv4_mpu_cache_on 670 W(b) __armv4_mpu_cache_off 671 W(b) __armv4_mpu_cache_flush 672 673 .word 0x00007000 @ ARM7 IDs 674 .word 0x0000f000 675 mov pc, lr 676 THUMB( nop ) 677 mov pc, lr 678 THUMB( nop ) 679 mov pc, lr 680 THUMB( nop ) 681 682 @ Everything from here on will be the new ID system. 683 684 .word 0x4401a100 @ sa110 / sa1100 685 .word 0xffffffe0 686 W(b) __armv4_mmu_cache_on 687 W(b) __armv4_mmu_cache_off 688 W(b) __armv4_mmu_cache_flush 689 690 .word 0x6901b110 @ sa1110 691 .word 0xfffffff0 692 W(b) __armv4_mmu_cache_on 693 W(b) __armv4_mmu_cache_off 694 W(b) __armv4_mmu_cache_flush 695 696 .word 0x56056900 697 .word 0xffffff00 @ PXA9xx 698 W(b) __armv4_mmu_cache_on 699 W(b) __armv4_mmu_cache_off 700 W(b) __armv4_mmu_cache_flush 701 702 .word 0x56158000 @ PXA168 703 .word 0xfffff000 704 W(b) __armv4_mmu_cache_on 705 W(b) __armv4_mmu_cache_off 706 W(b) __armv5tej_mmu_cache_flush 707 708 .word 0x56050000 @ Feroceon 709 .word 0xff0f0000 710 W(b) __armv4_mmu_cache_on 711 W(b) __armv4_mmu_cache_off 712 W(b) __armv5tej_mmu_cache_flush 713 714#ifdef CONFIG_CPU_FEROCEON_OLD_ID 715 /* this conflicts with the standard ARMv5TE entry */ 716 .long 0x41009260 @ Old Feroceon 717 .long 0xff00fff0 718 b __armv4_mmu_cache_on 719 b __armv4_mmu_cache_off 720 b __armv5tej_mmu_cache_flush 721#endif 722 723 .word 0x66015261 @ FA526 724 .word 0xff01fff1 725 W(b) __fa526_cache_on 726 W(b) __armv4_mmu_cache_off 727 W(b) __fa526_cache_flush 728 729 @ These match on the architecture ID 730 731 .word 0x00020000 @ ARMv4T 732 .word 0x000f0000 733 W(b) __armv4_mmu_cache_on 734 W(b) __armv4_mmu_cache_off 735 W(b) __armv4_mmu_cache_flush 736 737 .word 0x00050000 @ ARMv5TE 738 .word 0x000f0000 739 W(b) __armv4_mmu_cache_on 740 W(b) __armv4_mmu_cache_off 741 W(b) __armv4_mmu_cache_flush 742 743 .word 0x00060000 @ ARMv5TEJ 744 .word 0x000f0000 745 W(b) __armv4_mmu_cache_on 746 W(b) __armv4_mmu_cache_off 747 W(b) __armv5tej_mmu_cache_flush 748 749 .word 0x0007b000 @ ARMv6 750 .word 0x000ff000 751 W(b) __armv4_mmu_cache_on 752 W(b) __armv4_mmu_cache_off 753 W(b) __armv6_mmu_cache_flush 754 755 .word 0x560f5810 @ Marvell PJ4 ARMv6 756 .word 0xff0ffff0 757 W(b) __armv4_mmu_cache_on 758 W(b) __armv4_mmu_cache_off 759 W(b) __armv6_mmu_cache_flush 760 761 .word 0x000f0000 @ new CPU Id 762 .word 0x000f0000 763 W(b) __armv7_mmu_cache_on 764 W(b) __armv7_mmu_cache_off 765 W(b) __armv7_mmu_cache_flush 766 767 .word 0 @ unrecognised type 768 .word 0 769 mov pc, lr 770 THUMB( nop ) 771 mov pc, lr 772 THUMB( nop ) 773 mov pc, lr 774 THUMB( nop ) 775 776 .size proc_types, . - proc_types 777 778/* 779 * Turn off the Cache and MMU. ARMv3 does not support 780 * reading the control register, but ARMv4 does. 781 * 782 * On exit, 783 * r0, r1, r2, r3, r9, r12 corrupted 784 * This routine must preserve: 785 * r4, r6, r7 786 */ 787 .align 5 788cache_off: mov r3, #12 @ cache_off function 789 b call_cache_fn 790 791__armv4_mpu_cache_off: 792 mrc p15, 0, r0, c1, c0 793 bic r0, r0, #0x000d 794 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 795 mov r0, #0 796 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 797 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 798 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 799 mov pc, lr 800 801__armv3_mpu_cache_off: 802 mrc p15, 0, r0, c1, c0 803 bic r0, r0, #0x000d 804 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 805 mov r0, #0 806 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 807 mov pc, lr 808 809__armv4_mmu_cache_off: 810#ifdef CONFIG_MMU 811 mrc p15, 0, r0, c1, c0 812 bic r0, r0, #0x000d 813 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 814 mov r0, #0 815 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 816 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 817#endif 818 mov pc, lr 819 820__armv7_mmu_cache_off: 821 mrc p15, 0, r0, c1, c0 822#ifdef CONFIG_MMU 823 bic r0, r0, #0x000d 824#else 825 bic r0, r0, #0x000c 826#endif 827 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 828 mov r12, lr 829 bl __armv7_mmu_cache_flush 830 mov r0, #0 831#ifdef CONFIG_MMU 832 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 833#endif 834 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 835 mcr p15, 0, r0, c7, c10, 4 @ DSB 836 mcr p15, 0, r0, c7, c5, 4 @ ISB 837 mov pc, r12 838 839__arm6_mmu_cache_off: 840 mov r0, #0x00000030 @ ARM6 control reg. 841 b __armv3_mmu_cache_off 842 843__arm7_mmu_cache_off: 844 mov r0, #0x00000070 @ ARM7 control reg. 845 b __armv3_mmu_cache_off 846 847__armv3_mmu_cache_off: 848 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 849 mov r0, #0 850 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 851 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 852 mov pc, lr 853 854/* 855 * Clean and flush the cache to maintain consistency. 856 * 857 * On exit, 858 * r1, r2, r3, r9, r10, r11, r12 corrupted 859 * This routine must preserve: 860 * r0, r4, r5, r6, r7 861 */ 862 .align 5 863cache_clean_flush: 864 mov r3, #16 865 b call_cache_fn 866 867__armv4_mpu_cache_flush: 868 mov r2, #1 869 mov r3, #0 870 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 871 mov r1, #7 << 5 @ 8 segments 8721: orr r3, r1, #63 << 26 @ 64 entries 8732: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 874 subs r3, r3, #1 << 26 875 bcs 2b @ entries 63 to 0 876 subs r1, r1, #1 << 5 877 bcs 1b @ segments 7 to 0 878 879 teq r2, #0 880 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 881 mcr p15, 0, ip, c7, c10, 4 @ drain WB 882 mov pc, lr 883 884__fa526_cache_flush: 885 mov r1, #0 886 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 887 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 888 mcr p15, 0, r1, c7, c10, 4 @ drain WB 889 mov pc, lr 890 891__armv6_mmu_cache_flush: 892 mov r1, #0 893 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 894 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 895 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 896 mcr p15, 0, r1, c7, c10, 4 @ drain WB 897 mov pc, lr 898 899__armv7_mmu_cache_flush: 900 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 901 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 902 mov r10, #0 903 beq hierarchical 904 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 905 b iflush 906hierarchical: 907 mcr p15, 0, r10, c7, c10, 5 @ DMB 908 stmfd sp!, {r0-r7, r9-r11} 909 mrc p15, 1, r0, c0, c0, 1 @ read clidr 910 ands r3, r0, #0x7000000 @ extract loc from clidr 911 mov r3, r3, lsr #23 @ left align loc bit field 912 beq finished @ if loc is 0, then no need to clean 913 mov r10, #0 @ start clean at cache level 0 914loop1: 915 add r2, r10, r10, lsr #1 @ work out 3x current cache level 916 mov r1, r0, lsr r2 @ extract cache type bits from clidr 917 and r1, r1, #7 @ mask of the bits for current cache only 918 cmp r1, #2 @ see what cache we have at this level 919 blt skip @ skip if no cache, or just i-cache 920 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 921 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 922 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 923 and r2, r1, #7 @ extract the length of the cache lines 924 add r2, r2, #4 @ add 4 (line length offset) 925 ldr r4, =0x3ff 926 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 927 clz r5, r4 @ find bit position of way size increment 928 ldr r7, =0x7fff 929 ands r7, r7, r1, lsr #13 @ extract max number of the index size 930loop2: 931 mov r9, r4 @ create working copy of max way size 932loop3: 933 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 934 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 935 THUMB( lsl r6, r9, r5 ) 936 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 937 THUMB( lsl r6, r7, r2 ) 938 THUMB( orr r11, r11, r6 ) @ factor index number into r11 939 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 940 subs r9, r9, #1 @ decrement the way 941 bge loop3 942 subs r7, r7, #1 @ decrement the index 943 bge loop2 944skip: 945 add r10, r10, #2 @ increment cache number 946 cmp r3, r10 947 bgt loop1 948finished: 949 ldmfd sp!, {r0-r7, r9-r11} 950 mov r10, #0 @ swith back to cache level 0 951 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 952iflush: 953 mcr p15, 0, r10, c7, c10, 4 @ DSB 954 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 955 mcr p15, 0, r10, c7, c10, 4 @ DSB 956 mcr p15, 0, r10, c7, c5, 4 @ ISB 957 mov pc, lr 958 959__armv5tej_mmu_cache_flush: 9601: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 961 bne 1b 962 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 963 mcr p15, 0, r0, c7, c10, 4 @ drain WB 964 mov pc, lr 965 966__armv4_mmu_cache_flush: 967 mov r2, #64*1024 @ default: 32K dcache size (*2) 968 mov r11, #32 @ default: 32 byte line size 969 mrc p15, 0, r3, c0, c0, 1 @ read cache type 970 teq r3, r9 @ cache ID register present? 971 beq no_cache_id 972 mov r1, r3, lsr #18 973 and r1, r1, #7 974 mov r2, #1024 975 mov r2, r2, lsl r1 @ base dcache size *2 976 tst r3, #1 << 14 @ test M bit 977 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 978 mov r3, r3, lsr #12 979 and r3, r3, #3 980 mov r11, #8 981 mov r11, r11, lsl r3 @ cache line size in bytes 982no_cache_id: 983 mov r1, pc 984 bic r1, r1, #63 @ align to longest cache line 985 add r2, r1, r2 9861: 987 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache 988 THUMB( ldr r3, [r1] ) @ s/w flush D cache 989 THUMB( add r1, r1, r11 ) 990 teq r1, r2 991 bne 1b 992 993 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 994 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 995 mcr p15, 0, r1, c7, c10, 4 @ drain WB 996 mov pc, lr 997 998__armv3_mmu_cache_flush: 999__armv3_mpu_cache_flush: 1000 mov r1, #0 1001 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 1002 mov pc, lr 1003 1004/* 1005 * Various debugging routines for printing hex characters and 1006 * memory, which again must be relocatable. 1007 */ 1008#ifdef DEBUG 1009 .align 2 1010 .type phexbuf,#object 1011phexbuf: .space 12 1012 .size phexbuf, . - phexbuf 1013 1014@ phex corrupts {r0, r1, r2, r3} 1015phex: adr r3, phexbuf 1016 mov r2, #0 1017 strb r2, [r3, r1] 10181: subs r1, r1, #1 1019 movmi r0, r3 1020 bmi puts 1021 and r2, r0, #15 1022 mov r0, r0, lsr #4 1023 cmp r2, #10 1024 addge r2, r2, #7 1025 add r2, r2, #'0' 1026 strb r2, [r3, r1] 1027 b 1b 1028 1029@ puts corrupts {r0, r1, r2, r3} 1030puts: loadsp r3, r1 10311: ldrb r2, [r0], #1 1032 teq r2, #0 1033 moveq pc, lr 10342: writeb r2, r3 1035 mov r1, #0x00020000 10363: subs r1, r1, #1 1037 bne 3b 1038 teq r2, #'\n' 1039 moveq r2, #'\r' 1040 beq 2b 1041 teq r0, #0 1042 bne 1b 1043 mov pc, lr 1044@ putc corrupts {r0, r1, r2, r3} 1045putc: 1046 mov r2, r0 1047 mov r0, #0 1048 loadsp r3, r1 1049 b 2b 1050 1051@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} 1052memdump: mov r12, r0 1053 mov r10, lr 1054 mov r11, #0 10552: mov r0, r11, lsl #2 1056 add r0, r0, r12 1057 mov r1, #8 1058 bl phex 1059 mov r0, #':' 1060 bl putc 10611: mov r0, #' ' 1062 bl putc 1063 ldr r0, [r12, r11, lsl #2] 1064 mov r1, #8 1065 bl phex 1066 and r0, r11, #7 1067 teq r0, #3 1068 moveq r0, #' ' 1069 bleq putc 1070 and r0, r11, #7 1071 add r11, r11, #1 1072 teq r0, #7 1073 bne 1b 1074 mov r0, #'\n' 1075 bl putc 1076 cmp r11, #64 1077 blt 2b 1078 mov pc, r10 1079#endif 1080 1081 .ltorg 1082reloc_end: 1083 1084 .align 1085 .section ".stack", "w" 1086user_stack: .space 4096 1087user_stack_end: 1088