1/* 2 * linux/arch/arm/mach-omap2/sleep.S 3 * 4 * (C) Copyright 2004 5 * Texas Instruments, <www.ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * 8 * (C) Copyright 2006 Nokia Corporation 9 * Fixed idle loop sleep 10 * Igor Stoppa <igor.stoppa@nokia.com> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <linux/linkage.h> 29#include <asm/assembler.h> 30#include <mach/io.h> 31 32#include <plat/omap24xx.h> 33 34#include "sdrc.h" 35 36/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 37#define A_SDRC0_V (0xC0000000) 38 39 .text 40 41/* 42 * Forces OMAP into idle state 43 * 44 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI 45 * for normal idles. 46 * 47 * Note: This code get's copied to internal SRAM at boot. When the OMAP 48 * wakes up it continues execution at the point it went to sleep. 49 */ 50ENTRY(omap24xx_idle_loop_suspend) 51 stmfd sp!, {r0, lr} @ save registers on stack 52 mov r0, #0 @ clear for mcr setup 53 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 54 ldmfd sp!, {r0, pc} @ restore regs and return 55 56ENTRY(omap24xx_idle_loop_suspend_sz) 57 .word . - omap24xx_idle_loop_suspend 58 59ENTRY(omap24xx_cpu_suspend) 60 stmfd sp!, {r0 - r12, lr} @ save registers on stack 61 mov r3, #0x0 @ clear for mcr call 62 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 63 nop 64 nop 65 ldr r4, [r2] @ read SDRC_POWER 66 orr r4, r4, #0x40 @ enable self refresh on idle req 67 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 68 str r4, [r2] @ make it so 69 nop 70 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt 71 nop 72loop: 73 subs r5, r5, #0x1 @ awake, wait just a bit 74 bne loop 75 76 /* The DPLL has to be on before we take the DDR out of self refresh */ 77 bic r4, r4, #0x40 @ now clear self refresh bit. 78 str r4, [r2] @ write to SDRC_POWER 79 ldr r4, A_SDRC0 @ make a clock happen 80 ldr r4, [r4] @ read A_SDRC0 81 nop @ start auto refresh only after clk ok 82 movs r0, r0 @ see if DDR or SDR 83 strne r0, [r1] @ rewrite DLLA to force DLL reload 84 addne r1, r1, #0x8 @ move to DLLB 85 strne r0, [r1] @ rewrite DLLB to force DLL reload 86 87 mov r5, #0x1000 88loop2: 89 subs r5, r5, #0x1 90 bne loop2 91 /* resume*/ 92 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 93 94A_SDRC0: 95 .word A_SDRC0_V 96 97ENTRY(omap24xx_cpu_suspend_sz) 98 .word . - omap24xx_cpu_suspend 99