Lines Matching refs:mcr
81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
148 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
176 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
179 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
215 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
251 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
254 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
255 mcr p15, 0, r0, c7, c10, 4 @ drain WB
278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
296 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
297 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
318 mcr p15, 0, r0, c7, c10, 4 @ drain WB
328 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
329 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
331 mcr p15, 0, r0, c7, c10, 4 @ drain WB
345 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
349 mcr p15, 0, r0, c7, c10, 4 @ drain WB
359 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
360 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
362 mcr p15, 0, r0, c7, c10, 4 @ drain WB
432 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
438 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
443 mcr p15, 0, r0, c7, c10, 4 @ drain WB
471 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
472 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
488 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
491 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
493 mcr p15, 0, r0, c7, c10, 4 @ drain WB
502 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
503 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
505 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4