1/* 2 * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720 3 * 4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) 5 * Rob Scott (rscott@mtrob.fdns.net) 6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. 7 * hacked for non-paged-MM by Hyok S. Choi, 2004. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * 24 * These are the low level assembler for performing cache and TLB 25 * functions on the ARM720T. The ARM720T has a writethrough IDC 26 * cache, so we don't need to clean it. 27 * 28 * Changelog: 29 * 05-09-2000 SJH Created by moving 720 specific functions 30 * out of 'proc-arm6,7.S' per RMK discussion 31 * 07-25-2000 SJH Added idle function. 32 * 08-25-2000 DBS Updated for integration of ARM Ltd version. 33 * 04-20-2004 HSC modified for non-paged memory management mode. 34 */ 35#include <linux/linkage.h> 36#include <linux/init.h> 37#include <asm/assembler.h> 38#include <asm/asm-offsets.h> 39#include <asm/hwcap.h> 40#include <asm/pgtable-hwdef.h> 41#include <asm/pgtable.h> 42#include <asm/ptrace.h> 43 44#include "proc-macros.S" 45 46/* 47 * Function: arm720_proc_init (void) 48 * : arm720_proc_fin (void) 49 * 50 * Notes : This processor does not require these 51 */ 52ENTRY(cpu_arm720_dcache_clean_area) 53ENTRY(cpu_arm720_proc_init) 54 mov pc, lr 55 56ENTRY(cpu_arm720_proc_fin) 57 mrc p15, 0, r0, c1, c0, 0 58 bic r0, r0, #0x1000 @ ...i............ 59 bic r0, r0, #0x000e @ ............wca. 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mov pc, lr 62 63/* 64 * Function: arm720_proc_do_idle(void) 65 * Params : r0 = unused 66 * Purpose : put the processer in proper idle mode 67 */ 68ENTRY(cpu_arm720_do_idle) 69 mov pc, lr 70 71/* 72 * Function: arm720_switch_mm(unsigned long pgd_phys) 73 * Params : pgd_phys Physical address of page table 74 * Purpose : Perform a task switch, saving the old process' state and restoring 75 * the new. 76 */ 77ENTRY(cpu_arm720_switch_mm) 78#ifdef CONFIG_MMU 79 mov r1, #0 80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 83#endif 84 mov pc, lr 85 86/* 87 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) 88 * Params : r0 = Address to set 89 * : r1 = value to set 90 * Purpose : Set a PTE and flush it out of any WB cache 91 */ 92 .align 5 93ENTRY(cpu_arm720_set_pte_ext) 94#ifdef CONFIG_MMU 95 armv3_set_pte_ext wc_disable=0 96#endif 97 mov pc, lr 98 99/* 100 * Function: arm720_reset 101 * Params : r0 = address to jump to 102 * Notes : This sets up everything for a reset 103 */ 104ENTRY(cpu_arm720_reset) 105 mov ip, #0 106 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 107#ifdef CONFIG_MMU 108 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 109#endif 110 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 111 bic ip, ip, #0x000f @ ............wcam 112 bic ip, ip, #0x2100 @ ..v....s........ 113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 114 mov pc, r0 115 116 __INIT 117 118 .type __arm710_setup, #function 119__arm710_setup: 120 mov r0, #0 121 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 122#ifdef CONFIG_MMU 123 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 124#endif 125 mrc p15, 0, r0, c1, c0 @ get control register 126 ldr r5, arm710_cr1_clear 127 bic r0, r0, r5 128 ldr r5, arm710_cr1_set 129 orr r0, r0, r5 130 mov pc, lr @ __ret (head.S) 131 .size __arm710_setup, . - __arm710_setup 132 133 /* 134 * R 135 * .RVI ZFRS BLDP WCAM 136 * .... 0001 ..11 1101 137 * 138 */ 139 .type arm710_cr1_clear, #object 140 .type arm710_cr1_set, #object 141arm710_cr1_clear: 142 .word 0x0f3f 143arm710_cr1_set: 144 .word 0x013d 145 146 .type __arm720_setup, #function 147__arm720_setup: 148 mov r0, #0 149 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 150#ifdef CONFIG_MMU 151 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 152#endif 153 adr r5, arm720_crval 154 ldmia r5, {r5, r6} 155 mrc p15, 0, r0, c1, c0 @ get control register 156 bic r0, r0, r5 157 orr r0, r0, r6 158 mov pc, lr @ __ret (head.S) 159 .size __arm720_setup, . - __arm720_setup 160 161 /* 162 * R 163 * .RVI ZFRS BLDP WCAM 164 * ..1. 1001 ..11 1101 165 * 166 */ 167 .type arm720_crval, #object 168arm720_crval: 169 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130 170 171 __INITDATA 172 173/* 174 * Purpose : Function pointers used to access above functions - all calls 175 * come through these 176 */ 177 .type arm720_processor_functions, #object 178ENTRY(arm720_processor_functions) 179 .word v4t_late_abort 180 .word legacy_pabort 181 .word cpu_arm720_proc_init 182 .word cpu_arm720_proc_fin 183 .word cpu_arm720_reset 184 .word cpu_arm720_do_idle 185 .word cpu_arm720_dcache_clean_area 186 .word cpu_arm720_switch_mm 187 .word cpu_arm720_set_pte_ext 188 .size arm720_processor_functions, . - arm720_processor_functions 189 190 .section ".rodata" 191 192 .type cpu_arch_name, #object 193cpu_arch_name: .asciz "armv4t" 194 .size cpu_arch_name, . - cpu_arch_name 195 196 .type cpu_elf_name, #object 197cpu_elf_name: .asciz "v4" 198 .size cpu_elf_name, . - cpu_elf_name 199 200 .type cpu_arm710_name, #object 201cpu_arm710_name: 202 .asciz "ARM710T" 203 .size cpu_arm710_name, . - cpu_arm710_name 204 205 .type cpu_arm720_name, #object 206cpu_arm720_name: 207 .asciz "ARM720T" 208 .size cpu_arm720_name, . - cpu_arm720_name 209 210 .align 211 212/* 213 * See <asm/procinfo.h> for a definition of this structure. 214 */ 215 216 .section ".proc.info.init", #alloc, #execinstr 217 218 .type __arm710_proc_info, #object 219__arm710_proc_info: 220 .long 0x41807100 @ cpu_val 221 .long 0xffffff00 @ cpu_mask 222 .long PMD_TYPE_SECT | \ 223 PMD_SECT_BUFFERABLE | \ 224 PMD_SECT_CACHEABLE | \ 225 PMD_BIT4 | \ 226 PMD_SECT_AP_WRITE | \ 227 PMD_SECT_AP_READ 228 .long PMD_TYPE_SECT | \ 229 PMD_BIT4 | \ 230 PMD_SECT_AP_WRITE | \ 231 PMD_SECT_AP_READ 232 b __arm710_setup @ cpu_flush 233 .long cpu_arch_name @ arch_name 234 .long cpu_elf_name @ elf_name 235 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap 236 .long cpu_arm710_name @ name 237 .long arm720_processor_functions 238 .long v4_tlb_fns 239 .long v4wt_user_fns 240 .long v4_cache_fns 241 .size __arm710_proc_info, . - __arm710_proc_info 242 243 .type __arm720_proc_info, #object 244__arm720_proc_info: 245 .long 0x41807200 @ cpu_val 246 .long 0xffffff00 @ cpu_mask 247 .long PMD_TYPE_SECT | \ 248 PMD_SECT_BUFFERABLE | \ 249 PMD_SECT_CACHEABLE | \ 250 PMD_BIT4 | \ 251 PMD_SECT_AP_WRITE | \ 252 PMD_SECT_AP_READ 253 .long PMD_TYPE_SECT | \ 254 PMD_BIT4 | \ 255 PMD_SECT_AP_WRITE | \ 256 PMD_SECT_AP_READ 257 b __arm720_setup @ cpu_flush 258 .long cpu_arch_name @ arch_name 259 .long cpu_elf_name @ elf_name 260 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap 261 .long cpu_arm720_name @ name 262 .long arm720_processor_functions 263 .long v4_tlb_fns 264 .long v4wt_user_fns 265 .long v4_cache_fns 266 .size __arm720_proc_info, . - __arm720_proc_info 267