Lines Matching refs:mcr
28 mcr p14, 0, \ch, c0, c5, 0
36 mcr p14, 0, \ch, c0, c5, 0
42 mcr p14, 0, \ch, c8, c0, 0
48 mcr p14, 0, \ch, c1, c0, 0
358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
362 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
363 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
364 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
367 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
368 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
379 mcr p15, 0, r0, c1, c0, 0 @ write control reg
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
391 mcr p15, 0, r0, c2, c0, 0 @ cache on
392 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
395 mcr p15, 0, r0, c5, c0, 0 @ access permission
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
408 mcr p15, 0, r0, c1, c0, 0 @ write control reg
411 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
458 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
459 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
468 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
479 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
497 mcr p15, 0, r0, c1, c0, 0 @ load control register
500 mcr p15, 0, r0, c7, c5, 4 @ ISB
507 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
508 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
509 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
514 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
521 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
522 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
526 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
535 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
536 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
539 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
794 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
796 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
797 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
798 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
804 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
806 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
813 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
815 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
816 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
827 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
832 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
834 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
835 mcr p15, 0, r0, c7, c10, 4 @ DSB
836 mcr p15, 0, r0, c7, c5, 4 @ ISB
848 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
850 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
851 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
870 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
873 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
881 mcr p15, 0, ip, c7, c10, 4 @ drain WB
886 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
887 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
888 mcr p15, 0, r1, c7, c10, 4 @ drain WB
893 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
894 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
895 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
896 mcr p15, 0, r1, c7, c10, 4 @ drain WB
904 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
907 mcr p15, 0, r10, c7, c10, 5 @ DMB
920 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
921 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
939 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
951 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
953 mcr p15, 0, r10, c7, c10, 4 @ DSB
954 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
955 mcr p15, 0, r10, c7, c10, 4 @ DSB
956 mcr p15, 0, r10, c7, c5, 4 @ ISB
962 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
963 mcr p15, 0, r0, c7, c10, 4 @ drain WB
993 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
994 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
995 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1001 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3