Lines Matching refs:mcr
72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
138 mcr p14, 0, r0, c7, c0, 0 @ go to idle
187 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
214 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
220 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
221 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
241 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
242 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
262 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
266 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
279 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
296 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
300 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
357 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
358 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
359 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
361 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
362 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
413 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
414 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
415 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
416 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
418 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
421 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
426 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg