Implement hardware masking for MSI and MSI-X on amd64. Note that masking
MSIs can only be done for PCI devices that implement per-vector masking,
which a lot of hardware doesn't implement.

ok mlarkin@

Implement Multiple Message MSI support on amd64. This is experimental code
to assist qwx(4) development. We may remove this code again at some point
in the future.

Multiple Message MSI has some serious design flaws, especially when
combined with the APIC interrupt controller architecture. It was
superseded by MSI-X. Unfortunately qwx(4) does not implement MSI-X.

ok stsp@, deraadt@

Only probe device 0 on PCI busses corresponding to a PCIe root port or a
PCIe switch/bridge downstream port. This fixes an issue where a device would
show up 32 times if the PCIe port does not terminate configuration requests
targeted at device numbers 1-31 as required by the spec and the PCIe device
does not filter requests based on its own device number. Linux, NetBSD and
FreeBSD (to some extent) already do this.

This should fix an issue seen on Ampere Altra where the BMC's PCI bridge
and USB controller would show up multiple times.

ok jsg@

Interrups -> Interrupts

Add a few more PCIe capability registers and bits. As usual, the names
are taken from Intel chipset documentation. Prompted by a diff from kurt@.

ok kurt@

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Implement Multiple Message MSI support on amd64. This is experimental code
to assist qwx(4) development. We may remove this code again at some point
in the future.

Multiple Message MSI has some serious design flaws, especially when
combined with the APIC interrupt controller architecture. It was
superseded by MSI-X. Unfortunately qwx(4) does not implement MSI-X.

ok stsp@, deraadt@

Only probe device 0 on PCI busses corresponding to a PCIe root port or a
PCIe switch/bridge downstream port. This fixes an issue where a device would
show up 32 times if the PCIe port does not terminate configuration requests
targeted at device numbers 1-31 as required by the spec and the PCIe device
does not filter requests based on its own device number. Linux, NetBSD and
FreeBSD (to some extent) already do this.

This should fix an issue seen on Ampere Altra where the BMC's PCI bridge
and USB controller would show up multiple times.

ok jsg@

Interrups -> Interrupts

Add a few more PCIe capability registers and bits. As usual, the names
are taken from Intel chipset documentation. Prompted by a diff from kurt@.

ok kurt@

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Only probe device 0 on PCI busses corresponding to a PCIe root port or a
PCIe switch/bridge downstream port. This fixes an issue where a device would
show up 32 times if the PCIe port does not terminate configuration requests
targeted at device numbers 1-31 as required by the spec and the PCIe device
does not filter requests based on its own device number. Linux, NetBSD and
FreeBSD (to some extent) already do this.

This should fix an issue seen on Ampere Altra where the BMC's PCI bridge
and USB controller would show up multiple times.

ok jsg@

Interrups -> Interrupts

Add a few more PCIe capability registers and bits. As usual, the names
are taken from Intel chipset documentation. Prompted by a diff from kurt@.

ok kurt@

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Interrups -> Interrupts

Add a few more PCIe capability registers and bits. As usual, the names
are taken from Intel chipset documentation. Prompted by a diff from kurt@.

ok kurt@

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Add a few more PCIe capability registers and bits. As usual, the names
are taken from Intel chipset documentation. Prompted by a diff from kurt@.

ok kurt@

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Have iwm(4) configure the PCIe LTR.

Patch by Imre Vadasz.
Cross-check and pcireg.h tweak by kettenis@
ok patrick@

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu

more pci subclasses and such; netbsd

more bridge types

Adaption to new bus.h from NetBSD. Various driver has been updated to
NetBSD 961107 state. Other has not, partly because sometimes the bus.h
changes was coupled with other changes.

Add ATM defines. From Jim Rees <rees@umich.edu>

partial sync with netbsd 960418, more to come

NetBSD 960317 merge

branches: 1.1.1;
Initial revision

Fix definitions of PCI_MSIX_MAU32 and add a define for the MSI-X function
mask bit.

ok mlarkin@, jmatthew@

Let ahci(4) match on _CLS instead of _HID when attaching at acpi(4). Avoids
having to add many more _HID entries to the match table.

ok deraadt@, mlarkin@

vmd: allow guest PCI interrupt line reassignment.

I also added a couple config space register names to pcireg.h to try and
reduce the use of magic numbers in vmd/pci.c

ok pd@

From FreeBSD (r227593, r307982):
More and more RealTek controllers started to implement EEE feature.
Vendor driver seems to load a kind of firmware for EEE with
additional PHY fixups. It is known that the EEE feature may need
ASPM support. Unfortunately there is no documentation for EEE of
the controller so enabling ASPM may cause more problems.

The Realtek vendor drivers for FreeBSD and Linux also disable ASPM and
clock request. While here, add a define for the ECPM (Enable Clock Power
Management) bit.

Tested by stsp@ and myself.
ok stsp@

More PCI extended capabilities handling in pcidump.

From Simon Mages

ok deraadt@

Add some more PCI classes and subclasses. Checked against EDK2 as
"PCI Code and ID Assignment Specification" is only available for those
willing to pay thousands of dollars for PDFs.

Prompted by a dmesg from an AMD Zen system which uses class 0x13
(Non-Essential Instrumentation) and System subclass 0x06 (IOMMU). There
is currently no public documentation for AMD family 17h to reference to
see if this is sane.

ok kettenis@ on an earlier version

Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin

Fix two issues in the MSI-X code. First, actually read the MSI-X capability
register. Second, correctly decode the table sizefromits contents.

First issue pointed out by David Hill (with the help of clang). Second
issue spotted after seeing a diff from Christiano Hasbaert.

Initial support for MSI-X. Only supported on amd64 for now. I have diffs to
actually use this in em(4) and xhci(4), but I'm not committing those yet
because we almost certainly need to save and restore the MSI-X registers
during suspend/resume. However, this allows mpi@ to play with multiple-vector
support in networking hardware.

Requested by mpi@
ok mlarkin@, mikeb@

Add missing define for hpb(4).

Add PME_STATUS and PME_EN bitmasks for the PCI PMCSR register.
ok kettenis@

apparently NVM is a type of mass storage now

add a define for the link capabilities register for
version 2 of the PCIe capability.

Define some more DCSR/DCTL bits; ok kettenis

Add define for capability 0x12 (SATA).

Fix typo in the "fixed" HyperTransport MSI Mapping Capability address.

Enable MSI for HyperTransport devices that have MSI remapping enabled.

Add register definitions for PCI MSI capaility.

ok oga@, miod@, marco@, dlg@, krw@

PCIe based sparc64 machines have always supported access to the extended PCIe
configuration space. So on pyro(4) and vpci(4) return the size appropriate
for the extended PCIe configuration space.

ok miod@

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

Add definition for "Extended Synch" bit in PCIe Link Control register.
From PCI Express(R) Base Specification Rev 2.0.

Add "Interrupt Disable" bit definition for the PCI Configuration Space
Command register. From PCI Express Base Specification Rev 2.0.
Use same naming as NetBSD.
Needed for wpi(4) and iwn(4).

move some generic PCIe register flags used in wpi(4) and iwn(4)
into common pcireg.h

ok deraadt@, kettenis@, dlg@

Add PCI VPD read/write functions from NetBSD required for some things
dlg is playing with.

'put it in' dlg@

First step towards PCI Express/ExpressCard hotplug. Unplug should work on
detachable drivers.

"put it in" deraadt@

puc@cardbus (only added (commented out) to whom has puc@pci enabled)
tested on puc@pci by fkr and meself on the cardbus.
still needs a bit more work but generally works.
deraadt@ ok and some input from miod@

add 2 subclasses, subclass storage SAS and subclass system SD Host Controller.

From NetBSD

Support for standard SD host controllers like the Ricoh 5C822, a small
generic bus layer, and SCSI emulation for SD/MMC memory cards.

add PCI multimedia subclass type of HD audio.

add macros for the expansion ROM base address register

ok brad@ grange@ fgsch@

add PCI_ID_CODE

From NetBSD

Mark u_int64_t constants with ULL to make gcc3 happy.
ok drahn@

convert __attribute__((__packed__)) to __packed so that parsers unaware
of gcc extensions have more of a chance.
ok mcbride@, no objections from millert@, deraadt@

power management status reg. definition; from netbsd.
ok deraadt@ henning@ krw@.

this bit is defined as prefetchable and not cachable and thus rename and use appropriately

PCI_CAP_MBI should really be PCI_CAP_MSI
ok jason@

Add a couple of new pci subclasses and caps from NetBSD
ok jason@

definitions and structures for vital product data (VPD); from netbsd

define PCI_COMMAND_STATUS_BITS for printfs, according to the enlisted defines

s/REESSERVED/RESERVED/

branches: 1.17.4;
more class/subclass/caps ids; from netbsd

Add PCI Power Management Control Register definitions; from NetBSD.

Defines for min_gnt and max_lat fields in the bhlc reg.
Not used yet.

support 64bit BARs from NetBSD

import a few useful consts from netbsd; mainly for pcibios thing slip

branches: 1.12.2;
Missed earlier: add PCI_HDRTYPE_TYPE macro, from NetBSD.

Added pci_mapreg* interface from NetBSD.
Added PCI 2.2 stuff from NetBSD
Modified if_de to use mapreg interface

A slew of manifest constants for pci configuration registers gotten from freebsd

fix bhlcr shift values; fgsch@olimpo.com.br

UDF and 66MHz support; zubin@clouseau.arl.wustl.edu