pcireg.h revision 1.10
1/* $OpenBSD: pcireg.h,v 1.10 1999/01/30 23:24:22 niklas Exp $ */ 2/* $NetBSD: pcireg.h,v 1.11 1996/08/10 15:42:33 mycroft Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61/* 62 * Command and status register. 63 */ 64#define PCI_COMMAND_STATUS_REG 0x04 65 66#define PCI_COMMAND_IO_ENABLE 0x00000001 67#define PCI_COMMAND_MEM_ENABLE 0x00000002 68#define PCI_COMMAND_MASTER_ENABLE 0x00000004 69#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 70#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 71#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 72#define PCI_COMMAND_PARITY_ENABLE 0x00000040 73#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 74#define PCI_COMMAND_SERR_ENABLE 0x00000100 75#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 76 77#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 78#define PCI_STATUS_UDF_SUPPORT 0x00400000 79#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 80#define PCI_STATUS_PARITY_ERROR 0x01000000 81#define PCI_STATUS_DEVSEL_FAST 0x00000000 82#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 83#define PCI_STATUS_DEVSEL_SLOW 0x04000000 84#define PCI_STATUS_DEVSEL_MASK 0x06000000 85#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 86#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 87#define PCI_STATUS_MASTER_ABORT 0x20000000 88#define PCI_STATUS_SPECIAL_ERROR 0x40000000 89#define PCI_STATUS_PARITY_DETECT 0x80000000 90 91/* 92 * PCI Class and Revision Register; defines type and revision of device. 93 */ 94#define PCI_CLASS_REG 0x08 95 96typedef u_int8_t pci_class_t; 97typedef u_int8_t pci_subclass_t; 98typedef u_int8_t pci_interface_t; 99typedef u_int8_t pci_revision_t; 100 101#define PCI_CLASS_SHIFT 24 102#define PCI_CLASS_MASK 0xff 103#define PCI_CLASS(cr) \ 104 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 105 106#define PCI_SUBCLASS_SHIFT 16 107#define PCI_SUBCLASS_MASK 0xff 108#define PCI_SUBCLASS(cr) \ 109 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 110 111#define PCI_INTERFACE_SHIFT 8 112#define PCI_INTERFACE_MASK 0xff 113#define PCI_INTERFACE(cr) \ 114 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 115 116#define PCI_REVISION_SHIFT 0 117#define PCI_REVISION_MASK 0xff 118#define PCI_REVISION(cr) \ 119 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 120 121/* base classes */ 122#define PCI_CLASS_PREHISTORIC 0x00 123#define PCI_CLASS_MASS_STORAGE 0x01 124#define PCI_CLASS_NETWORK 0x02 125#define PCI_CLASS_DISPLAY 0x03 126#define PCI_CLASS_MULTIMEDIA 0x04 127#define PCI_CLASS_MEMORY 0x05 128#define PCI_CLASS_BRIDGE 0x06 129#define PCI_CLASS_COMMUNICATIONS 0x07 130#define PCI_CLASS_SYSTEM 0x08 131#define PCI_CLASS_INPUT 0x09 132#define PCI_CLASS_DOCK 0x0a 133#define PCI_CLASS_PROCESSOR 0x0b 134#define PCI_CLASS_SERIALBUS 0x0c 135#define PCI_CLASS_UNDEFINED 0xff 136 137/* 0x00 prehistoric subclasses */ 138#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 139#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 140 141/* 0x01 mass storage subclasses */ 142#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 143#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 144#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 145#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 146#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 147#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 148 149/* 0x02 network subclasses */ 150#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 151#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 152#define PCI_SUBCLASS_NETWORK_FDDI 0x02 153#define PCI_SUBCLASS_NETWORK_ATM 0x03 154#define PCI_SUBCLASS_NETWORK_MISC 0x80 155 156/* 0x03 display subclasses */ 157#define PCI_SUBCLASS_DISPLAY_VGA 0x00 158#define PCI_SUBCLASS_DISPLAY_XGA 0x01 159#define PCI_SUBCLASS_DISPLAY_MISC 0x80 160 161/* 0x04 multimedia subclasses */ 162#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 163#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 164#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 165 166/* 0x05 memory subclasses */ 167#define PCI_SUBCLASS_MEMORY_RAM 0x00 168#define PCI_SUBCLASS_MEMORY_FLASH 0x01 169#define PCI_SUBCLASS_MEMORY_MISC 0x80 170 171/* 0x06 bridge subclasses */ 172#define PCI_SUBCLASS_BRIDGE_HOST 0x00 173#define PCI_SUBCLASS_BRIDGE_ISA 0x01 174#define PCI_SUBCLASS_BRIDGE_EISA 0x02 175#define PCI_SUBCLASS_BRIDGE_MC 0x03 176#define PCI_SUBCLASS_BRIDGE_PCI 0x04 177#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 178#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 179#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 180#define PCI_SUBCLASS_BRIDGE_MISC 0x80 181 182/* 0x07 communications subclasses */ 183#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 184#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 185#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 186 187/* 0x08 system subclasses */ 188#define PCI_SUBCLASS_SYSTEM_PIC 0x00 189#define PCI_SUBCLASS_SYSTEM_DMA 0x01 190#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 191#define PCI_SUBCLASS_SYSTEM_RTC 0x03 192#define PCI_SUBCLASS_SYSTEM_MISC 0x80 193 194/* 0x09 input subclasses */ 195#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 196#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 197#define PCI_SUBCLASS_INPUT_MOUSE 0x02 198#define PCI_SUBCLASS_INPUT_MISC 0x80 199 200/* 0x0a dock subclasses */ 201#define PCI_SUBCLASS_DOCK_GENERIC 0x00 202#define PCI_SUBCLASS_DOCK_MISC 0x80 203 204/* 0x0b processor subclasses */ 205#define PCI_SUBCLASS_PROCESSOR_386 0x00 206#define PCI_SUBCLASS_PROCESSOR_486 0x01 207#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 208#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 209#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 210#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 211 212/* 0x0c serial bus subclasses */ 213#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 214#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 215#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 216#define PCI_SUBCLASS_SERIALBUS_USB 0x03 217#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 218 219/* 220 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 221 */ 222#define PCI_BHLC_REG 0x0c 223 224#define PCI_BIST_SHIFT 24 225#define PCI_BIST_MASK 0xff 226#define PCI_BIST(bhlcr) \ 227 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 228 229#define PCI_HDRTYPE_SHIFT 16 230#define PCI_HDRTYPE_MASK 0xff 231#define PCI_HDRTYPE(bhlcr) \ 232 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 233 234#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 235 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 236 237#define PCI_LATTIMER_SHIFT 8 238#define PCI_LATTIMER_MASK 0xff 239#define PCI_LATTIMER(bhlcr) \ 240 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 241 242#define PCI_CACHELINE_SHIFT 0 243#define PCI_CACHELINE_MASK 0xff 244#define PCI_CACHELINE(bhlcr) \ 245 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 246 247/* config registers for header type 0 devices */ 248 249#define PCI_MAPS 0x10 250#define PCI_CARDBUSCIS 0x28 251#define PCI_SUBVEND_0 0x2c 252#define PCI_SUBDEV_0 0x2e 253#define PCI_INTLINE 0x3c 254#define PCI_INTPIN 0x3d 255#define PCI_MINGNT 0x3e 256#define PCI_MAXLAT 0x3f 257 258/* config registers for header type 1 devices */ 259 260#define PCI_SECSTAT_1 0 /**/ 261 262#define PCI_PRIBUS_1 0x18 263#define PCI_SECBUS_1 0x19 264#define PCI_SUBBUS_1 0x1a 265#define PCI_SECLAT_1 0x1b 266 267#define PCI_IOBASEL_1 0x1c 268#define PCI_IOLIMITL_1 0x1d 269#define PCI_IOBASEH_1 0 /**/ 270#define PCI_IOLIMITH_1 0 /**/ 271 272#define PCI_MEMBASE_1 0x20 273#define PCI_MEMLIMIT_1 0x22 274 275#define PCI_PMBASEL_1 0x24 276#define PCI_PMLIMITL_1 0x26 277#define PCI_PMBASEH_1 0 /**/ 278#define PCI_PMLIMITH_1 0 /**/ 279 280#define PCI_BRIDGECTL_1 0 /**/ 281 282#define PCI_SUBVEND_1 0x34 283#define PCI_SUBDEV_1 0x36 284 285/* config registers for header type 2 devices */ 286 287#define PCI_SECSTAT_2 0x16 288 289#define PCI_PRIBUS_2 0x18 290#define PCI_SECBUS_2 0x19 291#define PCI_SUBBUS_2 0x1a 292#define PCI_SECLAT_2 0x1b 293 294#define PCI_MEMBASE0_2 0x1c 295#define PCI_MEMLIMIT0_2 0x20 296#define PCI_MEMBASE1_2 0x24 297#define PCI_MEMLIMIT1_2 0x28 298#define PCI_IOBASE0_2 0x2c 299#define PCI_IOLIMIT0_2 0x30 300#define PCI_IOBASE1_2 0x34 301#define PCI_IOLIMIT1_2 0x38 302 303#define PCI_BRIDGECTL_2 0x3e 304 305#define PCI_SUBVEND_2 0x40 306#define PCI_SUBDEV_2 0x42 307 308#define PCI_PCCARDIF_2 0x44 309 310/* 311 * Mapping registers 312 */ 313#define PCI_MAPREG_START 0x10 314#define PCI_MAPREG_END 0x28 315 316#define PCI_MAPREG_TYPE(mr) \ 317 ((mr) & PCI_MAPREG_TYPE_MASK) 318#define PCI_MAPREG_TYPE_MASK 0x00000001 319 320#define PCI_MAPREG_TYPE_MEM 0x00000000 321#define PCI_MAPREG_TYPE_IO 0x00000001 322 323#define PCI_MAPREG_MEM_TYPE(mr) \ 324 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 325#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 326 327#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 328#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 329#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 330 331#define PCI_MAPREG_MEM_CACHEABLE(mr) \ 332 (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0) 333#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008 334 335#define PCI_MAPREG_MEM_ADDR(mr) \ 336 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 337#define PCI_MAPREG_MEM_SIZE(mr) \ 338 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 339#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 340 341#define PCI_MAPREG_IO_ADDR(mr) \ 342 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 343#define PCI_MAPREG_IO_SIZE(mr) \ 344 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 345#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 346 347/* 348 * Interrupt Configuration Register; contains interrupt pin and line. 349 */ 350#define PCI_INTERRUPT_REG 0x3c 351 352typedef u_int8_t pci_intr_pin_t; 353typedef u_int8_t pci_intr_line_t; 354 355#define PCI_INTERRUPT_PIN_SHIFT 8 356#define PCI_INTERRUPT_PIN_MASK 0xff 357#define PCI_INTERRUPT_PIN(icr) \ 358 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 359 360#define PCI_INTERRUPT_LINE_SHIFT 0 361#define PCI_INTERRUPT_LINE_MASK 0xff 362#define PCI_INTERRUPT_LINE(icr) \ 363 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 364 365#define PCI_INTERRUPT_PIN_NONE 0x00 366#define PCI_INTERRUPT_PIN_A 0x01 367#define PCI_INTERRUPT_PIN_B 0x02 368#define PCI_INTERRUPT_PIN_C 0x03 369#define PCI_INTERRUPT_PIN_D 0x04 370 371#endif /* _DEV_PCI_PCIREG_H_ */ 372