pcireg.h revision 1.49
1/* $OpenBSD: pcireg.h,v 1.49 2016/05/04 14:30:00 kettenis Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43#define PCI_CONFIG_SPACE_SIZE 0x100 44#define PCIE_CONFIG_SPACE_SIZE 0x1000 45 46/* 47 * Device identification register; contains a vendor ID and a device ID. 48 */ 49#define PCI_ID_REG 0x00 50 51typedef u_int16_t pci_vendor_id_t; 52typedef u_int16_t pci_product_id_t; 53 54#define PCI_VENDOR_SHIFT 0 55#define PCI_VENDOR_MASK 0xffff 56#define PCI_VENDOR(id) \ 57 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 58 59#define PCI_PRODUCT_SHIFT 16 60#define PCI_PRODUCT_MASK 0xffff 61#define PCI_PRODUCT(id) \ 62 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 63 64#define PCI_ID_CODE(vid,pid) \ 65 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 66 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 67 68/* 69 * Command and status register. 70 */ 71#define PCI_COMMAND_STATUS_REG 0x04 72 73#define PCI_COMMAND_IO_ENABLE 0x00000001 74#define PCI_COMMAND_MEM_ENABLE 0x00000002 75#define PCI_COMMAND_MASTER_ENABLE 0x00000004 76#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 77#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 78#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 79#define PCI_COMMAND_PARITY_ENABLE 0x00000040 80#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 81#define PCI_COMMAND_SERR_ENABLE 0x00000100 82#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 83#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 84 85#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 86#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 87#define PCI_STATUS_UDF_SUPPORT 0x00400000 88#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 89#define PCI_STATUS_PARITY_ERROR 0x01000000 90#define PCI_STATUS_DEVSEL_FAST 0x00000000 91#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 92#define PCI_STATUS_DEVSEL_SLOW 0x04000000 93#define PCI_STATUS_DEVSEL_MASK 0x06000000 94#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 95#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 96#define PCI_STATUS_MASTER_ABORT 0x20000000 97#define PCI_STATUS_SPECIAL_ERROR 0x40000000 98#define PCI_STATUS_PARITY_DETECT 0x80000000 99 100#define PCI_COMMAND_STATUS_BITS \ 101 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 102 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 103 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 104 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 105 "\037SPECIAL_ERROR\040PARITY_DETECT") 106/* 107 * PCI Class and Revision Register; defines type and revision of device. 108 */ 109#define PCI_CLASS_REG 0x08 110 111typedef u_int8_t pci_class_t; 112typedef u_int8_t pci_subclass_t; 113typedef u_int8_t pci_interface_t; 114typedef u_int8_t pci_revision_t; 115 116#define PCI_CLASS_SHIFT 24 117#define PCI_CLASS_MASK 0xff 118#define PCI_CLASS(cr) \ 119 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 120 121#define PCI_SUBCLASS_SHIFT 16 122#define PCI_SUBCLASS_MASK 0xff 123#define PCI_SUBCLASS(cr) \ 124 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 125 126#define PCI_INTERFACE_SHIFT 8 127#define PCI_INTERFACE_MASK 0xff 128#define PCI_INTERFACE(cr) \ 129 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 130 131#define PCI_REVISION_SHIFT 0 132#define PCI_REVISION_MASK 0xff 133#define PCI_REVISION(cr) \ 134 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 135 136/* base classes */ 137#define PCI_CLASS_PREHISTORIC 0x00 138#define PCI_CLASS_MASS_STORAGE 0x01 139#define PCI_CLASS_NETWORK 0x02 140#define PCI_CLASS_DISPLAY 0x03 141#define PCI_CLASS_MULTIMEDIA 0x04 142#define PCI_CLASS_MEMORY 0x05 143#define PCI_CLASS_BRIDGE 0x06 144#define PCI_CLASS_COMMUNICATIONS 0x07 145#define PCI_CLASS_SYSTEM 0x08 146#define PCI_CLASS_INPUT 0x09 147#define PCI_CLASS_DOCK 0x0a 148#define PCI_CLASS_PROCESSOR 0x0b 149#define PCI_CLASS_SERIALBUS 0x0c 150#define PCI_CLASS_WIRELESS 0x0d 151#define PCI_CLASS_I2O 0x0e 152#define PCI_CLASS_SATCOM 0x0f 153#define PCI_CLASS_CRYPTO 0x10 154#define PCI_CLASS_DASP 0x11 155#define PCI_CLASS_UNDEFINED 0xff 156 157/* 0x00 prehistoric subclasses */ 158#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 159#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 160 161/* 0x01 mass storage subclasses */ 162#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 163#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 164#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 165#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 166#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 167#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 168#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 169#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 170#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 171#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 172 173/* 0x02 network subclasses */ 174#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 175#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 176#define PCI_SUBCLASS_NETWORK_FDDI 0x02 177#define PCI_SUBCLASS_NETWORK_ATM 0x03 178#define PCI_SUBCLASS_NETWORK_ISDN 0x04 179#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 180#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 181#define PCI_SUBCLASS_NETWORK_MISC 0x80 182 183/* 0x03 display subclasses */ 184#define PCI_SUBCLASS_DISPLAY_VGA 0x00 185#define PCI_SUBCLASS_DISPLAY_XGA 0x01 186#define PCI_SUBCLASS_DISPLAY_3D 0x02 187#define PCI_SUBCLASS_DISPLAY_MISC 0x80 188 189/* 0x04 multimedia subclasses */ 190#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 191#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 192#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 193#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 194#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 195 196/* 0x05 memory subclasses */ 197#define PCI_SUBCLASS_MEMORY_RAM 0x00 198#define PCI_SUBCLASS_MEMORY_FLASH 0x01 199#define PCI_SUBCLASS_MEMORY_MISC 0x80 200 201/* 0x06 bridge subclasses */ 202#define PCI_SUBCLASS_BRIDGE_HOST 0x00 203#define PCI_SUBCLASS_BRIDGE_ISA 0x01 204#define PCI_SUBCLASS_BRIDGE_EISA 0x02 205#define PCI_SUBCLASS_BRIDGE_MC 0x03 206#define PCI_SUBCLASS_BRIDGE_PCI 0x04 207#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 208#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 209#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 210#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 211#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 212#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 213#define PCI_SUBCLASS_BRIDGE_MISC 0x80 214 215/* 0x07 communications subclasses */ 216#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 217#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 218#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 219#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 220#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 221#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 222#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 223 224/* 0x08 system subclasses */ 225#define PCI_SUBCLASS_SYSTEM_PIC 0x00 226#define PCI_SUBCLASS_SYSTEM_DMA 0x01 227#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 228#define PCI_SUBCLASS_SYSTEM_RTC 0x03 229#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 230#define PCI_SUBCLASS_SYSTEM_SDHC 0x05 231#define PCI_SUBCLASS_SYSTEM_MISC 0x80 232 233/* 0x09 input subclasses */ 234#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 235#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 236#define PCI_SUBCLASS_INPUT_MOUSE 0x02 237#define PCI_SUBCLASS_INPUT_SCANNER 0x03 238#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 239#define PCI_SUBCLASS_INPUT_MISC 0x80 240 241/* 0x0a dock subclasses */ 242#define PCI_SUBCLASS_DOCK_GENERIC 0x00 243#define PCI_SUBCLASS_DOCK_MISC 0x80 244 245/* 0x0b processor subclasses */ 246#define PCI_SUBCLASS_PROCESSOR_386 0x00 247#define PCI_SUBCLASS_PROCESSOR_486 0x01 248#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 249#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 250#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 251#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 252#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 253 254/* 0x0c serial bus subclasses */ 255#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 256#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 257#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 258#define PCI_SUBCLASS_SERIALBUS_USB 0x03 259#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 260#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 261#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 262#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 263#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 264#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 265 266/* 0x0d wireless subclasses */ 267#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 268#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 269#define PCI_SUBCLASS_WIRELESS_RF 0x10 270#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 271#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 272#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 273#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 274#define PCI_SUBCLASS_WIRELESS_MISC 0x80 275 276/* 0x0e I2O (Intelligent I/O) subclasses */ 277#define PCI_SUBCLASS_I2O_STANDARD 0x00 278 279/* 0x0f satellite communication subclasses */ 280/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 281#define PCI_SUBCLASS_SATCOM_TV 0x01 282#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 283#define PCI_SUBCLASS_SATCOM_VOICE 0x03 284#define PCI_SUBCLASS_SATCOM_DATA 0x04 285 286/* 0x10 encryption/decryption subclasses */ 287#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 288#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 289#define PCI_SUBCLASS_CRYPTO_MISC 0x80 290 291/* 0x11 data acquisition and signal processing subclasses */ 292#define PCI_SUBCLASS_DASP_DPIO 0x00 293#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 294#define PCI_SUBCLASS_DASP_SYNC 0x10 295#define PCI_SUBCLASS_DASP_MGMT 0x20 296#define PCI_SUBCLASS_DASP_MISC 0x80 297 298/* 299 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 300 */ 301#define PCI_BHLC_REG 0x0c 302 303#define PCI_BIST_SHIFT 24 304#define PCI_BIST_MASK 0xff 305#define PCI_BIST(bhlcr) \ 306 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 307 308#define PCI_HDRTYPE_SHIFT 16 309#define PCI_HDRTYPE_MASK 0xff 310#define PCI_HDRTYPE(bhlcr) \ 311 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 312 313#define PCI_HDRTYPE_TYPE(bhlcr) \ 314 (PCI_HDRTYPE(bhlcr) & 0x7f) 315#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 316 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 317 318#define PCI_LATTIMER_SHIFT 8 319#define PCI_LATTIMER_MASK 0xff 320#define PCI_LATTIMER(bhlcr) \ 321 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 322 323#define PCI_CACHELINE_SHIFT 0 324#define PCI_CACHELINE_MASK 0xff 325#define PCI_CACHELINE(bhlcr) \ 326 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 327 328/* config registers for header type 0 devices */ 329 330#define PCI_MAPS 0x10 331#define PCI_CARDBUSCIS 0x28 332#define PCI_SUBVEND_0 0x2c 333#define PCI_SUBDEV_0 0x2e 334#define PCI_INTLINE 0x3c 335#define PCI_INTPIN 0x3d 336#define PCI_MINGNT 0x3e 337#define PCI_MAXLAT 0x3f 338 339/* config registers for header type 1 devices */ 340 341#define PCI_SECSTAT_1 0 /**/ 342 343#define PCI_PRIBUS_1 0x18 344#define PCI_SECBUS_1 0x19 345#define PCI_SUBBUS_1 0x1a 346#define PCI_SECLAT_1 0x1b 347 348#define PCI_IOBASEL_1 0x1c 349#define PCI_IOLIMITL_1 0x1d 350#define PCI_IOBASEH_1 0 /**/ 351#define PCI_IOLIMITH_1 0 /**/ 352 353#define PCI_MEMBASE_1 0x20 354#define PCI_MEMLIMIT_1 0x22 355 356#define PCI_PMBASEL_1 0x24 357#define PCI_PMLIMITL_1 0x26 358#define PCI_PMBASEH_1 0 /**/ 359#define PCI_PMLIMITH_1 0 /**/ 360 361#define PCI_BRIDGECTL_1 0 /**/ 362 363#define PCI_SUBVEND_1 0x34 364#define PCI_SUBDEV_1 0x36 365 366/* config registers for header type 2 devices */ 367 368#define PCI_SECSTAT_2 0x16 369 370#define PCI_PRIBUS_2 0x18 371#define PCI_SECBUS_2 0x19 372#define PCI_SUBBUS_2 0x1a 373#define PCI_SECLAT_2 0x1b 374 375#define PCI_MEMBASE0_2 0x1c 376#define PCI_MEMLIMIT0_2 0x20 377#define PCI_MEMBASE1_2 0x24 378#define PCI_MEMLIMIT1_2 0x28 379#define PCI_IOBASE0_2 0x2c 380#define PCI_IOLIMIT0_2 0x30 381#define PCI_IOBASE1_2 0x34 382#define PCI_IOLIMIT1_2 0x38 383 384#define PCI_BRIDGECTL_2 0x3e 385 386#define PCI_SUBVEND_2 0x40 387#define PCI_SUBDEV_2 0x42 388 389#define PCI_PCCARDIF_2 0x44 390 391/* 392 * Mapping registers 393 */ 394#define PCI_MAPREG_START 0x10 395#define PCI_MAPREG_END 0x28 396#define PCI_MAPREG_PPB_END 0x18 397#define PCI_MAPREG_PCB_END 0x14 398 399#define PCI_MAPREG_TYPE(mr) \ 400 ((mr) & PCI_MAPREG_TYPE_MASK) 401#define PCI_MAPREG_TYPE_MASK 0x00000001 402 403#define PCI_MAPREG_TYPE_MEM 0x00000000 404#define PCI_MAPREG_TYPE_IO 0x00000001 405 406#define PCI_MAPREG_MEM_TYPE(mr) \ 407 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 408#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 409 410#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 411#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 412#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 413 414#define _PCI_MAPREG_TYPEBITS(reg) \ 415 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 416 reg & PCI_MAPREG_TYPE_MASK : \ 417 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 418 419#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 420 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 421#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 422 423#define PCI_MAPREG_MEM_ADDR(mr) \ 424 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 425#define PCI_MAPREG_MEM_SIZE(mr) \ 426 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 427#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 428 429#define PCI_MAPREG_MEM64_ADDR(mr) \ 430 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 431#define PCI_MAPREG_MEM64_SIZE(mr) \ 432 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 433#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 434 435#define PCI_MAPREG_IO_ADDR(mr) \ 436 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 437#define PCI_MAPREG_IO_SIZE(mr) \ 438 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 439#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 440 441/* 442 * Cardbus CIS pointer (PCI rev. 2.1) 443 */ 444#define PCI_CARDBUS_CIS_REG 0x28 445 446/* 447 * Subsystem identification register; contains a vendor ID and a device ID. 448 * Types/macros for PCI_ID_REG apply. 449 * (PCI rev. 2.1) 450 */ 451#define PCI_SUBSYS_ID_REG 0x2c 452 453/* 454 * Expansion ROM Base Address register 455 * (PCI rev. 2.0) 456 */ 457#define PCI_ROM_REG 0x30 458 459#define PCI_ROM_ENABLE 0x00000001 460#define PCI_ROM_ADDR_MASK 0xfffff800 461#define PCI_ROM_ADDR(mr) \ 462 ((mr) & PCI_ROM_ADDR_MASK) 463#define PCI_ROM_SIZE(mr) \ 464 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 465 466/* 467 * capabilities link list (PCI rev. 2.2) 468 */ 469#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 470#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 471#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 472#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 473#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 474 475#define PCI_CAP_RESERVED 0x00 476#define PCI_CAP_PWRMGMT 0x01 477#define PCI_CAP_AGP 0x02 478#define PCI_CAP_VPD 0x03 479#define PCI_CAP_SLOTID 0x04 480#define PCI_CAP_MSI 0x05 481#define PCI_CAP_CPCI_HOTSWAP 0x06 482#define PCI_CAP_PCIX 0x07 483#define PCI_CAP_HT 0x08 484#define PCI_CAP_VENDSPEC 0x09 485#define PCI_CAP_DEBUGPORT 0x0a 486#define PCI_CAP_CPCI_RSRCCTL 0x0b 487#define PCI_CAP_HOTPLUG 0x0c 488#define PCI_CAP_AGP8 0x0e 489#define PCI_CAP_SECURE 0x0f 490#define PCI_CAP_PCIEXPRESS 0x10 491#define PCI_CAP_MSIX 0x11 492#define PCI_CAP_SATA 0x12 493 494/* 495 * Vital Product Data; access via capability pointer (PCI rev 2.2). 496 */ 497#define PCI_VPD_ADDRESS_MASK 0x7fff 498#define PCI_VPD_ADDRESS_SHIFT 16 499#define PCI_VPD_ADDRESS(ofs) \ 500 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 501#define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 502#define PCI_VPD_OPFLAG 0x80000000 503 504/* 505 * Message Signaled Interrups; access via capability pointer. 506 */ 507#define PCI_MSI_MC 0x00 508#define PCI_MSI_MC_C64 0x00800000 509#define PCI_MSI_MC_MME 0x00700000 510#define PCI_MSI_MC_MMC 0x000e0000 511#define PCI_MSI_MC_MSIE 0x00010000 512#define PCI_MSI_MA 0x04 513#define PCI_MSI_MAU32 0x08 514#define PCI_MSI_MD32 0x08 515#define PCI_MSI_MD64 0x0c 516 517/* 518 * Power Management Control Status Register; access via capability pointer. 519 */ 520#define PCI_PMCSR 0x04 521#define PCI_PMCSR_STATE_MASK 0x0003 522#define PCI_PMCSR_STATE_D0 0x0000 523#define PCI_PMCSR_STATE_D1 0x0001 524#define PCI_PMCSR_STATE_D2 0x0002 525#define PCI_PMCSR_STATE_D3 0x0003 526#define PCI_PMCSR_PME_STATUS 0x8000 527#define PCI_PMCSR_PME_EN 0x0100 528 529/* 530 * HyperTransport; access via capability pointer. 531 */ 532#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 533 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 534 535#define PCI_HT_CAP_SLAVE 0x00 536#define PCI_HT_CAP_HOST 0x04 537#define PCI_HT_CAP_INTR 0x10 538#define PCI_HT_CAP_MSI 0x15 539 540#define PCI_HT_MSI_ENABLED 0x00010000 541#define PCI_HT_MSI_FIXED 0x00020000 542 543#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 544 545#define PCI_HT_MSI_ADDR 0x04 546#define PCI_HT_MSI_ADDR_HI32 0x08 547 548#define PCI_HT_INTR_DATA 0x04 549 550/* 551 * PCI Express; access via capability pointer. 552 */ 553#define PCI_PCIE_XCAP 0x00 554#define PCI_PCIE_XCAP_SI 0x01000000 555#define PCI_PCIE_XCAP_VER(x) (((x) >> 16) & 0x0f) 556#define PCI_PCIE_DCAP 0x04 557#define PCI_PCIE_DCSR 0x08 558#define PCI_PCIE_DCSR_ERO 0x00000010 559#define PCI_PCIE_DCSR_ENS 0x00000800 560#define PCI_PCIE_DCSR_MPS 0x00007000 561#define PCI_PCIE_DCSR_CEE 0x00010000 562#define PCI_PCIE_DCSR_NFE 0x00020000 563#define PCI_PCIE_DCSR_FEE 0x00040000 564#define PCI_PCIE_DCSR_URE 0x00080000 565#define PCI_PCIE_LCAP 0x0c 566#define PCI_PCIE_LCSR 0x10 567#define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 568#define PCI_PCIE_LCSR_ASPM_L1 0x00000002 569#define PCI_PCIE_LCSR_ES 0x00000080 570#define PCI_PCIE_SLCAP 0x14 571#define PCI_PCIE_SLCAP_ABP 0x00000001 572#define PCI_PCIE_SLCAP_PCP 0x00000002 573#define PCI_PCIE_SLCAP_MSP 0x00000004 574#define PCI_PCIE_SLCAP_AIP 0x00000008 575#define PCI_PCIE_SLCAP_PIP 0x00000010 576#define PCI_PCIE_SLCAP_HPS 0x00000020 577#define PCI_PCIE_SLCAP_HPC 0x00000040 578#define PCI_PCIE_SLCSR 0x18 579#define PCI_PCIE_SLCSR_ABE 0x00000001 580#define PCI_PCIE_SLCSR_PFE 0x00000002 581#define PCI_PCIE_SLCSR_MSE 0x00000004 582#define PCI_PCIE_SLCSR_PDE 0x00000008 583#define PCI_PCIE_SLCSR_CCE 0x00000010 584#define PCI_PCIE_SLCSR_HPE 0x00000020 585#define PCI_PCIE_SLCSR_ABP 0x00010000 586#define PCI_PCIE_SLCSR_PFD 0x00020000 587#define PCI_PCIE_SLCSR_MSC 0x00040000 588#define PCI_PCIE_SLCSR_PDC 0x00080000 589#define PCI_PCIE_SLCSR_CC 0x00100000 590#define PCI_PCIE_SLCSR_MS 0x00200000 591#define PCI_PCIE_SLCSR_PDS 0x00400000 592#define PCI_PCIE_SLCSR_LACS 0x01000000 593#define PCI_PCIE_RCSR 0x1c 594#define PCI_PCIE_LCAP2 0x2c 595 596/* 597 * Extended Message Signaled Interrups; access via capability pointer. 598 */ 599#define PCI_MSIX_MC_MSIXE 0x80000000 600#define PCI_MSIX_MC_TBLSZ 0x000007ff 601#define PCI_MSIX_TABLE 0x04 602#define PCI_MSIX_TABLE_BIR 0x00000007 603#define PCI_MSIX_TABLE_OFF ~(PCI_MSIX_TABLE_BIR) 604 605#define PCI_MSIX_MA(i) ((i) * 16 + 0) 606#define PCI_MSIX_MAU32(i) ((i) * 16 + 0) 607#define PCI_MSIX_MD(i) ((i) * 16 + 8) 608#define PCI_MSIX_VC(i) ((i) * 16 + 12) 609#define PCI_MSIX_VC_MASK 0x00000001 610 611/* 612 * Interrupt Configuration Register; contains interrupt pin and line. 613 */ 614#define PCI_INTERRUPT_REG 0x3c 615 616typedef u_int8_t pci_intr_pin_t; 617typedef u_int8_t pci_intr_line_t; 618 619#define PCI_INTERRUPT_PIN_SHIFT 8 620#define PCI_INTERRUPT_PIN_MASK 0xff 621#define PCI_INTERRUPT_PIN(icr) \ 622 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 623 624#define PCI_INTERRUPT_LINE_SHIFT 0 625#define PCI_INTERRUPT_LINE_MASK 0xff 626#define PCI_INTERRUPT_LINE(icr) \ 627 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 628 629#define PCI_MIN_GNT_SHIFT 16 630#define PCI_MIN_GNT_MASK 0xff 631#define PCI_MIN_GNT(icr) \ 632 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 633 634#define PCI_MAX_LAT_SHIFT 24 635#define PCI_MAX_LAT_MASK 0xff 636#define PCI_MAX_LAT(icr) \ 637 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 638 639#define PCI_INTERRUPT_PIN_NONE 0x00 640#define PCI_INTERRUPT_PIN_A 0x01 641#define PCI_INTERRUPT_PIN_B 0x02 642#define PCI_INTERRUPT_PIN_C 0x03 643#define PCI_INTERRUPT_PIN_D 0x04 644#define PCI_INTERRUPT_PIN_MAX 0x04 645 646/* 647 * Vital Product Data resource tags. 648 */ 649struct pci_vpd_smallres { 650 uint8_t vpdres_byte0; /* length of data + tag */ 651 /* Actual data. */ 652} __packed; 653 654struct pci_vpd_largeres { 655 uint8_t vpdres_byte0; 656 uint8_t vpdres_len_lsb; /* length of data only */ 657 uint8_t vpdres_len_msb; 658 /* Actual data. */ 659} __packed; 660 661#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 662 663#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 664#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 665 666#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 667 668#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 669#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 670#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 671 672#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 673#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 674 675struct pci_vpd { 676 uint8_t vpd_key0; 677 uint8_t vpd_key1; 678 uint8_t vpd_len; /* length of data only */ 679 /* Actual data. */ 680} __packed; 681 682/* 683 * Recommended VPD fields: 684 * 685 * PN Part number of assembly 686 * FN FRU part number 687 * EC EC level of assembly 688 * MN Manufacture ID 689 * SN Serial Number 690 * 691 * Conditionally recommended VPD fields: 692 * 693 * LI Load ID 694 * RL ROM Level 695 * RM Alterable ROM Level 696 * NA Network Address 697 * DD Device Driver Level 698 * DG Diagnostic Level 699 * LL Loadable Microcode Level 700 * VI Vendor ID/Device ID 701 * FU Function Number 702 * SI Subsystem Vendor ID/Subsystem ID 703 * 704 * Additional VPD fields: 705 * 706 * Z0-ZZ User/Product Specific 707 */ 708 709#endif /* _DEV_PCI_PCIREG_H_ */ 710