pcireg.h revision 1.24
1/* $OpenBSD: pcireg.h,v 1.24 2003/10/06 16:04:45 fgsch Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61/* 62 * Command and status register. 63 */ 64#define PCI_COMMAND_STATUS_REG 0x04 65 66#define PCI_COMMAND_IO_ENABLE 0x00000001 67#define PCI_COMMAND_MEM_ENABLE 0x00000002 68#define PCI_COMMAND_MASTER_ENABLE 0x00000004 69#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 70#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 71#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 72#define PCI_COMMAND_PARITY_ENABLE 0x00000040 73#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 74#define PCI_COMMAND_SERR_ENABLE 0x00000100 75#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 76 77#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 78#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 79#define PCI_STATUS_UDF_SUPPORT 0x00400000 80#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 81#define PCI_STATUS_PARITY_ERROR 0x01000000 82#define PCI_STATUS_DEVSEL_FAST 0x00000000 83#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 84#define PCI_STATUS_DEVSEL_SLOW 0x04000000 85#define PCI_STATUS_DEVSEL_MASK 0x06000000 86#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 87#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 88#define PCI_STATUS_MASTER_ABORT 0x20000000 89#define PCI_STATUS_SPECIAL_ERROR 0x40000000 90#define PCI_STATUS_PARITY_DETECT 0x80000000 91 92#define PCI_COMMAND_STATUS_BITS \ 93 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 94 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 95 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 96 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 97 "\037SPECIAL_ERROR\040PARITY_DETECT") 98/* 99 * PCI Class and Revision Register; defines type and revision of device. 100 */ 101#define PCI_CLASS_REG 0x08 102 103typedef u_int8_t pci_class_t; 104typedef u_int8_t pci_subclass_t; 105typedef u_int8_t pci_interface_t; 106typedef u_int8_t pci_revision_t; 107 108#define PCI_CLASS_SHIFT 24 109#define PCI_CLASS_MASK 0xff 110#define PCI_CLASS(cr) \ 111 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 112 113#define PCI_SUBCLASS_SHIFT 16 114#define PCI_SUBCLASS_MASK 0xff 115#define PCI_SUBCLASS(cr) \ 116 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 117 118#define PCI_INTERFACE_SHIFT 8 119#define PCI_INTERFACE_MASK 0xff 120#define PCI_INTERFACE(cr) \ 121 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 122 123#define PCI_REVISION_SHIFT 0 124#define PCI_REVISION_MASK 0xff 125#define PCI_REVISION(cr) \ 126 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 127 128/* base classes */ 129#define PCI_CLASS_PREHISTORIC 0x00 130#define PCI_CLASS_MASS_STORAGE 0x01 131#define PCI_CLASS_NETWORK 0x02 132#define PCI_CLASS_DISPLAY 0x03 133#define PCI_CLASS_MULTIMEDIA 0x04 134#define PCI_CLASS_MEMORY 0x05 135#define PCI_CLASS_BRIDGE 0x06 136#define PCI_CLASS_COMMUNICATIONS 0x07 137#define PCI_CLASS_SYSTEM 0x08 138#define PCI_CLASS_INPUT 0x09 139#define PCI_CLASS_DOCK 0x0a 140#define PCI_CLASS_PROCESSOR 0x0b 141#define PCI_CLASS_SERIALBUS 0x0c 142#define PCI_CLASS_WIRELESS 0x0d 143#define PCI_CLASS_I2O 0x0e 144#define PCI_CLASS_SATCOM 0x0f 145#define PCI_CLASS_CRYPTO 0x10 146#define PCI_CLASS_DASP 0x11 147#define PCI_CLASS_UNDEFINED 0xff 148 149/* 0x00 prehistoric subclasses */ 150#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 151#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 152 153/* 0x01 mass storage subclasses */ 154#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 155#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 156#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 157#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 158#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 159#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 160#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 161#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 162 163/* 0x02 network subclasses */ 164#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 165#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 166#define PCI_SUBCLASS_NETWORK_FDDI 0x02 167#define PCI_SUBCLASS_NETWORK_ATM 0x03 168#define PCI_SUBCLASS_NETWORK_ISDN 0x04 169#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 170#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 171#define PCI_SUBCLASS_NETWORK_MISC 0x80 172 173/* 0x03 display subclasses */ 174#define PCI_SUBCLASS_DISPLAY_VGA 0x00 175#define PCI_SUBCLASS_DISPLAY_XGA 0x01 176#define PCI_SUBCLASS_DISPLAY_3D 0x02 177#define PCI_SUBCLASS_DISPLAY_MISC 0x80 178 179/* 0x04 multimedia subclasses */ 180#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 181#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 182#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 183#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 184 185/* 0x05 memory subclasses */ 186#define PCI_SUBCLASS_MEMORY_RAM 0x00 187#define PCI_SUBCLASS_MEMORY_FLASH 0x01 188#define PCI_SUBCLASS_MEMORY_MISC 0x80 189 190/* 0x06 bridge subclasses */ 191#define PCI_SUBCLASS_BRIDGE_HOST 0x00 192#define PCI_SUBCLASS_BRIDGE_ISA 0x01 193#define PCI_SUBCLASS_BRIDGE_EISA 0x02 194#define PCI_SUBCLASS_BRIDGE_MC 0x03 195#define PCI_SUBCLASS_BRIDGE_PCI 0x04 196#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 197#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 198#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 199#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 200#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 201#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 202#define PCI_SUBCLASS_BRIDGE_MISC 0x80 203 204/* 0x07 communications subclasses */ 205#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 206#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 207#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 208#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 209#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 210#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 211#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 212 213/* 0x08 system subclasses */ 214#define PCI_SUBCLASS_SYSTEM_PIC 0x00 215#define PCI_SUBCLASS_SYSTEM_DMA 0x01 216#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 217#define PCI_SUBCLASS_SYSTEM_RTC 0x03 218#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 219#define PCI_SUBCLASS_SYSTEM_MISC 0x80 220 221/* 0x09 input subclasses */ 222#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 223#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 224#define PCI_SUBCLASS_INPUT_MOUSE 0x02 225#define PCI_SUBCLASS_INPUT_SCANNER 0x03 226#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 227#define PCI_SUBCLASS_INPUT_MISC 0x80 228 229/* 0x0a dock subclasses */ 230#define PCI_SUBCLASS_DOCK_GENERIC 0x00 231#define PCI_SUBCLASS_DOCK_MISC 0x80 232 233/* 0x0b processor subclasses */ 234#define PCI_SUBCLASS_PROCESSOR_386 0x00 235#define PCI_SUBCLASS_PROCESSOR_486 0x01 236#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 237#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 238#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 239#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 240#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 241 242/* 0x0c serial bus subclasses */ 243#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 244#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 245#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 246#define PCI_SUBCLASS_SERIALBUS_USB 0x03 247#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 248#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 249#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 250#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 251#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 252#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 253 254/* 0x0d wireless subclasses */ 255#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 256#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 257#define PCI_SUBCLASS_WIRELESS_RF 0x10 258#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 259#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 260#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 261#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 262#define PCI_SUBCLASS_WIRELESS_MISC 0x80 263 264/* 0x0e I2O (Intelligent I/O) subclasses */ 265#define PCI_SUBCLASS_I2O_STANDARD 0x00 266 267/* 0x0f satellite communication subclasses */ 268/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 269#define PCI_SUBCLASS_SATCOM_TV 0x01 270#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 271#define PCI_SUBCLASS_SATCOM_VOICE 0x03 272#define PCI_SUBCLASS_SATCOM_DATA 0x04 273 274/* 0x10 encryption/decryption subclasses */ 275#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 276#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 277#define PCI_SUBCLASS_CRYPTO_MISC 0x80 278 279/* 0x11 data acquisition and signal processing subclasses */ 280#define PCI_SUBCLASS_DASP_DPIO 0x00 281#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 282#define PCI_SUBCLASS_DASP_SYNC 0x10 283#define PCI_SUBCLASS_DASP_MGMT 0x20 284#define PCI_SUBCLASS_DASP_MISC 0x80 285 286/* 287 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 288 */ 289#define PCI_BHLC_REG 0x0c 290 291#define PCI_BIST_SHIFT 24 292#define PCI_BIST_MASK 0xff 293#define PCI_BIST(bhlcr) \ 294 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 295 296#define PCI_HDRTYPE_SHIFT 16 297#define PCI_HDRTYPE_MASK 0xff 298#define PCI_HDRTYPE(bhlcr) \ 299 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 300 301#define PCI_HDRTYPE_TYPE(bhlcr) \ 302 (PCI_HDRTYPE(bhlcr) & 0x7f) 303#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 304 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 305 306#define PCI_LATTIMER_SHIFT 8 307#define PCI_LATTIMER_MASK 0xff 308#define PCI_LATTIMER(bhlcr) \ 309 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 310 311#define PCI_CACHELINE_SHIFT 0 312#define PCI_CACHELINE_MASK 0xff 313#define PCI_CACHELINE(bhlcr) \ 314 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 315 316/* config registers for header type 0 devices */ 317 318#define PCI_MAPS 0x10 319#define PCI_CARDBUSCIS 0x28 320#define PCI_SUBVEND_0 0x2c 321#define PCI_SUBDEV_0 0x2e 322#define PCI_INTLINE 0x3c 323#define PCI_INTPIN 0x3d 324#define PCI_MINGNT 0x3e 325#define PCI_MAXLAT 0x3f 326 327/* config registers for header type 1 devices */ 328 329#define PCI_SECSTAT_1 0 /**/ 330 331#define PCI_PRIBUS_1 0x18 332#define PCI_SECBUS_1 0x19 333#define PCI_SUBBUS_1 0x1a 334#define PCI_SECLAT_1 0x1b 335 336#define PCI_IOBASEL_1 0x1c 337#define PCI_IOLIMITL_1 0x1d 338#define PCI_IOBASEH_1 0 /**/ 339#define PCI_IOLIMITH_1 0 /**/ 340 341#define PCI_MEMBASE_1 0x20 342#define PCI_MEMLIMIT_1 0x22 343 344#define PCI_PMBASEL_1 0x24 345#define PCI_PMLIMITL_1 0x26 346#define PCI_PMBASEH_1 0 /**/ 347#define PCI_PMLIMITH_1 0 /**/ 348 349#define PCI_BRIDGECTL_1 0 /**/ 350 351#define PCI_SUBVEND_1 0x34 352#define PCI_SUBDEV_1 0x36 353 354/* config registers for header type 2 devices */ 355 356#define PCI_SECSTAT_2 0x16 357 358#define PCI_PRIBUS_2 0x18 359#define PCI_SECBUS_2 0x19 360#define PCI_SUBBUS_2 0x1a 361#define PCI_SECLAT_2 0x1b 362 363#define PCI_MEMBASE0_2 0x1c 364#define PCI_MEMLIMIT0_2 0x20 365#define PCI_MEMBASE1_2 0x24 366#define PCI_MEMLIMIT1_2 0x28 367#define PCI_IOBASE0_2 0x2c 368#define PCI_IOLIMIT0_2 0x30 369#define PCI_IOBASE1_2 0x34 370#define PCI_IOLIMIT1_2 0x38 371 372#define PCI_BRIDGECTL_2 0x3e 373 374#define PCI_SUBVEND_2 0x40 375#define PCI_SUBDEV_2 0x42 376 377#define PCI_PCCARDIF_2 0x44 378 379/* 380 * Mapping registers 381 */ 382#define PCI_MAPREG_START 0x10 383#define PCI_MAPREG_END 0x28 384#define PCI_MAPREG_PPB_END 0x18 385#define PCI_MAPREG_PCB_END 0x14 386 387#define PCI_MAPREG_TYPE(mr) \ 388 ((mr) & PCI_MAPREG_TYPE_MASK) 389#define PCI_MAPREG_TYPE_MASK 0x00000001 390 391#define PCI_MAPREG_TYPE_MEM 0x00000000 392#define PCI_MAPREG_TYPE_IO 0x00000001 393 394#define PCI_MAPREG_MEM_TYPE(mr) \ 395 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 396#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 397 398#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 399#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 400#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 401 402#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 403 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 404#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 405 406#define PCI_MAPREG_MEM_ADDR(mr) \ 407 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 408#define PCI_MAPREG_MEM_SIZE(mr) \ 409 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 410#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 411 412#define PCI_MAPREG_MEM64_ADDR(mr) \ 413 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 414#define PCI_MAPREG_MEM64_SIZE(mr) \ 415 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 416#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0 417 418#define PCI_MAPREG_IO_ADDR(mr) \ 419 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 420#define PCI_MAPREG_IO_SIZE(mr) \ 421 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 422#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 423 424/* 425 * Cardbus CIS pointer (PCI rev. 2.1) 426 */ 427#define PCI_CARDBUS_CIS_REG 0x28 428 429/* 430 * Subsystem identification register; contains a vendor ID and a device ID. 431 * Types/macros for PCI_ID_REG apply. 432 * (PCI rev. 2.1) 433 */ 434#define PCI_SUBSYS_ID_REG 0x2c 435 436/* 437 * capabilities link list (PCI rev. 2.2) 438 */ 439#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 440#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 441#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 442#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 443#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 444 445#define PCI_CAP_RESERVED 0x00 446#define PCI_CAP_PWRMGMT 0x01 447#define PCI_CAP_AGP 0x02 448#define PCI_CAP_VPD 0x03 449#define PCI_CAP_SLOTID 0x04 450#define PCI_CAP_MSI 0x05 451#define PCI_CAP_CPCI_HOTSWAP 0x06 452#define PCI_CAP_PCIX 0x07 453#define PCI_CAP_LDT 0x08 454#define PCI_CAP_VENDSPEC 0x09 455#define PCI_CAP_DEBUGPORT 0x0a 456#define PCI_CAP_CPCI_RSRCCTL 0x0b 457#define PCI_CAP_HOTPLUG 0x0c 458#define PCI_CAP_AGP8 0x0e 459#define PCI_CAP_SECURE 0x0f 460#define PCI_CAP_PCIEXPRESS 0x10 461#define PCI_CAP_MSIX 0x11 462 463/* 464 * Power Management Control Status Register; access via capability pointer. 465 */ 466#define PCI_PMCSR 0x04 467#define PCI_PMCSR_STATE_MASK 0x03 468#define PCI_PMCSR_STATE_D0 0x00 469#define PCI_PMCSR_STATE_D1 0x01 470#define PCI_PMCSR_STATE_D2 0x02 471#define PCI_PMCSR_STATE_D3 0x03 472 473/* 474 * Interrupt Configuration Register; contains interrupt pin and line. 475 */ 476#define PCI_INTERRUPT_REG 0x3c 477 478typedef u_int8_t pci_intr_pin_t; 479typedef u_int8_t pci_intr_line_t; 480 481#define PCI_INTERRUPT_PIN_SHIFT 8 482#define PCI_INTERRUPT_PIN_MASK 0xff 483#define PCI_INTERRUPT_PIN(icr) \ 484 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 485 486#define PCI_INTERRUPT_LINE_SHIFT 0 487#define PCI_INTERRUPT_LINE_MASK 0xff 488#define PCI_INTERRUPT_LINE(icr) \ 489 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 490 491#define PCI_MIN_GNT_SHIFT 16 492#define PCI_MIN_GNT_MASK 0xff 493#define PCI_MIN_GNT(icr) \ 494 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 495 496#define PCI_MAX_LAT_SHIFT 24 497#define PCI_MAX_LAT_MASK 0xff 498#define PCI_MAX_LAT(icr) \ 499 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 500 501#define PCI_INTERRUPT_PIN_NONE 0x00 502#define PCI_INTERRUPT_PIN_A 0x01 503#define PCI_INTERRUPT_PIN_B 0x02 504#define PCI_INTERRUPT_PIN_C 0x03 505#define PCI_INTERRUPT_PIN_D 0x04 506#define PCI_INTERRUPT_PIN_MAX 0x04 507 508/* 509 * Vital Product Data resource tags. 510 */ 511struct pci_vpd_smallres { 512 uint8_t vpdres_byte0; /* length of data + tag */ 513 /* Actual data. */ 514} __attribute__((__packed__)); 515 516struct pci_vpd_largeres { 517 uint8_t vpdres_byte0; 518 uint8_t vpdres_len_lsb; /* length of data only */ 519 uint8_t vpdres_len_msb; 520 /* Actual data. */ 521} __attribute__((__packed__)); 522 523#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 524 525#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 526#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 527 528#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 529 530#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 531#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 532#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 533 534#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 535#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 536 537struct pci_vpd { 538 uint8_t vpd_key0; 539 uint8_t vpd_key1; 540 uint8_t vpd_len; /* length of data only */ 541 /* Actual data. */ 542} __attribute__((__packed__)); 543 544/* 545 * Recommended VPD fields: 546 * 547 * PN Part number of assembly 548 * FN FRU part number 549 * EC EC level of assembly 550 * MN Manufacture ID 551 * SN Serial Number 552 * 553 * Conditionally recommended VPD fields: 554 * 555 * LI Load ID 556 * RL ROM Level 557 * RM Alterable ROM Level 558 * NA Network Address 559 * DD Device Driver Level 560 * DG Diagnostic Level 561 * LL Loadable Microcode Level 562 * VI Vendor ID/Device ID 563 * FU Function Number 564 * SI Subsystem Vendor ID/Subsystem ID 565 * 566 * Additional VPD fields: 567 * 568 * Z0-ZZ User/Product Specific 569 */ 570 571#endif /* _DEV_PCI_PCIREG_H_ */ 572