pcireg.h revision 1.17
1/* $OpenBSD: pcireg.h,v 1.17 2001/05/08 19:47:43 mickey Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61/* 62 * Command and status register. 63 */ 64#define PCI_COMMAND_STATUS_REG 0x04 65 66#define PCI_COMMAND_IO_ENABLE 0x00000001 67#define PCI_COMMAND_MEM_ENABLE 0x00000002 68#define PCI_COMMAND_MASTER_ENABLE 0x00000004 69#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 70#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 71#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 72#define PCI_COMMAND_PARITY_ENABLE 0x00000040 73#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 74#define PCI_COMMAND_SERR_ENABLE 0x00000100 75#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 76 77#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 78#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 79#define PCI_STATUS_UDF_SUPPORT 0x00400000 80#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 81#define PCI_STATUS_PARITY_ERROR 0x01000000 82#define PCI_STATUS_DEVSEL_FAST 0x00000000 83#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 84#define PCI_STATUS_DEVSEL_SLOW 0x04000000 85#define PCI_STATUS_DEVSEL_MASK 0x06000000 86#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 87#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 88#define PCI_STATUS_MASTER_ABORT 0x20000000 89#define PCI_STATUS_SPECIAL_ERROR 0x40000000 90#define PCI_STATUS_PARITY_DETECT 0x80000000 91 92/* 93 * PCI Class and Revision Register; defines type and revision of device. 94 */ 95#define PCI_CLASS_REG 0x08 96 97typedef u_int8_t pci_class_t; 98typedef u_int8_t pci_subclass_t; 99typedef u_int8_t pci_interface_t; 100typedef u_int8_t pci_revision_t; 101 102#define PCI_CLASS_SHIFT 24 103#define PCI_CLASS_MASK 0xff 104#define PCI_CLASS(cr) \ 105 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 106 107#define PCI_SUBCLASS_SHIFT 16 108#define PCI_SUBCLASS_MASK 0xff 109#define PCI_SUBCLASS(cr) \ 110 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 111 112#define PCI_INTERFACE_SHIFT 8 113#define PCI_INTERFACE_MASK 0xff 114#define PCI_INTERFACE(cr) \ 115 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 116 117#define PCI_REVISION_SHIFT 0 118#define PCI_REVISION_MASK 0xff 119#define PCI_REVISION(cr) \ 120 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 121 122/* base classes */ 123#define PCI_CLASS_PREHISTORIC 0x00 124#define PCI_CLASS_MASS_STORAGE 0x01 125#define PCI_CLASS_NETWORK 0x02 126#define PCI_CLASS_DISPLAY 0x03 127#define PCI_CLASS_MULTIMEDIA 0x04 128#define PCI_CLASS_MEMORY 0x05 129#define PCI_CLASS_BRIDGE 0x06 130#define PCI_CLASS_COMMUNICATIONS 0x07 131#define PCI_CLASS_SYSTEM 0x08 132#define PCI_CLASS_INPUT 0x09 133#define PCI_CLASS_DOCK 0x0a 134#define PCI_CLASS_PROCESSOR 0x0b 135#define PCI_CLASS_SERIALBUS 0x0c 136#define PCI_CLASS_WIRELESS 0x0d 137#define PCI_CLASS_I2O 0x0e 138#define PCI_CLASS_SATCOM 0x0f 139#define PCI_CLASS_CRYPTO 0x10 140#define PCI_CLASS_DASP 0x11 141#define PCI_CLASS_UNDEFINED 0xff 142 143/* 0x00 prehistoric subclasses */ 144#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 145#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 146 147/* 0x01 mass storage subclasses */ 148#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 149#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 150#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 151#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 152#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 153#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 154#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 155 156/* 0x02 network subclasses */ 157#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 158#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 159#define PCI_SUBCLASS_NETWORK_FDDI 0x02 160#define PCI_SUBCLASS_NETWORK_ATM 0x03 161#define PCI_SUBCLASS_NETWORK_ISDN 0x04 162#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 163#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 164#define PCI_SUBCLASS_NETWORK_MISC 0x80 165 166/* 0x03 display subclasses */ 167#define PCI_SUBCLASS_DISPLAY_VGA 0x00 168#define PCI_SUBCLASS_DISPLAY_XGA 0x01 169#define PCI_SUBCLASS_DISPLAY_3D 0x02 170#define PCI_SUBCLASS_DISPLAY_MISC 0x80 171 172/* 0x04 multimedia subclasses */ 173#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 174#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 175#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 176#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 177 178/* 0x05 memory subclasses */ 179#define PCI_SUBCLASS_MEMORY_RAM 0x00 180#define PCI_SUBCLASS_MEMORY_FLASH 0x01 181#define PCI_SUBCLASS_MEMORY_MISC 0x80 182 183/* 0x06 bridge subclasses */ 184#define PCI_SUBCLASS_BRIDGE_HOST 0x00 185#define PCI_SUBCLASS_BRIDGE_ISA 0x01 186#define PCI_SUBCLASS_BRIDGE_EISA 0x02 187#define PCI_SUBCLASS_BRIDGE_MC 0x03 188#define PCI_SUBCLASS_BRIDGE_PCI 0x04 189#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 190#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 191#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 192#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 193#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 194#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 195#define PCI_SUBCLASS_BRIDGE_MISC 0x80 196 197/* 0x07 communications subclasses */ 198#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 199#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 200#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 201#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 202#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 203 204/* 0x08 system subclasses */ 205#define PCI_SUBCLASS_SYSTEM_PIC 0x00 206#define PCI_SUBCLASS_SYSTEM_DMA 0x01 207#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 208#define PCI_SUBCLASS_SYSTEM_RTC 0x03 209#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 210#define PCI_SUBCLASS_SYSTEM_MISC 0x80 211 212/* 0x09 input subclasses */ 213#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 214#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 215#define PCI_SUBCLASS_INPUT_MOUSE 0x02 216#define PCI_SUBCLASS_INPUT_SCANNER 0x03 217#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 218#define PCI_SUBCLASS_INPUT_MISC 0x80 219 220/* 0x0a dock subclasses */ 221#define PCI_SUBCLASS_DOCK_GENERIC 0x00 222#define PCI_SUBCLASS_DOCK_MISC 0x80 223 224/* 0x0b processor subclasses */ 225#define PCI_SUBCLASS_PROCESSOR_386 0x00 226#define PCI_SUBCLASS_PROCESSOR_486 0x01 227#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 228#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 229#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 230#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 231#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 232 233/* 0x0c serial bus subclasses */ 234#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 235#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 236#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 237#define PCI_SUBCLASS_SERIALBUS_USB 0x03 238#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 239#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 240#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 241#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 242#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 243#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 244 245/* 0x0d wireless subclasses */ 246#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 247#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 248#define PCI_SUBCLASS_WIRELESS_RF 0x10 249#define PCI_SUBCLASS_WIRELESS_MISC 0x80 250 251/* 0x0e I2O (Intelligent I/O) subclasses */ 252#define PCI_SUBCLASS_I2O_STANDARD 0x00 253 254/* 0x0f satellite communication subclasses */ 255/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 256#define PCI_SUBCLASS_SATCOM_TV 0x01 257#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 258#define PCI_SUBCLASS_SATCOM_VOICE 0x03 259#define PCI_SUBCLASS_SATCOM_DATA 0x04 260 261/* 0x10 encryption/decryption subclasses */ 262#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 263#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 264#define PCI_SUBCLASS_CRYPTO_MISC 0x80 265 266/* 0x11 data acquisition and signal processing subclasses */ 267#define PCI_SUBCLASS_DASP_DPIO 0x00 268#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 269#define PCI_SUBCLASS_DASP_MISC 0x80 270 271/* 272 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 273 */ 274#define PCI_BHLC_REG 0x0c 275 276#define PCI_BIST_SHIFT 24 277#define PCI_BIST_MASK 0xff 278#define PCI_BIST(bhlcr) \ 279 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 280 281#define PCI_HDRTYPE_SHIFT 16 282#define PCI_HDRTYPE_MASK 0xff 283#define PCI_HDRTYPE(bhlcr) \ 284 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 285 286#define PCI_HDRTYPE_TYPE(bhlcr) \ 287 (PCI_HDRTYPE(bhlcr) & 0x7f) 288#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 289 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 290 291#define PCI_LATTIMER_SHIFT 8 292#define PCI_LATTIMER_MASK 0xff 293#define PCI_LATTIMER(bhlcr) \ 294 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 295 296#define PCI_CACHELINE_SHIFT 0 297#define PCI_CACHELINE_MASK 0xff 298#define PCI_CACHELINE(bhlcr) \ 299 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 300 301/* config registers for header type 0 devices */ 302 303#define PCI_MAPS 0x10 304#define PCI_CARDBUSCIS 0x28 305#define PCI_SUBVEND_0 0x2c 306#define PCI_SUBDEV_0 0x2e 307#define PCI_INTLINE 0x3c 308#define PCI_INTPIN 0x3d 309#define PCI_MINGNT 0x3e 310#define PCI_MAXLAT 0x3f 311 312/* config registers for header type 1 devices */ 313 314#define PCI_SECSTAT_1 0 /**/ 315 316#define PCI_PRIBUS_1 0x18 317#define PCI_SECBUS_1 0x19 318#define PCI_SUBBUS_1 0x1a 319#define PCI_SECLAT_1 0x1b 320 321#define PCI_IOBASEL_1 0x1c 322#define PCI_IOLIMITL_1 0x1d 323#define PCI_IOBASEH_1 0 /**/ 324#define PCI_IOLIMITH_1 0 /**/ 325 326#define PCI_MEMBASE_1 0x20 327#define PCI_MEMLIMIT_1 0x22 328 329#define PCI_PMBASEL_1 0x24 330#define PCI_PMLIMITL_1 0x26 331#define PCI_PMBASEH_1 0 /**/ 332#define PCI_PMLIMITH_1 0 /**/ 333 334#define PCI_BRIDGECTL_1 0 /**/ 335 336#define PCI_SUBVEND_1 0x34 337#define PCI_SUBDEV_1 0x36 338 339/* config registers for header type 2 devices */ 340 341#define PCI_SECSTAT_2 0x16 342 343#define PCI_PRIBUS_2 0x18 344#define PCI_SECBUS_2 0x19 345#define PCI_SUBBUS_2 0x1a 346#define PCI_SECLAT_2 0x1b 347 348#define PCI_MEMBASE0_2 0x1c 349#define PCI_MEMLIMIT0_2 0x20 350#define PCI_MEMBASE1_2 0x24 351#define PCI_MEMLIMIT1_2 0x28 352#define PCI_IOBASE0_2 0x2c 353#define PCI_IOLIMIT0_2 0x30 354#define PCI_IOBASE1_2 0x34 355#define PCI_IOLIMIT1_2 0x38 356 357#define PCI_BRIDGECTL_2 0x3e 358 359#define PCI_SUBVEND_2 0x40 360#define PCI_SUBDEV_2 0x42 361 362#define PCI_PCCARDIF_2 0x44 363 364/* 365 * Mapping registers 366 */ 367#define PCI_MAPREG_START 0x10 368#define PCI_MAPREG_END 0x28 369#define PCI_MAPREG_PPB_END 0x18 370#define PCI_MAPREG_PCB_END 0x14 371 372#define PCI_MAPREG_TYPE(mr) \ 373 ((mr) & PCI_MAPREG_TYPE_MASK) 374#define PCI_MAPREG_TYPE_MASK 0x00000001 375 376#define PCI_MAPREG_TYPE_MEM 0x00000000 377#define PCI_MAPREG_TYPE_IO 0x00000001 378 379#define PCI_MAPREG_MEM_TYPE(mr) \ 380 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 381#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 382 383#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 384#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 385#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 386 387#define PCI_MAPREG_MEM_CACHEABLE(mr) \ 388 (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0) 389#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008 390 391#define PCI_MAPREG_MEM_ADDR(mr) \ 392 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 393#define PCI_MAPREG_MEM_SIZE(mr) \ 394 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 395#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 396 397#define PCI_MAPREG_MEM64_ADDR(mr) \ 398 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 399#define PCI_MAPREG_MEM64_SIZE(mr) \ 400 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 401#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0 402 403#define PCI_MAPREG_IO_ADDR(mr) \ 404 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 405#define PCI_MAPREG_IO_SIZE(mr) \ 406 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 407#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 408 409/* 410 * Cardbus CIS pointer (PCI rev. 2.1) 411 */ 412#define PCI_CARDBUS_CIS_REG 0x28 413 414/* 415 * Subsystem identification register; contains a vendor ID and a device ID. 416 * Types/macros for PCI_ID_REG apply. 417 * (PCI rev. 2.1) 418 */ 419#define PCI_SUBSYS_ID_REG 0x2c 420 421/* 422 * capabilities link list (PCI rev. 2.2) 423 */ 424#define PCI_CAPLISTPTR_REG 0x34 425#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 426#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 427#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 428 429#define PCI_CAP_REESSERVED 0x00 430#define PCI_CAP_PWRMGMT 0x01 431#define PCI_CAP_AGP 0x02 432#define PCI_CAP_VPD 0x03 433#define PCI_CAP_SLOTID 0x04 434#define PCI_CAP_MBI 0x05 435#define PCI_CAP_CPCI_HOTSWAP 0x06 436#define PCI_CAP_PCIX 0x07 437#define PCI_CAP_LDT 0x08 438#define PCI_CAP_VENDSPEC 0x09 439#define PCI_CAP_DEBUGPORT 0x0a 440#define PCI_CAP_CPCI_RSRCCTL 0x0b 441#define PCI_CAP_HOTPLUG 0x0c 442 443/* 444 * Power Management Control Status Register; access via capability pointer. 445 */ 446#define PCI_PMCSR_STATE_MASK 0x03 447#define PCI_PMCSR_STATE_D0 0x00 448#define PCI_PMCSR_STATE_D1 0x01 449#define PCI_PMCSR_STATE_D2 0x02 450#define PCI_PMCSR_STATE_D3 0x03 451 452/* 453 * Interrupt Configuration Register; contains interrupt pin and line. 454 */ 455#define PCI_INTERRUPT_REG 0x3c 456 457typedef u_int8_t pci_intr_pin_t; 458typedef u_int8_t pci_intr_line_t; 459 460#define PCI_INTERRUPT_PIN_SHIFT 8 461#define PCI_INTERRUPT_PIN_MASK 0xff 462#define PCI_INTERRUPT_PIN(icr) \ 463 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 464 465#define PCI_INTERRUPT_LINE_SHIFT 0 466#define PCI_INTERRUPT_LINE_MASK 0xff 467#define PCI_INTERRUPT_LINE(icr) \ 468 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 469 470#define PCI_MIN_GNT_SHIFT 16 471#define PCI_MIN_GNT_MASK 0xff 472#define PCI_MIN_GNT(icr) \ 473 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 474 475#define PCI_MAX_LAT_SHIFT 24 476#define PCI_MAX_LAT_MASK 0xff 477#define PCI_MAX_LAT(icr) \ 478 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 479 480#define PCI_INTERRUPT_PIN_NONE 0x00 481#define PCI_INTERRUPT_PIN_A 0x01 482#define PCI_INTERRUPT_PIN_B 0x02 483#define PCI_INTERRUPT_PIN_C 0x03 484#define PCI_INTERRUPT_PIN_D 0x04 485#define PCI_INTERRUPT_PIN_MAX 0x04 486 487#endif /* _DEV_PCI_PCIREG_H_ */ 488