pcireg.h revision 1.4
1/* $OpenBSD: pcireg.h,v 1.4 1996/10/31 03:29:11 millert Exp $ */ 2/* $NetBSD: pcireg.h,v 1.7 1996/03/27 04:08:27 cgd Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61/* 62 * Command and status register. 63 */ 64#define PCI_COMMAND_STATUS_REG 0x04 65 66#define PCI_COMMAND_IO_ENABLE 0x00000001 67#define PCI_COMMAND_MEM_ENABLE 0x00000002 68#define PCI_COMMAND_MASTER_ENABLE 0x00000004 69#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 70#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 71#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 72#define PCI_COMMAND_PARITY_ENABLE 0x00000040 73#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 74#define PCI_COMMAND_SERR_ENABLE 0x00000100 75#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 76 77#define PCI_STATUS_BACKTOBACK_OKAY 0x00800000 78#define PCI_STATUS_PARITY_ERROR 0x01000000 79#define PCI_STATUS_DEVSEL_FAST 0x00000000 80#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 81#define PCI_STATUS_DEVSEL_SLOW 0x04000000 82#define PCI_STATUS_DEVSEL_MASK 0x06000000 83#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 84#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 85#define PCI_STATUS_MASTER_ABORT 0x20000000 86#define PCI_STATUS_SPECIAL_ERROR 0x40000000 87#define PCI_STATUS_PARITY_DETECT 0x80000000 88 89/* 90 * PCI Class and Revision Register; defines type and revision of device. 91 */ 92#define PCI_CLASS_REG 0x08 93 94typedef u_int8_t pci_class_t; 95typedef u_int8_t pci_subclass_t; 96typedef u_int8_t pci_interface_t; 97typedef u_int8_t pci_revision_t; 98 99#define PCI_CLASS_SHIFT 24 100#define PCI_CLASS_MASK 0xff 101#define PCI_CLASS(cr) \ 102 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 103 104#define PCI_SUBCLASS_SHIFT 16 105#define PCI_SUBCLASS_MASK 0xff 106#define PCI_SUBCLASS(cr) \ 107 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 108 109#define PCI_INTERFACE_SHIFT 8 110#define PCI_INTERFACE_MASK 0xff 111#define PCI_INTERFACE(cr) \ 112 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 113 114#define PCI_REVISION_SHIFT 0 115#define PCI_REVISION_MASK 0xff 116#define PCI_REVISION(cr) \ 117 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 118 119/* base classes */ 120#define PCI_CLASS_PREHISTORIC 0x00 121#define PCI_CLASS_MASS_STORAGE 0x01 122#define PCI_CLASS_NETWORK 0x02 123#define PCI_CLASS_DISPLAY 0x03 124#define PCI_CLASS_MULTIMEDIA 0x04 125#define PCI_CLASS_MEMORY 0x05 126#define PCI_CLASS_BRIDGE 0x06 127#define PCI_CLASS_UNDEFINED 0xff 128 129/* 0x00 prehistoric subclasses */ 130#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 131#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 132 133/* 0x01 mass storage subclasses */ 134#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 135#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 136#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 137#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 138#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 139 140/* 0x02 network subclasses */ 141#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 142#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 143#define PCI_SUBCLASS_NETWORK_FDDI 0x02 144#define PCI_SUBCLASS_NETWORK_ATM 0x03 145#define PCI_SUBCLASS_NETWORK_MISC 0x80 146 147/* 0x03 display subclasses */ 148#define PCI_SUBCLASS_DISPLAY_VGA 0x00 149#define PCI_SUBCLASS_DISPLAY_XGA 0x01 150#define PCI_SUBCLASS_DISPLAY_MISC 0x80 151 152/* 0x04 multimedia subclasses */ 153#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 154#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 155#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 156 157/* 0x05 memory subclasses */ 158#define PCI_SUBCLASS_MEMORY_RAM 0x00 159#define PCI_SUBCLASS_MEMORY_FLASH 0x01 160#define PCI_SUBCLASS_MEMORY_MISC 0x80 161 162/* 0x06 bridge subclasses */ 163#define PCI_SUBCLASS_BRIDGE_HOST 0x00 164#define PCI_SUBCLASS_BRIDGE_ISA 0x01 165#define PCI_SUBCLASS_BRIDGE_EISA 0x02 166#define PCI_SUBCLASS_BRIDGE_MC 0x03 167#define PCI_SUBCLASS_BRIDGE_PCI 0x04 168#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 169#define PCI_SUBCLASS_BRIDGE_MISC 0x80 170 171/* 172 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 173 */ 174#define PCI_BHLC_REG 0x0c 175 176#define PCI_BIST_SHIFT 24 177#define PCI_BIST_MASK 0xff 178#define PCI_BIST(bhlcr) \ 179 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 180 181#define PCI_HDRTYPE_SHIFT 24 182#define PCI_HDRTYPE_MASK 0xff 183#define PCI_HDRTYPE(bhlcr) \ 184 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 185 186#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 187 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 188 189#define PCI_LATTIMER_SHIFT 24 190#define PCI_LATTIMER_MASK 0xff 191#define PCI_LATTIMER(bhlcr) \ 192 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 193 194#define PCI_CACHELINE_SHIFT 24 195#define PCI_CACHELINE_MASK 0xff 196#define PCI_CACHELINE(bhlcr) \ 197 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 198 199/* 200 * Mapping registers 201 */ 202#define PCI_MAPREG_START 0x10 203#define PCI_MAPREG_END 0x28 204 205#define PCI_MAPREG_TYPE(mr) \ 206 ((mr) & PCI_MAPREG_TYPE_MASK) 207#define PCI_MAPREG_TYPE_MASK 0x00000001 208 209#define PCI_MAPREG_TYPE_MEM 0x00000000 210#define PCI_MAPREG_TYPE_IO 0x00000001 211 212#define PCI_MAPREG_MEM_TYPE(mr) \ 213 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 214#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 215 216#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 217#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 218#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 219 220#define PCI_MAPREG_MEM_CACHEABLE(mr) \ 221 (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0) 222#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008 223 224#define PCI_MAPREG_MEM_ADDR(mr) \ 225 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 226#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 227 228#define PCI_MAPREG_IO_ADDR(mr) \ 229 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 230#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 231 232/* 233 * Interrupt Configuration Register; contains interrupt pin and line. 234 */ 235#define PCI_INTERRUPT_REG 0x3c 236 237typedef u_int8_t pci_intr_pin_t; 238typedef u_int8_t pci_intr_line_t; 239 240#define PCI_INTERRUPT_PIN_SHIFT 8 241#define PCI_INTERRUPT_PIN_MASK 0xff 242#define PCI_INTERRUPT_PIN(icr) \ 243 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 244 245#define PCI_INTERRUPT_LINE_SHIFT 0 246#define PCI_INTERRUPT_LINE_MASK 0xff 247#define PCI_INTERRUPT_LINE(icr) \ 248 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 249 250#define PCI_INTERRUPT_PIN_NONE 0x00 251#define PCI_INTERRUPT_PIN_A 0x01 252#define PCI_INTERRUPT_PIN_B 0x02 253#define PCI_INTERRUPT_PIN_C 0x03 254#define PCI_INTERRUPT_PIN_D 0x04 255 256#endif /* _DEV_PCI_PCIREG_H_ */ 257