pcireg.h revision 1.52
1/* $OpenBSD: pcireg.h,v 1.52 2017/03/22 07:21:39 jsg Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43#define PCI_CONFIG_SPACE_SIZE 0x100 44#define PCIE_CONFIG_SPACE_SIZE 0x1000 45 46/* 47 * Device identification register; contains a vendor ID and a device ID. 48 */ 49#define PCI_ID_REG 0x00 50 51typedef u_int16_t pci_vendor_id_t; 52typedef u_int16_t pci_product_id_t; 53 54#define PCI_VENDOR_SHIFT 0 55#define PCI_VENDOR_MASK 0xffff 56#define PCI_VENDOR(id) \ 57 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 58 59#define PCI_PRODUCT_SHIFT 16 60#define PCI_PRODUCT_MASK 0xffff 61#define PCI_PRODUCT(id) \ 62 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 63 64#define PCI_ID_CODE(vid,pid) \ 65 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 66 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 67 68/* 69 * Command and status register. 70 */ 71#define PCI_COMMAND_STATUS_REG 0x04 72 73#define PCI_COMMAND_IO_ENABLE 0x00000001 74#define PCI_COMMAND_MEM_ENABLE 0x00000002 75#define PCI_COMMAND_MASTER_ENABLE 0x00000004 76#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 77#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 78#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 79#define PCI_COMMAND_PARITY_ENABLE 0x00000040 80#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 81#define PCI_COMMAND_SERR_ENABLE 0x00000100 82#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 83#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 84 85#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 86#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 87#define PCI_STATUS_UDF_SUPPORT 0x00400000 88#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 89#define PCI_STATUS_PARITY_ERROR 0x01000000 90#define PCI_STATUS_DEVSEL_FAST 0x00000000 91#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 92#define PCI_STATUS_DEVSEL_SLOW 0x04000000 93#define PCI_STATUS_DEVSEL_MASK 0x06000000 94#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 95#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 96#define PCI_STATUS_MASTER_ABORT 0x20000000 97#define PCI_STATUS_SPECIAL_ERROR 0x40000000 98#define PCI_STATUS_PARITY_DETECT 0x80000000 99 100#define PCI_COMMAND_STATUS_BITS \ 101 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 102 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 103 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 104 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 105 "\037SPECIAL_ERROR\040PARITY_DETECT") 106/* 107 * PCI Class and Revision Register; defines type and revision of device. 108 */ 109#define PCI_CLASS_REG 0x08 110 111typedef u_int8_t pci_class_t; 112typedef u_int8_t pci_subclass_t; 113typedef u_int8_t pci_interface_t; 114typedef u_int8_t pci_revision_t; 115 116#define PCI_CLASS_SHIFT 24 117#define PCI_CLASS_MASK 0xff 118#define PCI_CLASS(cr) \ 119 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 120 121#define PCI_SUBCLASS_SHIFT 16 122#define PCI_SUBCLASS_MASK 0xff 123#define PCI_SUBCLASS(cr) \ 124 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 125 126#define PCI_INTERFACE_SHIFT 8 127#define PCI_INTERFACE_MASK 0xff 128#define PCI_INTERFACE(cr) \ 129 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 130 131#define PCI_REVISION_SHIFT 0 132#define PCI_REVISION_MASK 0xff 133#define PCI_REVISION(cr) \ 134 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 135 136/* base classes */ 137#define PCI_CLASS_PREHISTORIC 0x00 138#define PCI_CLASS_MASS_STORAGE 0x01 139#define PCI_CLASS_NETWORK 0x02 140#define PCI_CLASS_DISPLAY 0x03 141#define PCI_CLASS_MULTIMEDIA 0x04 142#define PCI_CLASS_MEMORY 0x05 143#define PCI_CLASS_BRIDGE 0x06 144#define PCI_CLASS_COMMUNICATIONS 0x07 145#define PCI_CLASS_SYSTEM 0x08 146#define PCI_CLASS_INPUT 0x09 147#define PCI_CLASS_DOCK 0x0a 148#define PCI_CLASS_PROCESSOR 0x0b 149#define PCI_CLASS_SERIALBUS 0x0c 150#define PCI_CLASS_WIRELESS 0x0d 151#define PCI_CLASS_I2O 0x0e 152#define PCI_CLASS_SATCOM 0x0f 153#define PCI_CLASS_CRYPTO 0x10 154#define PCI_CLASS_DASP 0x11 155#define PCI_CLASS_ACCELERATOR 0x12 156#define PCI_CLASS_INSTRUMENTATION 0x13 157#define PCI_CLASS_UNDEFINED 0xff 158 159/* 0x00 prehistoric subclasses */ 160#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 161#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 162 163/* 0x01 mass storage subclasses */ 164#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 165#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 166#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 167#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 168#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 169#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 170#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 171#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 172#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08 173#define PCI_SUBCLASS_MASS_STORAGE_UFS 0x09 174#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 175 176/* 0x02 network subclasses */ 177#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 178#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 179#define PCI_SUBCLASS_NETWORK_FDDI 0x02 180#define PCI_SUBCLASS_NETWORK_ATM 0x03 181#define PCI_SUBCLASS_NETWORK_ISDN 0x04 182#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 183#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 184#define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07 185#define PCI_SUBCLASS_NETWORK_MISC 0x80 186 187/* 0x03 display subclasses */ 188#define PCI_SUBCLASS_DISPLAY_VGA 0x00 189#define PCI_SUBCLASS_DISPLAY_XGA 0x01 190#define PCI_SUBCLASS_DISPLAY_3D 0x02 191#define PCI_SUBCLASS_DISPLAY_MISC 0x80 192 193/* 0x04 multimedia subclasses */ 194#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 195#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 196#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 197#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 198#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 199 200/* 0x05 memory subclasses */ 201#define PCI_SUBCLASS_MEMORY_RAM 0x00 202#define PCI_SUBCLASS_MEMORY_FLASH 0x01 203#define PCI_SUBCLASS_MEMORY_MISC 0x80 204 205/* 0x06 bridge subclasses */ 206#define PCI_SUBCLASS_BRIDGE_HOST 0x00 207#define PCI_SUBCLASS_BRIDGE_ISA 0x01 208#define PCI_SUBCLASS_BRIDGE_EISA 0x02 209#define PCI_SUBCLASS_BRIDGE_MC 0x03 210#define PCI_SUBCLASS_BRIDGE_PCI 0x04 211#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 212#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 213#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 214#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 215#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 216#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 217#define PCI_SUBCLASS_BRIDGE_AS 0x0b 218#define PCI_SUBCLASS_BRIDGE_MISC 0x80 219 220/* 0x07 communications subclasses */ 221#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 222#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 223#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 224#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 225#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 226#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 227#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 228 229/* 0x08 system subclasses */ 230#define PCI_SUBCLASS_SYSTEM_PIC 0x00 231#define PCI_SUBCLASS_SYSTEM_DMA 0x01 232#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 233#define PCI_SUBCLASS_SYSTEM_RTC 0x03 234#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 235#define PCI_SUBCLASS_SYSTEM_SDHC 0x05 236#define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 237#define PCI_SUBCLASS_SYSTEM_ROOTCOMPEVENT 0x07 238#define PCI_SUBCLASS_SYSTEM_MISC 0x80 239 240/* 0x09 input subclasses */ 241#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 242#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 243#define PCI_SUBCLASS_INPUT_MOUSE 0x02 244#define PCI_SUBCLASS_INPUT_SCANNER 0x03 245#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 246#define PCI_SUBCLASS_INPUT_MISC 0x80 247 248/* 0x0a dock subclasses */ 249#define PCI_SUBCLASS_DOCK_GENERIC 0x00 250#define PCI_SUBCLASS_DOCK_MISC 0x80 251 252/* 0x0b processor subclasses */ 253#define PCI_SUBCLASS_PROCESSOR_386 0x00 254#define PCI_SUBCLASS_PROCESSOR_486 0x01 255#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 256#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 257#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 258#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 259#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 260 261/* 0x0c serial bus subclasses */ 262#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 263#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 264#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 265#define PCI_SUBCLASS_SERIALBUS_USB 0x03 266#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 267#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 268#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 269#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 270#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 271#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 272 273/* 0x0d wireless subclasses */ 274#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 275#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 276#define PCI_SUBCLASS_WIRELESS_RF 0x10 277#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 278#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 279#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 280#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 281#define PCI_SUBCLASS_WIRELESS_MISC 0x80 282 283/* 0x0e I2O (Intelligent I/O) subclasses */ 284#define PCI_SUBCLASS_I2O_STANDARD 0x00 285 286/* 0x0f satellite communication subclasses */ 287/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 288#define PCI_SUBCLASS_SATCOM_TV 0x01 289#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 290#define PCI_SUBCLASS_SATCOM_VOICE 0x03 291#define PCI_SUBCLASS_SATCOM_DATA 0x04 292 293/* 0x10 encryption/decryption subclasses */ 294#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 295#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 296#define PCI_SUBCLASS_CRYPTO_MISC 0x80 297 298/* 0x11 data acquisition and signal processing subclasses */ 299#define PCI_SUBCLASS_DASP_DPIO 0x00 300#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 301#define PCI_SUBCLASS_DASP_SYNC 0x10 302#define PCI_SUBCLASS_DASP_MGMT 0x20 303#define PCI_SUBCLASS_DASP_MISC 0x80 304 305/* 306 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 307 */ 308#define PCI_BHLC_REG 0x0c 309 310#define PCI_BIST_SHIFT 24 311#define PCI_BIST_MASK 0xff 312#define PCI_BIST(bhlcr) \ 313 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 314 315#define PCI_HDRTYPE_SHIFT 16 316#define PCI_HDRTYPE_MASK 0xff 317#define PCI_HDRTYPE(bhlcr) \ 318 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 319 320#define PCI_HDRTYPE_TYPE(bhlcr) \ 321 (PCI_HDRTYPE(bhlcr) & 0x7f) 322#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 323 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 324 325#define PCI_LATTIMER_SHIFT 8 326#define PCI_LATTIMER_MASK 0xff 327#define PCI_LATTIMER(bhlcr) \ 328 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 329 330#define PCI_CACHELINE_SHIFT 0 331#define PCI_CACHELINE_MASK 0xff 332#define PCI_CACHELINE(bhlcr) \ 333 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 334 335/* config registers for header type 0 devices */ 336 337#define PCI_MAPS 0x10 338#define PCI_CARDBUSCIS 0x28 339#define PCI_SUBVEND_0 0x2c 340#define PCI_SUBDEV_0 0x2e 341#define PCI_INTLINE 0x3c 342#define PCI_INTPIN 0x3d 343#define PCI_MINGNT 0x3e 344#define PCI_MAXLAT 0x3f 345 346/* config registers for header type 1 devices */ 347 348#define PCI_SECSTAT_1 0 /**/ 349 350#define PCI_PRIBUS_1 0x18 351#define PCI_SECBUS_1 0x19 352#define PCI_SUBBUS_1 0x1a 353#define PCI_SECLAT_1 0x1b 354 355#define PCI_IOBASEL_1 0x1c 356#define PCI_IOLIMITL_1 0x1d 357#define PCI_IOBASEH_1 0 /**/ 358#define PCI_IOLIMITH_1 0 /**/ 359 360#define PCI_MEMBASE_1 0x20 361#define PCI_MEMLIMIT_1 0x22 362 363#define PCI_PMBASEL_1 0x24 364#define PCI_PMLIMITL_1 0x26 365#define PCI_PMBASEH_1 0 /**/ 366#define PCI_PMLIMITH_1 0 /**/ 367 368#define PCI_BRIDGECTL_1 0 /**/ 369 370#define PCI_SUBVEND_1 0x34 371#define PCI_SUBDEV_1 0x36 372 373/* config registers for header type 2 devices */ 374 375#define PCI_SECSTAT_2 0x16 376 377#define PCI_PRIBUS_2 0x18 378#define PCI_SECBUS_2 0x19 379#define PCI_SUBBUS_2 0x1a 380#define PCI_SECLAT_2 0x1b 381 382#define PCI_MEMBASE0_2 0x1c 383#define PCI_MEMLIMIT0_2 0x20 384#define PCI_MEMBASE1_2 0x24 385#define PCI_MEMLIMIT1_2 0x28 386#define PCI_IOBASE0_2 0x2c 387#define PCI_IOLIMIT0_2 0x30 388#define PCI_IOBASE1_2 0x34 389#define PCI_IOLIMIT1_2 0x38 390 391#define PCI_BRIDGECTL_2 0x3e 392 393#define PCI_SUBVEND_2 0x40 394#define PCI_SUBDEV_2 0x42 395 396#define PCI_PCCARDIF_2 0x44 397 398/* 399 * Mapping registers 400 */ 401#define PCI_MAPREG_START 0x10 402#define PCI_MAPREG_END 0x28 403#define PCI_MAPREG_PPB_END 0x18 404#define PCI_MAPREG_PCB_END 0x14 405 406#define PCI_MAPREG_TYPE(mr) \ 407 ((mr) & PCI_MAPREG_TYPE_MASK) 408#define PCI_MAPREG_TYPE_MASK 0x00000001 409 410#define PCI_MAPREG_TYPE_MEM 0x00000000 411#define PCI_MAPREG_TYPE_IO 0x00000001 412 413#define PCI_MAPREG_MEM_TYPE(mr) \ 414 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 415#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 416 417#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 418#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 419#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 420 421#define _PCI_MAPREG_TYPEBITS(reg) \ 422 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 423 reg & PCI_MAPREG_TYPE_MASK : \ 424 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 425 426#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 427 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 428#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 429 430#define PCI_MAPREG_MEM_ADDR(mr) \ 431 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 432#define PCI_MAPREG_MEM_SIZE(mr) \ 433 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 434#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 435 436#define PCI_MAPREG_MEM64_ADDR(mr) \ 437 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 438#define PCI_MAPREG_MEM64_SIZE(mr) \ 439 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 440#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 441 442#define PCI_MAPREG_IO_ADDR(mr) \ 443 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 444#define PCI_MAPREG_IO_SIZE(mr) \ 445 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 446#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 447 448/* 449 * Cardbus CIS pointer (PCI rev. 2.1) 450 */ 451#define PCI_CARDBUS_CIS_REG 0x28 452 453/* 454 * Subsystem identification register; contains a vendor ID and a device ID. 455 * Types/macros for PCI_ID_REG apply. 456 * (PCI rev. 2.1) 457 */ 458#define PCI_SUBSYS_ID_REG 0x2c 459 460/* 461 * Expansion ROM Base Address register 462 * (PCI rev. 2.0) 463 */ 464#define PCI_ROM_REG 0x30 465 466#define PCI_ROM_ENABLE 0x00000001 467#define PCI_ROM_ADDR_MASK 0xfffff800 468#define PCI_ROM_ADDR(mr) \ 469 ((mr) & PCI_ROM_ADDR_MASK) 470#define PCI_ROM_SIZE(mr) \ 471 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 472 473/* 474 * capabilities link list (PCI rev. 2.2) 475 */ 476#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 477#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 478#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 479#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 480#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 481 482#define PCI_CAP_RESERVED 0x00 483#define PCI_CAP_PWRMGMT 0x01 484#define PCI_CAP_AGP 0x02 485#define PCI_CAP_VPD 0x03 486#define PCI_CAP_SLOTID 0x04 487#define PCI_CAP_MSI 0x05 488#define PCI_CAP_CPCI_HOTSWAP 0x06 489#define PCI_CAP_PCIX 0x07 490#define PCI_CAP_HT 0x08 491#define PCI_CAP_VENDSPEC 0x09 492#define PCI_CAP_DEBUGPORT 0x0a 493#define PCI_CAP_CPCI_RSRCCTL 0x0b 494#define PCI_CAP_HOTPLUG 0x0c 495#define PCI_CAP_AGP8 0x0e 496#define PCI_CAP_SECURE 0x0f 497#define PCI_CAP_PCIEXPRESS 0x10 498#define PCI_CAP_MSIX 0x11 499#define PCI_CAP_SATA 0x12 500 501/* 502 * Vital Product Data; access via capability pointer (PCI rev 2.2). 503 */ 504#define PCI_VPD_ADDRESS_MASK 0x7fff 505#define PCI_VPD_ADDRESS_SHIFT 16 506#define PCI_VPD_ADDRESS(ofs) \ 507 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 508#define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 509#define PCI_VPD_OPFLAG 0x80000000 510 511/* 512 * Message Signaled Interrups; access via capability pointer. 513 */ 514#define PCI_MSI_MC 0x00 515#define PCI_MSI_MC_C64 0x00800000 516#define PCI_MSI_MC_MME 0x00700000 517#define PCI_MSI_MC_MMC 0x000e0000 518#define PCI_MSI_MC_MSIE 0x00010000 519#define PCI_MSI_MA 0x04 520#define PCI_MSI_MAU32 0x08 521#define PCI_MSI_MD32 0x08 522#define PCI_MSI_MD64 0x0c 523 524/* 525 * Power Management Control Status Register; access via capability pointer. 526 */ 527#define PCI_PMCSR 0x04 528#define PCI_PMCSR_STATE_MASK 0x0003 529#define PCI_PMCSR_STATE_D0 0x0000 530#define PCI_PMCSR_STATE_D1 0x0001 531#define PCI_PMCSR_STATE_D2 0x0002 532#define PCI_PMCSR_STATE_D3 0x0003 533#define PCI_PMCSR_PME_STATUS 0x8000 534#define PCI_PMCSR_PME_EN 0x0100 535 536/* 537 * HyperTransport; access via capability pointer. 538 */ 539#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 540 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 541 542#define PCI_HT_CAP_SLAVE 0x00 543#define PCI_HT_CAP_HOST 0x04 544#define PCI_HT_CAP_INTR 0x10 545#define PCI_HT_CAP_MSI 0x15 546 547#define PCI_HT_MSI_ENABLED 0x00010000 548#define PCI_HT_MSI_FIXED 0x00020000 549 550#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 551 552#define PCI_HT_MSI_ADDR 0x04 553#define PCI_HT_MSI_ADDR_HI32 0x08 554 555#define PCI_HT_INTR_DATA 0x04 556 557/* 558 * PCI Express; access via capability pointer. 559 */ 560#define PCI_PCIE_XCAP 0x00 561#define PCI_PCIE_XCAP_SI 0x01000000 562#define PCI_PCIE_XCAP_VER(x) (((x) >> 16) & 0x0f) 563#define PCI_PCIE_DCAP 0x04 564#define PCI_PCIE_DCSR 0x08 565#define PCI_PCIE_DCSR_ERO 0x00000010 566#define PCI_PCIE_DCSR_ENS 0x00000800 567#define PCI_PCIE_DCSR_MPS 0x00007000 568#define PCI_PCIE_DCSR_CEE 0x00010000 569#define PCI_PCIE_DCSR_NFE 0x00020000 570#define PCI_PCIE_DCSR_FEE 0x00040000 571#define PCI_PCIE_DCSR_URE 0x00080000 572#define PCI_PCIE_LCAP 0x0c 573#define PCI_PCIE_LCSR 0x10 574#define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 575#define PCI_PCIE_LCSR_ASPM_L1 0x00000002 576#define PCI_PCIE_LCSR_ES 0x00000080 577#define PCI_PCIE_SLCAP 0x14 578#define PCI_PCIE_SLCAP_ABP 0x00000001 579#define PCI_PCIE_SLCAP_PCP 0x00000002 580#define PCI_PCIE_SLCAP_MSP 0x00000004 581#define PCI_PCIE_SLCAP_AIP 0x00000008 582#define PCI_PCIE_SLCAP_PIP 0x00000010 583#define PCI_PCIE_SLCAP_HPS 0x00000020 584#define PCI_PCIE_SLCAP_HPC 0x00000040 585#define PCI_PCIE_SLCSR 0x18 586#define PCI_PCIE_SLCSR_ABE 0x00000001 587#define PCI_PCIE_SLCSR_PFE 0x00000002 588#define PCI_PCIE_SLCSR_MSE 0x00000004 589#define PCI_PCIE_SLCSR_PDE 0x00000008 590#define PCI_PCIE_SLCSR_CCE 0x00000010 591#define PCI_PCIE_SLCSR_HPE 0x00000020 592#define PCI_PCIE_SLCSR_ABP 0x00010000 593#define PCI_PCIE_SLCSR_PFD 0x00020000 594#define PCI_PCIE_SLCSR_MSC 0x00040000 595#define PCI_PCIE_SLCSR_PDC 0x00080000 596#define PCI_PCIE_SLCSR_CC 0x00100000 597#define PCI_PCIE_SLCSR_MS 0x00200000 598#define PCI_PCIE_SLCSR_PDS 0x00400000 599#define PCI_PCIE_SLCSR_LACS 0x01000000 600#define PCI_PCIE_RCSR 0x1c 601#define PCI_PCIE_LCAP2 0x2c 602 603/* 604 * PCI Express; enhanced capabilities 605 */ 606#define PCI_PCIE_ECAP 0x100 607#define PCI_PCIE_ECAP_ID(x) (((x) & 0x0000ffff)) 608#define PCI_PCIE_ECAP_VER(x) (((x) >> 16) & 0x0f) 609#define PCI_PCIE_ECAP_NEXT(x) ((x) >> 20) 610#define PCI_PCIE_ECAP_LAST 0x0 611 612/* 613 * Extended Message Signaled Interrups; access via capability pointer. 614 */ 615#define PCI_MSIX_MC_MSIXE 0x80000000 616#define PCI_MSIX_MC_TBLSZ_MASK 0x07ff0000 617#define PCI_MSIX_MC_TBLSZ_SHIFT 16 618#define PCI_MSIX_MC_TBLSZ(reg) \ 619 (((reg) & PCI_MSIX_MC_TBLSZ_MASK) >> PCI_MSIX_MC_TBLSZ_SHIFT) 620#define PCI_MSIX_TABLE 0x04 621#define PCI_MSIX_TABLE_BIR 0x00000007 622#define PCI_MSIX_TABLE_OFF ~(PCI_MSIX_TABLE_BIR) 623 624#define PCI_MSIX_MA(i) ((i) * 16 + 0) 625#define PCI_MSIX_MAU32(i) ((i) * 16 + 0) 626#define PCI_MSIX_MD(i) ((i) * 16 + 8) 627#define PCI_MSIX_VC(i) ((i) * 16 + 12) 628#define PCI_MSIX_VC_MASK 0x00000001 629 630/* 631 * Interrupt Configuration Register; contains interrupt pin and line. 632 */ 633#define PCI_INTERRUPT_REG 0x3c 634 635typedef u_int8_t pci_intr_pin_t; 636typedef u_int8_t pci_intr_line_t; 637 638#define PCI_INTERRUPT_PIN_SHIFT 8 639#define PCI_INTERRUPT_PIN_MASK 0xff 640#define PCI_INTERRUPT_PIN(icr) \ 641 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 642 643#define PCI_INTERRUPT_LINE_SHIFT 0 644#define PCI_INTERRUPT_LINE_MASK 0xff 645#define PCI_INTERRUPT_LINE(icr) \ 646 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 647 648#define PCI_MIN_GNT_SHIFT 16 649#define PCI_MIN_GNT_MASK 0xff 650#define PCI_MIN_GNT(icr) \ 651 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 652 653#define PCI_MAX_LAT_SHIFT 24 654#define PCI_MAX_LAT_MASK 0xff 655#define PCI_MAX_LAT(icr) \ 656 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 657 658#define PCI_INTERRUPT_PIN_NONE 0x00 659#define PCI_INTERRUPT_PIN_A 0x01 660#define PCI_INTERRUPT_PIN_B 0x02 661#define PCI_INTERRUPT_PIN_C 0x03 662#define PCI_INTERRUPT_PIN_D 0x04 663#define PCI_INTERRUPT_PIN_MAX 0x04 664 665/* 666 * Vital Product Data resource tags. 667 */ 668struct pci_vpd_smallres { 669 uint8_t vpdres_byte0; /* length of data + tag */ 670 /* Actual data. */ 671} __packed; 672 673struct pci_vpd_largeres { 674 uint8_t vpdres_byte0; 675 uint8_t vpdres_len_lsb; /* length of data only */ 676 uint8_t vpdres_len_msb; 677 /* Actual data. */ 678} __packed; 679 680#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 681 682#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 683#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 684 685#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 686 687#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 688#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 689#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 690 691#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 692#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 693 694struct pci_vpd { 695 uint8_t vpd_key0; 696 uint8_t vpd_key1; 697 uint8_t vpd_len; /* length of data only */ 698 /* Actual data. */ 699} __packed; 700 701/* 702 * Recommended VPD fields: 703 * 704 * PN Part number of assembly 705 * FN FRU part number 706 * EC EC level of assembly 707 * MN Manufacture ID 708 * SN Serial Number 709 * 710 * Conditionally recommended VPD fields: 711 * 712 * LI Load ID 713 * RL ROM Level 714 * RM Alterable ROM Level 715 * NA Network Address 716 * DD Device Driver Level 717 * DG Diagnostic Level 718 * LL Loadable Microcode Level 719 * VI Vendor ID/Device ID 720 * FU Function Number 721 * SI Subsystem Vendor ID/Subsystem ID 722 * 723 * Additional VPD fields: 724 * 725 * Z0-ZZ User/Product Specific 726 */ 727 728#endif /* _DEV_PCI_PCIREG_H_ */ 729