pcireg.h revision 1.43
1/* $OpenBSD: pcireg.h,v 1.43 2012/05/13 13:47:52 kettenis Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43#define PCI_CONFIG_SPACE_SIZE 0x100 44#define PCIE_CONFIG_SPACE_SIZE 0x1000 45 46/* 47 * Device identification register; contains a vendor ID and a device ID. 48 */ 49#define PCI_ID_REG 0x00 50 51typedef u_int16_t pci_vendor_id_t; 52typedef u_int16_t pci_product_id_t; 53 54#define PCI_VENDOR_SHIFT 0 55#define PCI_VENDOR_MASK 0xffff 56#define PCI_VENDOR(id) \ 57 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 58 59#define PCI_PRODUCT_SHIFT 16 60#define PCI_PRODUCT_MASK 0xffff 61#define PCI_PRODUCT(id) \ 62 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 63 64#define PCI_ID_CODE(vid,pid) \ 65 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 66 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 67 68/* 69 * Command and status register. 70 */ 71#define PCI_COMMAND_STATUS_REG 0x04 72 73#define PCI_COMMAND_IO_ENABLE 0x00000001 74#define PCI_COMMAND_MEM_ENABLE 0x00000002 75#define PCI_COMMAND_MASTER_ENABLE 0x00000004 76#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 77#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 78#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 79#define PCI_COMMAND_PARITY_ENABLE 0x00000040 80#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 81#define PCI_COMMAND_SERR_ENABLE 0x00000100 82#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 83#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400 84 85#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 86#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 87#define PCI_STATUS_UDF_SUPPORT 0x00400000 88#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 89#define PCI_STATUS_PARITY_ERROR 0x01000000 90#define PCI_STATUS_DEVSEL_FAST 0x00000000 91#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 92#define PCI_STATUS_DEVSEL_SLOW 0x04000000 93#define PCI_STATUS_DEVSEL_MASK 0x06000000 94#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 95#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 96#define PCI_STATUS_MASTER_ABORT 0x20000000 97#define PCI_STATUS_SPECIAL_ERROR 0x40000000 98#define PCI_STATUS_PARITY_DETECT 0x80000000 99 100#define PCI_COMMAND_STATUS_BITS \ 101 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 102 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 103 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 104 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 105 "\037SPECIAL_ERROR\040PARITY_DETECT") 106/* 107 * PCI Class and Revision Register; defines type and revision of device. 108 */ 109#define PCI_CLASS_REG 0x08 110 111typedef u_int8_t pci_class_t; 112typedef u_int8_t pci_subclass_t; 113typedef u_int8_t pci_interface_t; 114typedef u_int8_t pci_revision_t; 115 116#define PCI_CLASS_SHIFT 24 117#define PCI_CLASS_MASK 0xff 118#define PCI_CLASS(cr) \ 119 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 120 121#define PCI_SUBCLASS_SHIFT 16 122#define PCI_SUBCLASS_MASK 0xff 123#define PCI_SUBCLASS(cr) \ 124 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 125 126#define PCI_INTERFACE_SHIFT 8 127#define PCI_INTERFACE_MASK 0xff 128#define PCI_INTERFACE(cr) \ 129 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 130 131#define PCI_REVISION_SHIFT 0 132#define PCI_REVISION_MASK 0xff 133#define PCI_REVISION(cr) \ 134 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 135 136/* base classes */ 137#define PCI_CLASS_PREHISTORIC 0x00 138#define PCI_CLASS_MASS_STORAGE 0x01 139#define PCI_CLASS_NETWORK 0x02 140#define PCI_CLASS_DISPLAY 0x03 141#define PCI_CLASS_MULTIMEDIA 0x04 142#define PCI_CLASS_MEMORY 0x05 143#define PCI_CLASS_BRIDGE 0x06 144#define PCI_CLASS_COMMUNICATIONS 0x07 145#define PCI_CLASS_SYSTEM 0x08 146#define PCI_CLASS_INPUT 0x09 147#define PCI_CLASS_DOCK 0x0a 148#define PCI_CLASS_PROCESSOR 0x0b 149#define PCI_CLASS_SERIALBUS 0x0c 150#define PCI_CLASS_WIRELESS 0x0d 151#define PCI_CLASS_I2O 0x0e 152#define PCI_CLASS_SATCOM 0x0f 153#define PCI_CLASS_CRYPTO 0x10 154#define PCI_CLASS_DASP 0x11 155#define PCI_CLASS_UNDEFINED 0xff 156 157/* 0x00 prehistoric subclasses */ 158#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 159#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 160 161/* 0x01 mass storage subclasses */ 162#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 163#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 164#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 165#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 166#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 167#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 168#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 169#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07 170#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 171 172/* 0x02 network subclasses */ 173#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 174#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 175#define PCI_SUBCLASS_NETWORK_FDDI 0x02 176#define PCI_SUBCLASS_NETWORK_ATM 0x03 177#define PCI_SUBCLASS_NETWORK_ISDN 0x04 178#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 179#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 180#define PCI_SUBCLASS_NETWORK_MISC 0x80 181 182/* 0x03 display subclasses */ 183#define PCI_SUBCLASS_DISPLAY_VGA 0x00 184#define PCI_SUBCLASS_DISPLAY_XGA 0x01 185#define PCI_SUBCLASS_DISPLAY_3D 0x02 186#define PCI_SUBCLASS_DISPLAY_MISC 0x80 187 188/* 0x04 multimedia subclasses */ 189#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 190#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 191#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 192#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03 193#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 194 195/* 0x05 memory subclasses */ 196#define PCI_SUBCLASS_MEMORY_RAM 0x00 197#define PCI_SUBCLASS_MEMORY_FLASH 0x01 198#define PCI_SUBCLASS_MEMORY_MISC 0x80 199 200/* 0x06 bridge subclasses */ 201#define PCI_SUBCLASS_BRIDGE_HOST 0x00 202#define PCI_SUBCLASS_BRIDGE_ISA 0x01 203#define PCI_SUBCLASS_BRIDGE_EISA 0x02 204#define PCI_SUBCLASS_BRIDGE_MC 0x03 205#define PCI_SUBCLASS_BRIDGE_PCI 0x04 206#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 207#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 208#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 209#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 210#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 211#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 212#define PCI_SUBCLASS_BRIDGE_MISC 0x80 213 214/* 0x07 communications subclasses */ 215#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 216#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 217#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 218#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 219#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 220#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 221#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 222 223/* 0x08 system subclasses */ 224#define PCI_SUBCLASS_SYSTEM_PIC 0x00 225#define PCI_SUBCLASS_SYSTEM_DMA 0x01 226#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 227#define PCI_SUBCLASS_SYSTEM_RTC 0x03 228#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 229#define PCI_SUBCLASS_SYSTEM_SDHC 0x05 230#define PCI_SUBCLASS_SYSTEM_MISC 0x80 231 232/* 0x09 input subclasses */ 233#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 234#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 235#define PCI_SUBCLASS_INPUT_MOUSE 0x02 236#define PCI_SUBCLASS_INPUT_SCANNER 0x03 237#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 238#define PCI_SUBCLASS_INPUT_MISC 0x80 239 240/* 0x0a dock subclasses */ 241#define PCI_SUBCLASS_DOCK_GENERIC 0x00 242#define PCI_SUBCLASS_DOCK_MISC 0x80 243 244/* 0x0b processor subclasses */ 245#define PCI_SUBCLASS_PROCESSOR_386 0x00 246#define PCI_SUBCLASS_PROCESSOR_486 0x01 247#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 248#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 249#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 250#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 251#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 252 253/* 0x0c serial bus subclasses */ 254#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 255#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 256#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 257#define PCI_SUBCLASS_SERIALBUS_USB 0x03 258#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 259#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 260#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 261#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 262#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 263#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 264 265/* 0x0d wireless subclasses */ 266#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 267#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 268#define PCI_SUBCLASS_WIRELESS_RF 0x10 269#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 270#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 271#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 272#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 273#define PCI_SUBCLASS_WIRELESS_MISC 0x80 274 275/* 0x0e I2O (Intelligent I/O) subclasses */ 276#define PCI_SUBCLASS_I2O_STANDARD 0x00 277 278/* 0x0f satellite communication subclasses */ 279/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 280#define PCI_SUBCLASS_SATCOM_TV 0x01 281#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 282#define PCI_SUBCLASS_SATCOM_VOICE 0x03 283#define PCI_SUBCLASS_SATCOM_DATA 0x04 284 285/* 0x10 encryption/decryption subclasses */ 286#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 287#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 288#define PCI_SUBCLASS_CRYPTO_MISC 0x80 289 290/* 0x11 data acquisition and signal processing subclasses */ 291#define PCI_SUBCLASS_DASP_DPIO 0x00 292#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 293#define PCI_SUBCLASS_DASP_SYNC 0x10 294#define PCI_SUBCLASS_DASP_MGMT 0x20 295#define PCI_SUBCLASS_DASP_MISC 0x80 296 297/* 298 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 299 */ 300#define PCI_BHLC_REG 0x0c 301 302#define PCI_BIST_SHIFT 24 303#define PCI_BIST_MASK 0xff 304#define PCI_BIST(bhlcr) \ 305 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 306 307#define PCI_HDRTYPE_SHIFT 16 308#define PCI_HDRTYPE_MASK 0xff 309#define PCI_HDRTYPE(bhlcr) \ 310 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 311 312#define PCI_HDRTYPE_TYPE(bhlcr) \ 313 (PCI_HDRTYPE(bhlcr) & 0x7f) 314#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 315 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 316 317#define PCI_LATTIMER_SHIFT 8 318#define PCI_LATTIMER_MASK 0xff 319#define PCI_LATTIMER(bhlcr) \ 320 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 321 322#define PCI_CACHELINE_SHIFT 0 323#define PCI_CACHELINE_MASK 0xff 324#define PCI_CACHELINE(bhlcr) \ 325 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 326 327/* config registers for header type 0 devices */ 328 329#define PCI_MAPS 0x10 330#define PCI_CARDBUSCIS 0x28 331#define PCI_SUBVEND_0 0x2c 332#define PCI_SUBDEV_0 0x2e 333#define PCI_INTLINE 0x3c 334#define PCI_INTPIN 0x3d 335#define PCI_MINGNT 0x3e 336#define PCI_MAXLAT 0x3f 337 338/* config registers for header type 1 devices */ 339 340#define PCI_SECSTAT_1 0 /**/ 341 342#define PCI_PRIBUS_1 0x18 343#define PCI_SECBUS_1 0x19 344#define PCI_SUBBUS_1 0x1a 345#define PCI_SECLAT_1 0x1b 346 347#define PCI_IOBASEL_1 0x1c 348#define PCI_IOLIMITL_1 0x1d 349#define PCI_IOBASEH_1 0 /**/ 350#define PCI_IOLIMITH_1 0 /**/ 351 352#define PCI_MEMBASE_1 0x20 353#define PCI_MEMLIMIT_1 0x22 354 355#define PCI_PMBASEL_1 0x24 356#define PCI_PMLIMITL_1 0x26 357#define PCI_PMBASEH_1 0 /**/ 358#define PCI_PMLIMITH_1 0 /**/ 359 360#define PCI_BRIDGECTL_1 0 /**/ 361 362#define PCI_SUBVEND_1 0x34 363#define PCI_SUBDEV_1 0x36 364 365/* config registers for header type 2 devices */ 366 367#define PCI_SECSTAT_2 0x16 368 369#define PCI_PRIBUS_2 0x18 370#define PCI_SECBUS_2 0x19 371#define PCI_SUBBUS_2 0x1a 372#define PCI_SECLAT_2 0x1b 373 374#define PCI_MEMBASE0_2 0x1c 375#define PCI_MEMLIMIT0_2 0x20 376#define PCI_MEMBASE1_2 0x24 377#define PCI_MEMLIMIT1_2 0x28 378#define PCI_IOBASE0_2 0x2c 379#define PCI_IOLIMIT0_2 0x30 380#define PCI_IOBASE1_2 0x34 381#define PCI_IOLIMIT1_2 0x38 382 383#define PCI_BRIDGECTL_2 0x3e 384 385#define PCI_SUBVEND_2 0x40 386#define PCI_SUBDEV_2 0x42 387 388#define PCI_PCCARDIF_2 0x44 389 390/* 391 * Mapping registers 392 */ 393#define PCI_MAPREG_START 0x10 394#define PCI_MAPREG_END 0x28 395#define PCI_MAPREG_PPB_END 0x18 396#define PCI_MAPREG_PCB_END 0x14 397 398#define PCI_MAPREG_TYPE(mr) \ 399 ((mr) & PCI_MAPREG_TYPE_MASK) 400#define PCI_MAPREG_TYPE_MASK 0x00000001 401 402#define PCI_MAPREG_TYPE_MEM 0x00000000 403#define PCI_MAPREG_TYPE_IO 0x00000001 404 405#define PCI_MAPREG_MEM_TYPE(mr) \ 406 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 407#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 408 409#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 410#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 411#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 412 413#define _PCI_MAPREG_TYPEBITS(reg) \ 414 (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \ 415 reg & PCI_MAPREG_TYPE_MASK : \ 416 reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK)) 417 418#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 419 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 420#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 421 422#define PCI_MAPREG_MEM_ADDR(mr) \ 423 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 424#define PCI_MAPREG_MEM_SIZE(mr) \ 425 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 426#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 427 428#define PCI_MAPREG_MEM64_ADDR(mr) \ 429 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 430#define PCI_MAPREG_MEM64_SIZE(mr) \ 431 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 432#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 433 434#define PCI_MAPREG_IO_ADDR(mr) \ 435 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 436#define PCI_MAPREG_IO_SIZE(mr) \ 437 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 438#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 439 440/* 441 * Cardbus CIS pointer (PCI rev. 2.1) 442 */ 443#define PCI_CARDBUS_CIS_REG 0x28 444 445/* 446 * Subsystem identification register; contains a vendor ID and a device ID. 447 * Types/macros for PCI_ID_REG apply. 448 * (PCI rev. 2.1) 449 */ 450#define PCI_SUBSYS_ID_REG 0x2c 451 452/* 453 * Expansion ROM Base Address register 454 * (PCI rev. 2.0) 455 */ 456#define PCI_ROM_REG 0x30 457 458#define PCI_ROM_ENABLE 0x00000001 459#define PCI_ROM_ADDR_MASK 0xfffff800 460#define PCI_ROM_ADDR(mr) \ 461 ((mr) & PCI_ROM_ADDR_MASK) 462#define PCI_ROM_SIZE(mr) \ 463 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 464 465/* 466 * capabilities link list (PCI rev. 2.2) 467 */ 468#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 469#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 470#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 471#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 472#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 473 474#define PCI_CAP_RESERVED 0x00 475#define PCI_CAP_PWRMGMT 0x01 476#define PCI_CAP_AGP 0x02 477#define PCI_CAP_VPD 0x03 478#define PCI_CAP_SLOTID 0x04 479#define PCI_CAP_MSI 0x05 480#define PCI_CAP_CPCI_HOTSWAP 0x06 481#define PCI_CAP_PCIX 0x07 482#define PCI_CAP_HT 0x08 483#define PCI_CAP_VENDSPEC 0x09 484#define PCI_CAP_DEBUGPORT 0x0a 485#define PCI_CAP_CPCI_RSRCCTL 0x0b 486#define PCI_CAP_HOTPLUG 0x0c 487#define PCI_CAP_AGP8 0x0e 488#define PCI_CAP_SECURE 0x0f 489#define PCI_CAP_PCIEXPRESS 0x10 490#define PCI_CAP_MSIX 0x11 491#define PCI_CAP_SATA 0x12 492 493/* 494 * Vital Product Data; access via capability pointer (PCI rev 2.2). 495 */ 496#define PCI_VPD_ADDRESS_MASK 0x7fff 497#define PCI_VPD_ADDRESS_SHIFT 16 498#define PCI_VPD_ADDRESS(ofs) \ 499 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT) 500#define PCI_VPD_DATAREG(ofs) ((ofs) + 4) 501#define PCI_VPD_OPFLAG 0x80000000 502 503/* 504 * Message Signaled Interrups; access via capability pointer. 505 */ 506#define PCI_MSI_MC 0x00 507#define PCI_MSI_MC_C64 0x00800000 508#define PCI_MSI_MC_MME 0x00700000 509#define PCI_MSI_MC_MMC 0x000e0000 510#define PCI_MSI_MC_MSIE 0x00010000 511#define PCI_MSI_MA 0x04 512#define PCI_MSI_MAU32 0x08 513#define PCI_MSI_MD32 0x08 514#define PCI_MSI_MD64 0x0c 515 516/* 517 * Power Management Control Status Register; access via capability pointer. 518 */ 519#define PCI_PMCSR 0x04 520#define PCI_PMCSR_STATE_MASK 0x03 521#define PCI_PMCSR_STATE_D0 0x00 522#define PCI_PMCSR_STATE_D1 0x01 523#define PCI_PMCSR_STATE_D2 0x02 524#define PCI_PMCSR_STATE_D3 0x03 525 526/* 527 * HyperTransport; access via capability pointer. 528 */ 529#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \ 530 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f)) 531 532#define PCI_HT_CAP_SLAVE 0x00 533#define PCI_HT_CAP_HOST 0x04 534#define PCI_HT_CAP_INTERRUPT 0x10 535#define PCI_HT_CAP_MSI 0x15 536 537#define PCI_HT_MSI_ENABLED 0x00010000 538#define PCI_HT_MSI_FIXED 0x00020000 539 540#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL 541 542#define PCI_HT_MSI_ADDR 0x04 543#define PCI_HT_MSI_ADDR_HI32 0x08 544 545/* 546 * PCI Express; access via capability pointer. 547 */ 548#define PCI_PCIE_XCAP 0x00 549#define PCI_PCIE_XCAP_SI 0x01000000 550#define PCI_PCIE_DCAP 0x04 551#define PCI_PCIE_DCSR 0x08 552#define PCI_PCIE_DCSR_ENA_NO_SNOOP 0x00000800 553#define PCI_PCIE_LCAP 0x0c 554#define PCI_PCIE_LCSR 0x10 555#define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 556#define PCI_PCIE_LCSR_ASPM_L1 0x00000002 557#define PCI_PCIE_LCSR_ES 0x00000080 558#define PCI_PCIE_SLCAP 0x14 559#define PCI_PCIE_SLCAP_ABP 0x00000001 560#define PCI_PCIE_SLCAP_PCP 0x00000002 561#define PCI_PCIE_SLCAP_MSP 0x00000004 562#define PCI_PCIE_SLCAP_AIP 0x00000008 563#define PCI_PCIE_SLCAP_PIP 0x00000010 564#define PCI_PCIE_SLCAP_HPS 0x00000020 565#define PCI_PCIE_SLCAP_HPC 0x00000040 566#define PCI_PCIE_SLCSR 0x18 567#define PCI_PCIE_SLCSR_ABE 0x00000001 568#define PCI_PCIE_SLCSR_PFE 0x00000002 569#define PCI_PCIE_SLCSR_MSE 0x00000004 570#define PCI_PCIE_SLCSR_PDE 0x00000008 571#define PCI_PCIE_SLCSR_CCE 0x00000010 572#define PCI_PCIE_SLCSR_HPE 0x00000020 573#define PCI_PCIE_SLCSR_ABP 0x00010000 574#define PCI_PCIE_SLCSR_PFD 0x00020000 575#define PCI_PCIE_SLCSR_MSC 0x00040000 576#define PCI_PCIE_SLCSR_PDC 0x00080000 577#define PCI_PCIE_SLCSR_CC 0x00100000 578#define PCI_PCIE_SLCSR_MS 0x00200000 579#define PCI_PCIE_SLCSR_PDS 0x00400000 580#define PCI_PCIE_SLCSR_LACS 0x01000000 581#define PCI_PCIE_RCSR 0x1c 582 583/* 584 * Interrupt Configuration Register; contains interrupt pin and line. 585 */ 586#define PCI_INTERRUPT_REG 0x3c 587 588typedef u_int8_t pci_intr_pin_t; 589typedef u_int8_t pci_intr_line_t; 590 591#define PCI_INTERRUPT_PIN_SHIFT 8 592#define PCI_INTERRUPT_PIN_MASK 0xff 593#define PCI_INTERRUPT_PIN(icr) \ 594 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 595 596#define PCI_INTERRUPT_LINE_SHIFT 0 597#define PCI_INTERRUPT_LINE_MASK 0xff 598#define PCI_INTERRUPT_LINE(icr) \ 599 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 600 601#define PCI_MIN_GNT_SHIFT 16 602#define PCI_MIN_GNT_MASK 0xff 603#define PCI_MIN_GNT(icr) \ 604 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 605 606#define PCI_MAX_LAT_SHIFT 24 607#define PCI_MAX_LAT_MASK 0xff 608#define PCI_MAX_LAT(icr) \ 609 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 610 611#define PCI_INTERRUPT_PIN_NONE 0x00 612#define PCI_INTERRUPT_PIN_A 0x01 613#define PCI_INTERRUPT_PIN_B 0x02 614#define PCI_INTERRUPT_PIN_C 0x03 615#define PCI_INTERRUPT_PIN_D 0x04 616#define PCI_INTERRUPT_PIN_MAX 0x04 617 618/* 619 * Vital Product Data resource tags. 620 */ 621struct pci_vpd_smallres { 622 uint8_t vpdres_byte0; /* length of data + tag */ 623 /* Actual data. */ 624} __packed; 625 626struct pci_vpd_largeres { 627 uint8_t vpdres_byte0; 628 uint8_t vpdres_len_lsb; /* length of data only */ 629 uint8_t vpdres_len_msb; 630 /* Actual data. */ 631} __packed; 632 633#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 634 635#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 636#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 637 638#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 639 640#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 641#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 642#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 643 644#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 645#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 646 647struct pci_vpd { 648 uint8_t vpd_key0; 649 uint8_t vpd_key1; 650 uint8_t vpd_len; /* length of data only */ 651 /* Actual data. */ 652} __packed; 653 654/* 655 * Recommended VPD fields: 656 * 657 * PN Part number of assembly 658 * FN FRU part number 659 * EC EC level of assembly 660 * MN Manufacture ID 661 * SN Serial Number 662 * 663 * Conditionally recommended VPD fields: 664 * 665 * LI Load ID 666 * RL ROM Level 667 * RM Alterable ROM Level 668 * NA Network Address 669 * DD Device Driver Level 670 * DG Diagnostic Level 671 * LL Loadable Microcode Level 672 * VI Vendor ID/Device ID 673 * FU Function Number 674 * SI Subsystem Vendor ID/Subsystem ID 675 * 676 * Additional VPD fields: 677 * 678 * Z0-ZZ User/Product Specific 679 */ 680 681#endif /* _DEV_PCI_PCIREG_H_ */ 682