pcireg.h revision 1.28
1/* $OpenBSD: pcireg.h,v 1.28 2005/12/31 04:11:40 dlg Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61#define PCI_ID_CODE(vid,pid) \ 62 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \ 63 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) 64 65/* 66 * Command and status register. 67 */ 68#define PCI_COMMAND_STATUS_REG 0x04 69 70#define PCI_COMMAND_IO_ENABLE 0x00000001 71#define PCI_COMMAND_MEM_ENABLE 0x00000002 72#define PCI_COMMAND_MASTER_ENABLE 0x00000004 73#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 74#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 75#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 76#define PCI_COMMAND_PARITY_ENABLE 0x00000040 77#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 78#define PCI_COMMAND_SERR_ENABLE 0x00000100 79#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 80 81#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 82#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 83#define PCI_STATUS_UDF_SUPPORT 0x00400000 84#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 85#define PCI_STATUS_PARITY_ERROR 0x01000000 86#define PCI_STATUS_DEVSEL_FAST 0x00000000 87#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 88#define PCI_STATUS_DEVSEL_SLOW 0x04000000 89#define PCI_STATUS_DEVSEL_MASK 0x06000000 90#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 91#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 92#define PCI_STATUS_MASTER_ABORT 0x20000000 93#define PCI_STATUS_SPECIAL_ERROR 0x40000000 94#define PCI_STATUS_PARITY_DETECT 0x80000000 95 96#define PCI_COMMAND_STATUS_BITS \ 97 ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\ 98 "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\ 99 "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\ 100 "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\ 101 "\037SPECIAL_ERROR\040PARITY_DETECT") 102/* 103 * PCI Class and Revision Register; defines type and revision of device. 104 */ 105#define PCI_CLASS_REG 0x08 106 107typedef u_int8_t pci_class_t; 108typedef u_int8_t pci_subclass_t; 109typedef u_int8_t pci_interface_t; 110typedef u_int8_t pci_revision_t; 111 112#define PCI_CLASS_SHIFT 24 113#define PCI_CLASS_MASK 0xff 114#define PCI_CLASS(cr) \ 115 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 116 117#define PCI_SUBCLASS_SHIFT 16 118#define PCI_SUBCLASS_MASK 0xff 119#define PCI_SUBCLASS(cr) \ 120 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 121 122#define PCI_INTERFACE_SHIFT 8 123#define PCI_INTERFACE_MASK 0xff 124#define PCI_INTERFACE(cr) \ 125 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 126 127#define PCI_REVISION_SHIFT 0 128#define PCI_REVISION_MASK 0xff 129#define PCI_REVISION(cr) \ 130 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 131 132/* base classes */ 133#define PCI_CLASS_PREHISTORIC 0x00 134#define PCI_CLASS_MASS_STORAGE 0x01 135#define PCI_CLASS_NETWORK 0x02 136#define PCI_CLASS_DISPLAY 0x03 137#define PCI_CLASS_MULTIMEDIA 0x04 138#define PCI_CLASS_MEMORY 0x05 139#define PCI_CLASS_BRIDGE 0x06 140#define PCI_CLASS_COMMUNICATIONS 0x07 141#define PCI_CLASS_SYSTEM 0x08 142#define PCI_CLASS_INPUT 0x09 143#define PCI_CLASS_DOCK 0x0a 144#define PCI_CLASS_PROCESSOR 0x0b 145#define PCI_CLASS_SERIALBUS 0x0c 146#define PCI_CLASS_WIRELESS 0x0d 147#define PCI_CLASS_I2O 0x0e 148#define PCI_CLASS_SATCOM 0x0f 149#define PCI_CLASS_CRYPTO 0x10 150#define PCI_CLASS_DASP 0x11 151#define PCI_CLASS_UNDEFINED 0xff 152 153/* 0x00 prehistoric subclasses */ 154#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 155#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 156 157/* 0x01 mass storage subclasses */ 158#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 159#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 160#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 161#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 162#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 163#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 164#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06 165#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 166 167/* 0x02 network subclasses */ 168#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 169#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 170#define PCI_SUBCLASS_NETWORK_FDDI 0x02 171#define PCI_SUBCLASS_NETWORK_ATM 0x03 172#define PCI_SUBCLASS_NETWORK_ISDN 0x04 173#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 174#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 175#define PCI_SUBCLASS_NETWORK_MISC 0x80 176 177/* 0x03 display subclasses */ 178#define PCI_SUBCLASS_DISPLAY_VGA 0x00 179#define PCI_SUBCLASS_DISPLAY_XGA 0x01 180#define PCI_SUBCLASS_DISPLAY_3D 0x02 181#define PCI_SUBCLASS_DISPLAY_MISC 0x80 182 183/* 0x04 multimedia subclasses */ 184#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 185#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 186#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 187#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 188 189/* 0x05 memory subclasses */ 190#define PCI_SUBCLASS_MEMORY_RAM 0x00 191#define PCI_SUBCLASS_MEMORY_FLASH 0x01 192#define PCI_SUBCLASS_MEMORY_MISC 0x80 193 194/* 0x06 bridge subclasses */ 195#define PCI_SUBCLASS_BRIDGE_HOST 0x00 196#define PCI_SUBCLASS_BRIDGE_ISA 0x01 197#define PCI_SUBCLASS_BRIDGE_EISA 0x02 198#define PCI_SUBCLASS_BRIDGE_MC 0x03 199#define PCI_SUBCLASS_BRIDGE_PCI 0x04 200#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 201#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 202#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 203#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 204#define PCI_SUBCLASS_BRIDGE_STPCI 0x09 205#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a 206#define PCI_SUBCLASS_BRIDGE_MISC 0x80 207 208/* 0x07 communications subclasses */ 209#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 210#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 211#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 212#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 213#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 214#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 215#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 216 217/* 0x08 system subclasses */ 218#define PCI_SUBCLASS_SYSTEM_PIC 0x00 219#define PCI_SUBCLASS_SYSTEM_DMA 0x01 220#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 221#define PCI_SUBCLASS_SYSTEM_RTC 0x03 222#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 223#define PCI_SUBCLASS_SYSTEM_MISC 0x80 224 225/* 0x09 input subclasses */ 226#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 227#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 228#define PCI_SUBCLASS_INPUT_MOUSE 0x02 229#define PCI_SUBCLASS_INPUT_SCANNER 0x03 230#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 231#define PCI_SUBCLASS_INPUT_MISC 0x80 232 233/* 0x0a dock subclasses */ 234#define PCI_SUBCLASS_DOCK_GENERIC 0x00 235#define PCI_SUBCLASS_DOCK_MISC 0x80 236 237/* 0x0b processor subclasses */ 238#define PCI_SUBCLASS_PROCESSOR_386 0x00 239#define PCI_SUBCLASS_PROCESSOR_486 0x01 240#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 241#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 242#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 243#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 244#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 245 246/* 0x0c serial bus subclasses */ 247#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 248#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 249#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 250#define PCI_SUBCLASS_SERIALBUS_USB 0x03 251#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 252#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 253#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 254#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07 255#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 256#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 257 258/* 0x0d wireless subclasses */ 259#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 260#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 261#define PCI_SUBCLASS_WIRELESS_RF 0x10 262#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 263#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 264#define PCI_SUBCLASS_WIRELESS_802_11A 0x20 265#define PCI_SUBCLASS_WIRELESS_802_11B 0x21 266#define PCI_SUBCLASS_WIRELESS_MISC 0x80 267 268/* 0x0e I2O (Intelligent I/O) subclasses */ 269#define PCI_SUBCLASS_I2O_STANDARD 0x00 270 271/* 0x0f satellite communication subclasses */ 272/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */ 273#define PCI_SUBCLASS_SATCOM_TV 0x01 274#define PCI_SUBCLASS_SATCOM_AUDIO 0x02 275#define PCI_SUBCLASS_SATCOM_VOICE 0x03 276#define PCI_SUBCLASS_SATCOM_DATA 0x04 277 278/* 0x10 encryption/decryption subclasses */ 279#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 280#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 281#define PCI_SUBCLASS_CRYPTO_MISC 0x80 282 283/* 0x11 data acquisition and signal processing subclasses */ 284#define PCI_SUBCLASS_DASP_DPIO 0x00 285#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 286#define PCI_SUBCLASS_DASP_SYNC 0x10 287#define PCI_SUBCLASS_DASP_MGMT 0x20 288#define PCI_SUBCLASS_DASP_MISC 0x80 289 290/* 291 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 292 */ 293#define PCI_BHLC_REG 0x0c 294 295#define PCI_BIST_SHIFT 24 296#define PCI_BIST_MASK 0xff 297#define PCI_BIST(bhlcr) \ 298 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 299 300#define PCI_HDRTYPE_SHIFT 16 301#define PCI_HDRTYPE_MASK 0xff 302#define PCI_HDRTYPE(bhlcr) \ 303 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 304 305#define PCI_HDRTYPE_TYPE(bhlcr) \ 306 (PCI_HDRTYPE(bhlcr) & 0x7f) 307#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 308 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 309 310#define PCI_LATTIMER_SHIFT 8 311#define PCI_LATTIMER_MASK 0xff 312#define PCI_LATTIMER(bhlcr) \ 313 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 314 315#define PCI_CACHELINE_SHIFT 0 316#define PCI_CACHELINE_MASK 0xff 317#define PCI_CACHELINE(bhlcr) \ 318 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 319 320/* config registers for header type 0 devices */ 321 322#define PCI_MAPS 0x10 323#define PCI_CARDBUSCIS 0x28 324#define PCI_SUBVEND_0 0x2c 325#define PCI_SUBDEV_0 0x2e 326#define PCI_INTLINE 0x3c 327#define PCI_INTPIN 0x3d 328#define PCI_MINGNT 0x3e 329#define PCI_MAXLAT 0x3f 330 331/* config registers for header type 1 devices */ 332 333#define PCI_SECSTAT_1 0 /**/ 334 335#define PCI_PRIBUS_1 0x18 336#define PCI_SECBUS_1 0x19 337#define PCI_SUBBUS_1 0x1a 338#define PCI_SECLAT_1 0x1b 339 340#define PCI_IOBASEL_1 0x1c 341#define PCI_IOLIMITL_1 0x1d 342#define PCI_IOBASEH_1 0 /**/ 343#define PCI_IOLIMITH_1 0 /**/ 344 345#define PCI_MEMBASE_1 0x20 346#define PCI_MEMLIMIT_1 0x22 347 348#define PCI_PMBASEL_1 0x24 349#define PCI_PMLIMITL_1 0x26 350#define PCI_PMBASEH_1 0 /**/ 351#define PCI_PMLIMITH_1 0 /**/ 352 353#define PCI_BRIDGECTL_1 0 /**/ 354 355#define PCI_SUBVEND_1 0x34 356#define PCI_SUBDEV_1 0x36 357 358/* config registers for header type 2 devices */ 359 360#define PCI_SECSTAT_2 0x16 361 362#define PCI_PRIBUS_2 0x18 363#define PCI_SECBUS_2 0x19 364#define PCI_SUBBUS_2 0x1a 365#define PCI_SECLAT_2 0x1b 366 367#define PCI_MEMBASE0_2 0x1c 368#define PCI_MEMLIMIT0_2 0x20 369#define PCI_MEMBASE1_2 0x24 370#define PCI_MEMLIMIT1_2 0x28 371#define PCI_IOBASE0_2 0x2c 372#define PCI_IOLIMIT0_2 0x30 373#define PCI_IOBASE1_2 0x34 374#define PCI_IOLIMIT1_2 0x38 375 376#define PCI_BRIDGECTL_2 0x3e 377 378#define PCI_SUBVEND_2 0x40 379#define PCI_SUBDEV_2 0x42 380 381#define PCI_PCCARDIF_2 0x44 382 383/* 384 * Mapping registers 385 */ 386#define PCI_MAPREG_START 0x10 387#define PCI_MAPREG_END 0x28 388#define PCI_MAPREG_PPB_END 0x18 389#define PCI_MAPREG_PCB_END 0x14 390 391#define PCI_MAPREG_TYPE(mr) \ 392 ((mr) & PCI_MAPREG_TYPE_MASK) 393#define PCI_MAPREG_TYPE_MASK 0x00000001 394 395#define PCI_MAPREG_TYPE_MEM 0x00000000 396#define PCI_MAPREG_TYPE_IO 0x00000001 397 398#define PCI_MAPREG_MEM_TYPE(mr) \ 399 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 400#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 401 402#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 403#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 404#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 405 406#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \ 407 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) 408#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 409 410#define PCI_MAPREG_MEM_ADDR(mr) \ 411 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 412#define PCI_MAPREG_MEM_SIZE(mr) \ 413 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 414#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 415 416#define PCI_MAPREG_MEM64_ADDR(mr) \ 417 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 418#define PCI_MAPREG_MEM64_SIZE(mr) \ 419 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 420#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 421 422#define PCI_MAPREG_IO_ADDR(mr) \ 423 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 424#define PCI_MAPREG_IO_SIZE(mr) \ 425 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 426#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 427 428/* 429 * Cardbus CIS pointer (PCI rev. 2.1) 430 */ 431#define PCI_CARDBUS_CIS_REG 0x28 432 433/* 434 * Subsystem identification register; contains a vendor ID and a device ID. 435 * Types/macros for PCI_ID_REG apply. 436 * (PCI rev. 2.1) 437 */ 438#define PCI_SUBSYS_ID_REG 0x2c 439 440/* 441 * Expansion ROM Base Address register 442 * (PCI rev. 2.0) 443 */ 444#define PCI_ROM_REG 0x30 445 446#define PCI_ROM_ENABLE 0x00000001 447#define PCI_ROM_ADDR_MASK 0xfffff800 448#define PCI_ROM_ADDR(mr) \ 449 ((mr) & PCI_ROM_ADDR_MASK) 450#define PCI_ROM_SIZE(mr) \ 451 (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr)) 452 453/* 454 * capabilities link list (PCI rev. 2.2) 455 */ 456#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ 457#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ 458#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 459#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 460#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 461 462#define PCI_CAP_RESERVED 0x00 463#define PCI_CAP_PWRMGMT 0x01 464#define PCI_CAP_AGP 0x02 465#define PCI_CAP_VPD 0x03 466#define PCI_CAP_SLOTID 0x04 467#define PCI_CAP_MSI 0x05 468#define PCI_CAP_CPCI_HOTSWAP 0x06 469#define PCI_CAP_PCIX 0x07 470#define PCI_CAP_LDT 0x08 471#define PCI_CAP_VENDSPEC 0x09 472#define PCI_CAP_DEBUGPORT 0x0a 473#define PCI_CAP_CPCI_RSRCCTL 0x0b 474#define PCI_CAP_HOTPLUG 0x0c 475#define PCI_CAP_AGP8 0x0e 476#define PCI_CAP_SECURE 0x0f 477#define PCI_CAP_PCIEXPRESS 0x10 478#define PCI_CAP_MSIX 0x11 479 480/* 481 * Power Management Control Status Register; access via capability pointer. 482 */ 483#define PCI_PMCSR 0x04 484#define PCI_PMCSR_STATE_MASK 0x03 485#define PCI_PMCSR_STATE_D0 0x00 486#define PCI_PMCSR_STATE_D1 0x01 487#define PCI_PMCSR_STATE_D2 0x02 488#define PCI_PMCSR_STATE_D3 0x03 489 490/* 491 * Interrupt Configuration Register; contains interrupt pin and line. 492 */ 493#define PCI_INTERRUPT_REG 0x3c 494 495typedef u_int8_t pci_intr_pin_t; 496typedef u_int8_t pci_intr_line_t; 497 498#define PCI_INTERRUPT_PIN_SHIFT 8 499#define PCI_INTERRUPT_PIN_MASK 0xff 500#define PCI_INTERRUPT_PIN(icr) \ 501 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 502 503#define PCI_INTERRUPT_LINE_SHIFT 0 504#define PCI_INTERRUPT_LINE_MASK 0xff 505#define PCI_INTERRUPT_LINE(icr) \ 506 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 507 508#define PCI_MIN_GNT_SHIFT 16 509#define PCI_MIN_GNT_MASK 0xff 510#define PCI_MIN_GNT(icr) \ 511 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) 512 513#define PCI_MAX_LAT_SHIFT 24 514#define PCI_MAX_LAT_MASK 0xff 515#define PCI_MAX_LAT(icr) \ 516 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) 517 518#define PCI_INTERRUPT_PIN_NONE 0x00 519#define PCI_INTERRUPT_PIN_A 0x01 520#define PCI_INTERRUPT_PIN_B 0x02 521#define PCI_INTERRUPT_PIN_C 0x03 522#define PCI_INTERRUPT_PIN_D 0x04 523#define PCI_INTERRUPT_PIN_MAX 0x04 524 525/* 526 * Vital Product Data resource tags. 527 */ 528struct pci_vpd_smallres { 529 uint8_t vpdres_byte0; /* length of data + tag */ 530 /* Actual data. */ 531} __packed; 532 533struct pci_vpd_largeres { 534 uint8_t vpdres_byte0; 535 uint8_t vpdres_len_lsb; /* length of data only */ 536 uint8_t vpdres_len_msb; 537 /* Actual data. */ 538} __packed; 539 540#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 541 542#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) 543#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) 544 545#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 546 547#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ 548#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ 549#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */ 550 551#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ 552#define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 553 554struct pci_vpd { 555 uint8_t vpd_key0; 556 uint8_t vpd_key1; 557 uint8_t vpd_len; /* length of data only */ 558 /* Actual data. */ 559} __packed; 560 561/* 562 * Recommended VPD fields: 563 * 564 * PN Part number of assembly 565 * FN FRU part number 566 * EC EC level of assembly 567 * MN Manufacture ID 568 * SN Serial Number 569 * 570 * Conditionally recommended VPD fields: 571 * 572 * LI Load ID 573 * RL ROM Level 574 * RM Alterable ROM Level 575 * NA Network Address 576 * DD Device Driver Level 577 * DG Diagnostic Level 578 * LL Loadable Microcode Level 579 * VI Vendor ID/Device ID 580 * FU Function Number 581 * SI Subsystem Vendor ID/Subsystem ID 582 * 583 * Additional VPD fields: 584 * 585 * Z0-ZZ User/Product Specific 586 */ 587 588#endif /* _DEV_PCI_PCIREG_H_ */ 589