pcireg.h revision 1.14
1/* $OpenBSD: pcireg.h,v 1.14 2000/09/20 17:39:05 niklas Exp $ */ 2/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved. 6 * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles Hannum. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef _DEV_PCI_PCIREG_H_ 35#define _DEV_PCI_PCIREG_H_ 36 37/* 38 * Standardized PCI configuration information 39 * 40 * XXX This is not complete. 41 */ 42 43/* 44 * Device identification register; contains a vendor ID and a device ID. 45 */ 46#define PCI_ID_REG 0x00 47 48typedef u_int16_t pci_vendor_id_t; 49typedef u_int16_t pci_product_id_t; 50 51#define PCI_VENDOR_SHIFT 0 52#define PCI_VENDOR_MASK 0xffff 53#define PCI_VENDOR(id) \ 54 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) 55 56#define PCI_PRODUCT_SHIFT 16 57#define PCI_PRODUCT_MASK 0xffff 58#define PCI_PRODUCT(id) \ 59 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) 60 61/* 62 * Command and status register. 63 */ 64#define PCI_COMMAND_STATUS_REG 0x04 65 66#define PCI_COMMAND_IO_ENABLE 0x00000001 67#define PCI_COMMAND_MEM_ENABLE 0x00000002 68#define PCI_COMMAND_MASTER_ENABLE 0x00000004 69#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008 70#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 71#define PCI_COMMAND_PALETTE_ENABLE 0x00000020 72#define PCI_COMMAND_PARITY_ENABLE 0x00000040 73#define PCI_COMMAND_STEPPING_ENABLE 0x00000080 74#define PCI_COMMAND_SERR_ENABLE 0x00000100 75#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 76 77#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000 78#define PCI_STATUS_66MHZ_SUPPORT 0x00200000 79#define PCI_STATUS_UDF_SUPPORT 0x00400000 80#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 81#define PCI_STATUS_PARITY_ERROR 0x01000000 82#define PCI_STATUS_DEVSEL_FAST 0x00000000 83#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000 84#define PCI_STATUS_DEVSEL_SLOW 0x04000000 85#define PCI_STATUS_DEVSEL_MASK 0x06000000 86#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 87#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 88#define PCI_STATUS_MASTER_ABORT 0x20000000 89#define PCI_STATUS_SPECIAL_ERROR 0x40000000 90#define PCI_STATUS_PARITY_DETECT 0x80000000 91 92/* 93 * PCI Class and Revision Register; defines type and revision of device. 94 */ 95#define PCI_CLASS_REG 0x08 96 97typedef u_int8_t pci_class_t; 98typedef u_int8_t pci_subclass_t; 99typedef u_int8_t pci_interface_t; 100typedef u_int8_t pci_revision_t; 101 102#define PCI_CLASS_SHIFT 24 103#define PCI_CLASS_MASK 0xff 104#define PCI_CLASS(cr) \ 105 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) 106 107#define PCI_SUBCLASS_SHIFT 16 108#define PCI_SUBCLASS_MASK 0xff 109#define PCI_SUBCLASS(cr) \ 110 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) 111 112#define PCI_INTERFACE_SHIFT 8 113#define PCI_INTERFACE_MASK 0xff 114#define PCI_INTERFACE(cr) \ 115 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) 116 117#define PCI_REVISION_SHIFT 0 118#define PCI_REVISION_MASK 0xff 119#define PCI_REVISION(cr) \ 120 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) 121 122/* base classes */ 123#define PCI_CLASS_PREHISTORIC 0x00 124#define PCI_CLASS_MASS_STORAGE 0x01 125#define PCI_CLASS_NETWORK 0x02 126#define PCI_CLASS_DISPLAY 0x03 127#define PCI_CLASS_MULTIMEDIA 0x04 128#define PCI_CLASS_MEMORY 0x05 129#define PCI_CLASS_BRIDGE 0x06 130#define PCI_CLASS_COMMUNICATIONS 0x07 131#define PCI_CLASS_SYSTEM 0x08 132#define PCI_CLASS_INPUT 0x09 133#define PCI_CLASS_DOCK 0x0a 134#define PCI_CLASS_PROCESSOR 0x0b 135#define PCI_CLASS_SERIALBUS 0x0c 136#define PCI_CLASS_UNDEFINED 0xff 137 138/* 0x00 prehistoric subclasses */ 139#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 140#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 141 142/* 0x01 mass storage subclasses */ 143#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 144#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 145#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 146#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 147#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 148#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 149 150/* 0x02 network subclasses */ 151#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 152#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 153#define PCI_SUBCLASS_NETWORK_FDDI 0x02 154#define PCI_SUBCLASS_NETWORK_ATM 0x03 155#define PCI_SUBCLASS_NETWORK_MISC 0x80 156 157/* 0x03 display subclasses */ 158#define PCI_SUBCLASS_DISPLAY_VGA 0x00 159#define PCI_SUBCLASS_DISPLAY_XGA 0x01 160#define PCI_SUBCLASS_DISPLAY_MISC 0x80 161 162/* 0x04 multimedia subclasses */ 163#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 164#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 165#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 166 167/* 0x05 memory subclasses */ 168#define PCI_SUBCLASS_MEMORY_RAM 0x00 169#define PCI_SUBCLASS_MEMORY_FLASH 0x01 170#define PCI_SUBCLASS_MEMORY_MISC 0x80 171 172/* 0x06 bridge subclasses */ 173#define PCI_SUBCLASS_BRIDGE_HOST 0x00 174#define PCI_SUBCLASS_BRIDGE_ISA 0x01 175#define PCI_SUBCLASS_BRIDGE_EISA 0x02 176#define PCI_SUBCLASS_BRIDGE_MC 0x03 177#define PCI_SUBCLASS_BRIDGE_PCI 0x04 178#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 179#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06 180#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 181#define PCI_SUBCLASS_BRIDGE_MISC 0x80 182 183/* 0x07 communications subclasses */ 184#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 185#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 186#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 187 188/* 0x08 system subclasses */ 189#define PCI_SUBCLASS_SYSTEM_PIC 0x00 190#define PCI_SUBCLASS_SYSTEM_DMA 0x01 191#define PCI_SUBCLASS_SYSTEM_TIMER 0x02 192#define PCI_SUBCLASS_SYSTEM_RTC 0x03 193#define PCI_SUBCLASS_SYSTEM_MISC 0x80 194 195/* 0x09 input subclasses */ 196#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 197#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 198#define PCI_SUBCLASS_INPUT_MOUSE 0x02 199#define PCI_SUBCLASS_INPUT_MISC 0x80 200 201/* 0x0a dock subclasses */ 202#define PCI_SUBCLASS_DOCK_GENERIC 0x00 203#define PCI_SUBCLASS_DOCK_MISC 0x80 204 205/* 0x0b processor subclasses */ 206#define PCI_SUBCLASS_PROCESSOR_386 0x00 207#define PCI_SUBCLASS_PROCESSOR_486 0x01 208#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 209#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 210#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 211#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 212 213/* 0x0c serial bus subclasses */ 214#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 215#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 216#define PCI_SUBCLASS_SERIALBUS_SSA 0x02 217#define PCI_SUBCLASS_SERIALBUS_USB 0x03 218#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 219 220/* 221 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register. 222 */ 223#define PCI_BHLC_REG 0x0c 224 225#define PCI_BIST_SHIFT 24 226#define PCI_BIST_MASK 0xff 227#define PCI_BIST(bhlcr) \ 228 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) 229 230#define PCI_HDRTYPE_SHIFT 16 231#define PCI_HDRTYPE_MASK 0xff 232#define PCI_HDRTYPE(bhlcr) \ 233 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) 234 235#define PCI_HDRTYPE_TYPE(bhlcr) \ 236 (PCI_HDRTYPE(bhlcr) & 0x7f) 237#define PCI_HDRTYPE_MULTIFN(bhlcr) \ 238 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) 239 240#define PCI_LATTIMER_SHIFT 8 241#define PCI_LATTIMER_MASK 0xff 242#define PCI_LATTIMER(bhlcr) \ 243 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) 244 245#define PCI_CACHELINE_SHIFT 0 246#define PCI_CACHELINE_MASK 0xff 247#define PCI_CACHELINE(bhlcr) \ 248 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) 249 250/* config registers for header type 0 devices */ 251 252#define PCI_MAPS 0x10 253#define PCI_CARDBUSCIS 0x28 254#define PCI_SUBVEND_0 0x2c 255#define PCI_SUBDEV_0 0x2e 256#define PCI_INTLINE 0x3c 257#define PCI_INTPIN 0x3d 258#define PCI_MINGNT 0x3e 259#define PCI_MAXLAT 0x3f 260 261/* config registers for header type 1 devices */ 262 263#define PCI_SECSTAT_1 0 /**/ 264 265#define PCI_PRIBUS_1 0x18 266#define PCI_SECBUS_1 0x19 267#define PCI_SUBBUS_1 0x1a 268#define PCI_SECLAT_1 0x1b 269 270#define PCI_IOBASEL_1 0x1c 271#define PCI_IOLIMITL_1 0x1d 272#define PCI_IOBASEH_1 0 /**/ 273#define PCI_IOLIMITH_1 0 /**/ 274 275#define PCI_MEMBASE_1 0x20 276#define PCI_MEMLIMIT_1 0x22 277 278#define PCI_PMBASEL_1 0x24 279#define PCI_PMLIMITL_1 0x26 280#define PCI_PMBASEH_1 0 /**/ 281#define PCI_PMLIMITH_1 0 /**/ 282 283#define PCI_BRIDGECTL_1 0 /**/ 284 285#define PCI_SUBVEND_1 0x34 286#define PCI_SUBDEV_1 0x36 287 288/* config registers for header type 2 devices */ 289 290#define PCI_SECSTAT_2 0x16 291 292#define PCI_PRIBUS_2 0x18 293#define PCI_SECBUS_2 0x19 294#define PCI_SUBBUS_2 0x1a 295#define PCI_SECLAT_2 0x1b 296 297#define PCI_MEMBASE0_2 0x1c 298#define PCI_MEMLIMIT0_2 0x20 299#define PCI_MEMBASE1_2 0x24 300#define PCI_MEMLIMIT1_2 0x28 301#define PCI_IOBASE0_2 0x2c 302#define PCI_IOLIMIT0_2 0x30 303#define PCI_IOBASE1_2 0x34 304#define PCI_IOLIMIT1_2 0x38 305 306#define PCI_BRIDGECTL_2 0x3e 307 308#define PCI_SUBVEND_2 0x40 309#define PCI_SUBDEV_2 0x42 310 311#define PCI_PCCARDIF_2 0x44 312 313/* 314 * Mapping registers 315 */ 316#define PCI_MAPREG_START 0x10 317#define PCI_MAPREG_END 0x28 318#define PCI_MAPREG_PPB_END 0x18 319#define PCI_MAPREG_PCB_END 0x14 320 321#define PCI_MAPREG_TYPE(mr) \ 322 ((mr) & PCI_MAPREG_TYPE_MASK) 323#define PCI_MAPREG_TYPE_MASK 0x00000001 324 325#define PCI_MAPREG_TYPE_MEM 0x00000000 326#define PCI_MAPREG_TYPE_IO 0x00000001 327 328#define PCI_MAPREG_MEM_TYPE(mr) \ 329 ((mr) & PCI_MAPREG_MEM_TYPE_MASK) 330#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006 331 332#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 333#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 334#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 335 336#define PCI_MAPREG_MEM_CACHEABLE(mr) \ 337 (((mr) & PCI_MAPREG_MEM_CACHEABLE_MASK) != 0) 338#define PCI_MAPREG_MEM_CACHEABLE_MASK 0x00000008 339 340#define PCI_MAPREG_MEM_ADDR(mr) \ 341 ((mr) & PCI_MAPREG_MEM_ADDR_MASK) 342#define PCI_MAPREG_MEM_SIZE(mr) \ 343 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) 344#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 345 346#define PCI_MAPREG_MEM64_ADDR(mr) \ 347 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) 348#define PCI_MAPREG_MEM64_SIZE(mr) \ 349 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) 350#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0 351 352#define PCI_MAPREG_IO_ADDR(mr) \ 353 ((mr) & PCI_MAPREG_IO_ADDR_MASK) 354#define PCI_MAPREG_IO_SIZE(mr) \ 355 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 356#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe 357 358/* 359 * Cardbus CIS pointer (PCI rev. 2.1) 360 */ 361#define PCI_CARDBUS_CIS_REG 0x28 362 363/* 364 * Subsystem identification register; contains a vendor ID and a device ID. 365 * Types/macros for PCI_ID_REG apply. 366 * (PCI rev. 2.1) 367 */ 368#define PCI_SUBSYS_ID_REG 0x2c 369 370/* 371 * capabilities link list (PCI rev. 2.2) 372 */ 373#define PCI_CAPLISTPTR_REG 0x34 374#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) 375#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) 376#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff) 377#define PCI_CAP_PWRMGMT 1 378#define PCI_CAP_AGP 2 379#define PCI_CAP_VPD 3 380#define PCI_CAP_SLOTID 4 381#define PCI_CAP_MBI 5 382#define PCI_CAP_HOTSWAP 6 383 384/* 385 * Interrupt Configuration Register; contains interrupt pin and line. 386 */ 387#define PCI_INTERRUPT_REG 0x3c 388 389typedef u_int8_t pci_intr_pin_t; 390typedef u_int8_t pci_intr_line_t; 391 392#define PCI_INTERRUPT_PIN_SHIFT 8 393#define PCI_INTERRUPT_PIN_MASK 0xff 394#define PCI_INTERRUPT_PIN(icr) \ 395 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) 396 397#define PCI_INTERRUPT_LINE_SHIFT 0 398#define PCI_INTERRUPT_LINE_MASK 0xff 399#define PCI_INTERRUPT_LINE(icr) \ 400 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) 401 402#define PCI_INTERRUPT_PIN_NONE 0x00 403#define PCI_INTERRUPT_PIN_A 0x01 404#define PCI_INTERRUPT_PIN_B 0x02 405#define PCI_INTERRUPT_PIN_C 0x03 406#define PCI_INTERRUPT_PIN_D 0x04 407#define PCI_INTERRUPT_PIN_MAX 0x04 408 409#endif /* _DEV_PCI_PCIREG_H_ */ 410