/linux-master/kernel/sched/ |
H A D | fair.c | 35 #include <linux/sched/clock.h> 4161 * The rq clock has already been updated in 4163 * the rq clock again in unthrottle_cfs_rq(). 4506 * we know we are at the greatest risk to have an outdated clock. 4538 /* The clock has been stopped for throttling */ 5584 * directly instead of rq->clock to avoid adding additional synchronization 6500 * The rq clock has already been updated in the 6502 * the rq clock again in unthrottle_cfs_rq(). 8240 * the current rq's clock. But if that clock has [all...] |
H A D | sched.h | 233 * atomically change clock frequency. Remove once fast switching will be 394 * load_avg can be heavily contended at clock tick time, so put 1042 u64 clock; member in struct:rq 1487 * %RQCF_REQ_SKIP - will request skipping of clock update on the next 1489 * neighbouring rq clock updates. 1514 * The only reason for not seeing a clock update since the 1525 return rq->clock; 1574 * rq_clock_start_loop_update() can be called after updating the clock 3345 WRITE_ONCE(pcpu_cid->time, rq->clock);
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/linux-master/arch/x86/kernel/cpu/ |
H A D | amd.c | 9 #include <linux/sched/clock.h>
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/linux-master/net/bluetooth/ |
H A D | mgmt.c | 7407 rp.local_clock = cpu_to_le32(hdev->clock); 7410 rp.piconet_clock = cpu_to_le32(conn->clock); 7438 hci_cp.which = 0x01; /* Piconet clock */
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H A D | hci_event.c | 1112 hdev->clock = le32_to_cpu(rp->clock); 1118 conn->clock = le32_to_cpu(rp->clock);
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/linux-master/include/net/bluetooth/ |
H A D | hci_core.h | 438 __u32 clock; member in struct:hci_dev 754 __u32 clock; member in struct:hci_conn
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/linux-master/drivers/net/ethernet/wangxun/txgbe/ |
H A D | txgbe_phy.c | 57 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 570 struct clk_lookup *clock; local 581 clock = clkdev_create(clk, NULL, clk_name); 582 if (!clock) { 588 txgbe->clock = clock; 756 wx_err(wx, "failed to register clock: %d\n", ret); 777 clkdev_drop(txgbe->clock); 799 clkdev_drop(txgbe->clock);
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/linux-master/drivers/net/ethernet/renesas/ |
H A D | ravb_main.c | 1717 info->phc_index = ptp_clock_index(priv->ptp.clock); 1827 /* Set tx and rx clock internal delay modes */
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/linux-master/drivers/mmc/host/ |
H A D | sdhci-of-dwcmshc.c | 122 /* PHY clock pad settings */ 177 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 235 return pltfm_host->clock; 458 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) argument 469 if (clock == 0) { 470 /* Disable interface clock at initial state. */ 471 sdhci_set_clock(host, clock); 476 if (clock <= 400000) 477 clock = 375000; 479 err = clk_set_rate(pltfm_host->clk, clock); [all...] |
H A D | sdhci-msm.c | 263 struct clk *bus_clk; /* SDHC bus voter clock */ 341 * The SDHC requires internal clock frequency to be double the 342 * actual clock that will be set for DDR mode. The controller 343 * uses the faster clock(100/400MHz) for some of its parts and 344 * send the actual required clock (50/200MHz) to the card. 355 unsigned int clock) 367 desired_rate = clock * mult; 370 pr_err("%s: Failed to set clock at rate %u at timing %d\n", 376 * Qualcomm clock drivers by default round clock _up 354 msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, unsigned int clock) argument 1766 __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) argument 1785 sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) argument [all...] |
H A D | moxart-mmc.c | 489 if (ios->clock) { 491 if (ios->clock >= host->sysclk / (2 * (div + 1)))
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/linux-master/drivers/gpu/drm/etnaviv/ |
H A D | etnaviv_gpu.c | 473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) argument 475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); local 492 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 493 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 494 etnaviv_gpu_load_clock(gpu, clock); 519 /* disable clock gating */ 528 /* enable clock */ 595 /* We rely on the GPU running, so program the clock */ [all...] |
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 664 * If there aren't any active_planes then DCH HUBP may be clock-gated. 2491 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2493 * boot up: dc calculate dcn watermark clock settings within dc_create, 2501 * For Renoir, clock settings of dcn watermark are also fixed values. 5599 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5698 timing_out->pix_clk_100hz = mode_in->clock * 10; 5800 } else if (native_mode->clock == drm_mode->clock && 5937 if (aconnector->freesync_vid_base.clock != 0) 5992 if (high_mode->clock 7136 int clock, bpp = 0; local [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v9_0.c | 2469 /* These interrupts should be enabled to drive DS clock */ 3811 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3989 pr_err("failed to read gpu clock\n"); 3995 uint64_t clock, clock_lo, clock_hi, hi_check; local 4003 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 4011 clock = clock_lo | (clock_hi << 32ULL); 4019 clock = gfx_v9_0_kiq_read_clock(adev); 4022 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4029 return clock;
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H A D | gfx_v11_0.c | 4660 uint64_t clock; local 4682 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 4684 return clock;
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H A D | gfx_v10_0.c | 7336 uint64_t clock, clock_lo, clock_hi, hi_check; local 7345 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7353 clock = clock_lo | (clock_hi << 32ULL); 7362 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7370 clock = clock_lo | (clock_hi << 32ULL); 7377 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7385 clock = clock_lo | (clock_hi << 32ULL); 7392 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7400 clock = clock_lo | (clock_hi << 32ULL); 7403 return clock; [all...] |
/linux-master/fs/bcachefs/ |
H A D | journal_io.c | 622 struct jset_entry_clock *clock = local 627 if (journal_entry_err_on(bytes != sizeof(*clock), 635 if (journal_entry_err_on(clock->rw > 1, 650 struct jset_entry_clock *clock = local 653 prt_printf(out, "%s=%llu", clock->rw ? "write" : "read", le64_to_cpu(clock->time));
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H A D | recovery.c | 394 struct jset_entry_clock *clock = local 397 atomic64_set(&c->io_clock[clock->rw].now, le64_to_cpu(clock->time));
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H A D | sb-clean.c | 259 struct jset_entry_clock *clock = local 260 container_of(jset_entry_init(end, sizeof(*clock)), 263 clock->entry.type = BCH_JSET_ENTRY_clock; 264 clock->rw = i; 265 clock->time = cpu_to_le64(atomic64_read(&c->io_clock[i].now));
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H A D | btree_gc.c | 21 #include "clock.h" 1991 struct io_clock *clock = &c->io_clock[WRITE]; local 1992 unsigned long last = atomic64_read(&clock->now); 2012 if (atomic64_read(&clock->now) >= next) 2015 bch2_io_clock_schedule_timeout(clock, next); 2024 last = atomic64_read(&clock->now);
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H A D | bcachefs_format.h | 1313 x(clock, 7) \
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/linux-master/drivers/usb/typec/tcpm/ |
H A D | tcpm.c | 20 #include <linux/sched/clock.h>
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/linux-master/drivers/tty/serial/8250/ |
H A D | 8250_pci.c | 560 /* Change clock frequency for the first UART. */ 1116 * Determine the oversampling rate, the clock prescaler, and the clock 1117 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1120 * to use a scaled clock rate, which is the baud base multiplied by 32 1121 * (or our assumed UART clock rate multiplied by 2). 1124 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1126 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1130 * oversampling rates and clock prescalers that records all possible 1138 * rate and a clock prescale 1456 unsigned long clock; local [all...] |
/linux-master/drivers/clk/mediatek/ |
H A D | clk-mt7988-infracfg.c | 16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
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/linux-master/arch/x86/kvm/ |
H A D | x86.c | 2261 struct pvclock_clock clock; /* extract of a clocksource struct */ member in struct:pvclock_gtod_data 2277 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; 2278 vdata->clock.cycle_last = tk->tkr_mono.cycle_last; 2279 vdata->clock.mask = tk->tkr_mono.mask; 2280 vdata->clock.mult = tk->tkr_mono.mult; 2281 vdata->clock.shift = tk->tkr_mono.shift; 2282 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; 2283 vdata->clock.offset = tk->tkr_mono.base; 2285 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock 2825 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, int *mode) argument [all...] |