1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6#include <linux/clk.h> 7#include <linux/component.h> 8#include <linux/delay.h> 9#include <linux/dma-fence.h> 10#include <linux/dma-mapping.h> 11#include <linux/mod_devicetable.h> 12#include <linux/module.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/regulator/consumer.h> 16#include <linux/thermal.h> 17 18#include "etnaviv_cmdbuf.h" 19#include "etnaviv_dump.h" 20#include "etnaviv_gpu.h" 21#include "etnaviv_gem.h" 22#include "etnaviv_mmu.h" 23#include "etnaviv_perfmon.h" 24#include "etnaviv_sched.h" 25#include "common.xml.h" 26#include "state.xml.h" 27#include "state_hi.xml.h" 28#include "cmdstream.xml.h" 29 30static const struct platform_device_id gpu_ids[] = { 31 { .name = "etnaviv-gpu,2d" }, 32 { }, 33}; 34 35/* 36 * Driver functions: 37 */ 38 39int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 40{ 41 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 42 43 switch (param) { 44 case ETNAVIV_PARAM_GPU_MODEL: 45 *value = gpu->identity.model; 46 break; 47 48 case ETNAVIV_PARAM_GPU_REVISION: 49 *value = gpu->identity.revision; 50 break; 51 52 case ETNAVIV_PARAM_GPU_FEATURES_0: 53 *value = gpu->identity.features; 54 break; 55 56 case ETNAVIV_PARAM_GPU_FEATURES_1: 57 *value = gpu->identity.minor_features0; 58 break; 59 60 case ETNAVIV_PARAM_GPU_FEATURES_2: 61 *value = gpu->identity.minor_features1; 62 break; 63 64 case ETNAVIV_PARAM_GPU_FEATURES_3: 65 *value = gpu->identity.minor_features2; 66 break; 67 68 case ETNAVIV_PARAM_GPU_FEATURES_4: 69 *value = gpu->identity.minor_features3; 70 break; 71 72 case ETNAVIV_PARAM_GPU_FEATURES_5: 73 *value = gpu->identity.minor_features4; 74 break; 75 76 case ETNAVIV_PARAM_GPU_FEATURES_6: 77 *value = gpu->identity.minor_features5; 78 break; 79 80 case ETNAVIV_PARAM_GPU_FEATURES_7: 81 *value = gpu->identity.minor_features6; 82 break; 83 84 case ETNAVIV_PARAM_GPU_FEATURES_8: 85 *value = gpu->identity.minor_features7; 86 break; 87 88 case ETNAVIV_PARAM_GPU_FEATURES_9: 89 *value = gpu->identity.minor_features8; 90 break; 91 92 case ETNAVIV_PARAM_GPU_FEATURES_10: 93 *value = gpu->identity.minor_features9; 94 break; 95 96 case ETNAVIV_PARAM_GPU_FEATURES_11: 97 *value = gpu->identity.minor_features10; 98 break; 99 100 case ETNAVIV_PARAM_GPU_FEATURES_12: 101 *value = gpu->identity.minor_features11; 102 break; 103 104 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 105 *value = gpu->identity.stream_count; 106 break; 107 108 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 109 *value = gpu->identity.register_max; 110 break; 111 112 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 113 *value = gpu->identity.thread_count; 114 break; 115 116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 117 *value = gpu->identity.vertex_cache_size; 118 break; 119 120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 121 *value = gpu->identity.shader_core_count; 122 break; 123 124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 125 *value = gpu->identity.pixel_pipes; 126 break; 127 128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 129 *value = gpu->identity.vertex_output_buffer_size; 130 break; 131 132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 133 *value = gpu->identity.buffer_size; 134 break; 135 136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 137 *value = gpu->identity.instruction_count; 138 break; 139 140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 141 *value = gpu->identity.num_constants; 142 break; 143 144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 145 *value = gpu->identity.varyings_count; 146 break; 147 148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 150 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 151 else 152 *value = ~0ULL; 153 break; 154 155 case ETNAVIV_PARAM_GPU_PRODUCT_ID: 156 *value = gpu->identity.product_id; 157 break; 158 159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 160 *value = gpu->identity.customer_id; 161 break; 162 163 case ETNAVIV_PARAM_GPU_ECO_ID: 164 *value = gpu->identity.eco_id; 165 break; 166 167 default: 168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 169 return -EINVAL; 170 } 171 172 return 0; 173} 174 175 176#define etnaviv_is_model_rev(gpu, mod, rev) \ 177 ((gpu)->identity.model == chipModel_##mod && \ 178 (gpu)->identity.revision == rev) 179#define etnaviv_field(val, field) \ 180 (((val) & field##__MASK) >> field##__SHIFT) 181 182static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 183{ 184 if (gpu->identity.minor_features0 & 185 chipMinorFeatures0_MORE_MINOR_FEATURES) { 186 u32 specs[4]; 187 unsigned int streams; 188 189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 193 194 gpu->identity.stream_count = etnaviv_field(specs[0], 195 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 196 gpu->identity.register_max = etnaviv_field(specs[0], 197 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 198 gpu->identity.thread_count = etnaviv_field(specs[0], 199 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 202 gpu->identity.shader_core_count = etnaviv_field(specs[0], 203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 204 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 206 gpu->identity.vertex_output_buffer_size = 207 etnaviv_field(specs[0], 208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 209 210 gpu->identity.buffer_size = etnaviv_field(specs[1], 211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 212 gpu->identity.instruction_count = etnaviv_field(specs[1], 213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 214 gpu->identity.num_constants = etnaviv_field(specs[1], 215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 216 217 gpu->identity.varyings_count = etnaviv_field(specs[2], 218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 219 220 /* This overrides the value from older register if non-zero */ 221 streams = etnaviv_field(specs[3], 222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 223 if (streams) 224 gpu->identity.stream_count = streams; 225 } 226 227 /* Fill in the stream count if not specified */ 228 if (gpu->identity.stream_count == 0) { 229 if (gpu->identity.model >= 0x1000) 230 gpu->identity.stream_count = 4; 231 else 232 gpu->identity.stream_count = 1; 233 } 234 235 /* Convert the register max value */ 236 if (gpu->identity.register_max) 237 gpu->identity.register_max = 1 << gpu->identity.register_max; 238 else if (gpu->identity.model == chipModel_GC400) 239 gpu->identity.register_max = 32; 240 else 241 gpu->identity.register_max = 64; 242 243 /* Convert thread count */ 244 if (gpu->identity.thread_count) 245 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 246 else if (gpu->identity.model == chipModel_GC400) 247 gpu->identity.thread_count = 64; 248 else if (gpu->identity.model == chipModel_GC500 || 249 gpu->identity.model == chipModel_GC530) 250 gpu->identity.thread_count = 128; 251 else 252 gpu->identity.thread_count = 256; 253 254 if (gpu->identity.vertex_cache_size == 0) 255 gpu->identity.vertex_cache_size = 8; 256 257 if (gpu->identity.shader_core_count == 0) { 258 if (gpu->identity.model >= 0x1000) 259 gpu->identity.shader_core_count = 2; 260 else 261 gpu->identity.shader_core_count = 1; 262 } 263 264 if (gpu->identity.pixel_pipes == 0) 265 gpu->identity.pixel_pipes = 1; 266 267 /* Convert virtex buffer size */ 268 if (gpu->identity.vertex_output_buffer_size) { 269 gpu->identity.vertex_output_buffer_size = 270 1 << gpu->identity.vertex_output_buffer_size; 271 } else if (gpu->identity.model == chipModel_GC400) { 272 if (gpu->identity.revision < 0x4000) 273 gpu->identity.vertex_output_buffer_size = 512; 274 else if (gpu->identity.revision < 0x4200) 275 gpu->identity.vertex_output_buffer_size = 256; 276 else 277 gpu->identity.vertex_output_buffer_size = 128; 278 } else { 279 gpu->identity.vertex_output_buffer_size = 512; 280 } 281 282 switch (gpu->identity.instruction_count) { 283 case 0: 284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 285 gpu->identity.model == chipModel_GC880) 286 gpu->identity.instruction_count = 512; 287 else 288 gpu->identity.instruction_count = 256; 289 break; 290 291 case 1: 292 gpu->identity.instruction_count = 1024; 293 break; 294 295 case 2: 296 gpu->identity.instruction_count = 2048; 297 break; 298 299 default: 300 gpu->identity.instruction_count = 256; 301 break; 302 } 303 304 if (gpu->identity.num_constants == 0) 305 gpu->identity.num_constants = 168; 306 307 if (gpu->identity.varyings_count == 0) { 308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 309 gpu->identity.varyings_count = 12; 310 else 311 gpu->identity.varyings_count = 8; 312 } 313 314 /* 315 * For some cores, two varyings are consumed for position, so the 316 * maximum varying count needs to be reduced by one. 317 */ 318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 327 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 328 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 329 gpu->identity.varyings_count -= 1; 330} 331 332static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 333{ 334 u32 chipIdentity; 335 336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 337 338 /* Special case for older graphic cores. */ 339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 340 gpu->identity.model = chipModel_GC500; 341 gpu->identity.revision = etnaviv_field(chipIdentity, 342 VIVS_HI_CHIP_IDENTITY_REVISION); 343 } else { 344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 345 346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 349 350 /* 351 * Reading these two registers on GC600 rev 0x19 result in a 352 * unhandled fault: external abort on non-linefetch 353 */ 354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { 355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 357 } 358 359 /* 360 * !!!! HACK ALERT !!!! 361 * Because people change device IDs without letting software 362 * know about it - here is the hack to make it all look the 363 * same. Only for GC400 family. 364 */ 365 if ((gpu->identity.model & 0xff00) == 0x0400 && 366 gpu->identity.model != chipModel_GC420) { 367 gpu->identity.model = gpu->identity.model & 0x0400; 368 } 369 370 /* Another special case */ 371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 373 374 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 375 /* 376 * This IP has an ECO; put the correct 377 * revision in it. 378 */ 379 gpu->identity.revision = 0x1051; 380 } 381 } 382 383 /* 384 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 385 * reality it's just a re-branded GC3000. We can identify this 386 * core by the upper half of the revision register being all 1. 387 * Fix model/rev here, so all other places can refer to this 388 * core by its real identity. 389 */ 390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 391 gpu->identity.model = chipModel_GC3000; 392 gpu->identity.revision &= 0xffff; 393 } 394 395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) 396 gpu->identity.eco_id = 1; 397 398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) 399 gpu->identity.eco_id = 1; 400 } 401 402 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 403 gpu->identity.model, gpu->identity.revision); 404 405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 406 /* 407 * If there is a match in the HWDB, we aren't interested in the 408 * remaining register values, as they might be wrong. 409 */ 410 if (etnaviv_fill_identity_from_hwdb(gpu)) 411 return; 412 413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 414 415 /* Disable fast clear on GC700. */ 416 if (gpu->identity.model == chipModel_GC700) 417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 418 419 /* These models/revisions don't have the 2D pipe bit */ 420 if ((gpu->identity.model == chipModel_GC500 && 421 gpu->identity.revision <= 2) || 422 gpu->identity.model == chipModel_GC300) 423 gpu->identity.features |= chipFeatures_PIPE_2D; 424 425 if ((gpu->identity.model == chipModel_GC500 && 426 gpu->identity.revision < 2) || 427 (gpu->identity.model == chipModel_GC300 && 428 gpu->identity.revision < 0x2000)) { 429 430 /* 431 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 432 * registers. 433 */ 434 gpu->identity.minor_features0 = 0; 435 gpu->identity.minor_features1 = 0; 436 gpu->identity.minor_features2 = 0; 437 gpu->identity.minor_features3 = 0; 438 gpu->identity.minor_features4 = 0; 439 gpu->identity.minor_features5 = 0; 440 } else 441 gpu->identity.minor_features0 = 442 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 443 444 if (gpu->identity.minor_features0 & 445 chipMinorFeatures0_MORE_MINOR_FEATURES) { 446 gpu->identity.minor_features1 = 447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 448 gpu->identity.minor_features2 = 449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 450 gpu->identity.minor_features3 = 451 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 452 gpu->identity.minor_features4 = 453 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 454 gpu->identity.minor_features5 = 455 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 456 } 457 458 /* GC600/300 idle register reports zero bits where modules aren't present */ 459 if (gpu->identity.model == chipModel_GC600 || 460 gpu->identity.model == chipModel_GC300) 461 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 462 VIVS_HI_IDLE_STATE_RA | 463 VIVS_HI_IDLE_STATE_SE | 464 VIVS_HI_IDLE_STATE_PA | 465 VIVS_HI_IDLE_STATE_SH | 466 VIVS_HI_IDLE_STATE_PE | 467 VIVS_HI_IDLE_STATE_DE | 468 VIVS_HI_IDLE_STATE_FE; 469 470 etnaviv_hw_specs(gpu); 471} 472 473static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 474{ 475 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 476 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 478} 479 480static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 481{ 482 if (gpu->identity.minor_features2 & 483 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 484 clk_set_rate(gpu->clk_core, 485 gpu->base_rate_core >> gpu->freq_scale); 486 clk_set_rate(gpu->clk_shader, 487 gpu->base_rate_shader >> gpu->freq_scale); 488 } else { 489 unsigned int fscale = 1 << (6 - gpu->freq_scale); 490 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 491 492 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 493 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 494 etnaviv_gpu_load_clock(gpu, clock); 495 } 496 497 /* 498 * Choose number of wait cycles to target a ~30us (1/32768) max latency 499 * until new work is picked up by the FE when it polls in the idle loop. 500 * If the GPU base frequency is unknown use 200 wait cycles. 501 */ 502 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), 503 200UL, 0xffffUL); 504} 505 506static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 507{ 508 u32 control, idle; 509 unsigned long timeout; 510 bool failed = true; 511 512 /* We hope that the GPU resets in under one second */ 513 timeout = jiffies + msecs_to_jiffies(1000); 514 515 while (time_is_after_jiffies(timeout)) { 516 unsigned int fscale = 1 << (6 - gpu->freq_scale); 517 u32 pulse_eater = 0x01590880; 518 519 /* disable clock gating */ 520 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0); 521 522 /* disable pulse eater */ 523 pulse_eater |= BIT(17); 524 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 525 pulse_eater |= BIT(0); 526 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 527 528 /* enable clock */ 529 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 530 etnaviv_gpu_load_clock(gpu, control); 531 532 /* isolate the GPU. */ 533 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 534 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 535 536 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 537 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 538 VIVS_MMUv2_AHB_CONTROL_RESET); 539 } else { 540 /* set soft reset. */ 541 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 542 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 543 } 544 545 /* wait for reset. */ 546 usleep_range(10, 20); 547 548 /* reset soft reset bit. */ 549 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 550 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 551 552 /* reset GPU isolation. */ 553 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 554 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 555 556 /* read idle register. */ 557 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 558 559 /* try resetting again if FE is not idle */ 560 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 561 dev_dbg(gpu->dev, "FE is not idle\n"); 562 continue; 563 } 564 565 /* read reset register. */ 566 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 567 568 /* is the GPU idle? */ 569 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 570 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 571 dev_dbg(gpu->dev, "GPU is not idle\n"); 572 continue; 573 } 574 575 /* disable debug registers, as they are not normally needed */ 576 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 577 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 578 579 failed = false; 580 break; 581 } 582 583 if (failed) { 584 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 585 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 586 587 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 588 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 589 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 590 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 591 592 return -EBUSY; 593 } 594 595 /* We rely on the GPU running, so program the clock */ 596 etnaviv_gpu_update_clock(gpu); 597 598 gpu->state = ETNA_GPU_STATE_RESET; 599 gpu->exec_state = -1; 600 if (gpu->mmu_context) 601 etnaviv_iommu_context_put(gpu->mmu_context); 602 gpu->mmu_context = NULL; 603 604 return 0; 605} 606 607static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 608{ 609 u32 pmc, ppc; 610 611 /* enable clock gating */ 612 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 613 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 614 615 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 616 if (gpu->identity.revision == 0x4301 || 617 gpu->identity.revision == 0x4302) 618 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 619 620 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); 621 622 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); 623 624 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 625 if (gpu->identity.model >= chipModel_GC400 && 626 gpu->identity.model != chipModel_GC420 && 627 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 628 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 629 630 /* 631 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 632 * present without a bug fix. 633 */ 634 if (gpu->identity.revision < 0x5000 && 635 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 636 !(gpu->identity.minor_features1 & 637 chipMinorFeatures1_DISABLE_PE_GATING)) 638 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 639 640 if (gpu->identity.revision < 0x5422) 641 pmc |= BIT(15); /* Unknown bit */ 642 643 /* Disable TX clock gating on affected core revisions. */ 644 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 645 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 646 etnaviv_is_model_rev(gpu, GC7000, 0x6202) || 647 etnaviv_is_model_rev(gpu, GC7000, 0x6203)) 648 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 649 650 /* Disable SE and RA clock gating on affected core revisions. */ 651 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) 652 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 653 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; 654 655 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 656 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 657 658 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 659} 660 661void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 662{ 663 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 664 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 665 VIVS_FE_COMMAND_CONTROL_ENABLE | 666 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 667 668 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 669 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 670 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 671 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 672 } 673} 674 675static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, 676 struct etnaviv_iommu_context *context) 677{ 678 u16 prefetch; 679 u32 address; 680 681 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED); 682 683 /* setup the MMU */ 684 etnaviv_iommu_restore(gpu, context); 685 686 /* Start command processor */ 687 prefetch = etnaviv_buffer_init(gpu); 688 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 689 &gpu->mmu_context->cmdbuf_mapping); 690 691 etnaviv_gpu_start_fe(gpu, address, prefetch); 692 693 gpu->state = ETNA_GPU_STATE_RUNNING; 694} 695 696static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 697{ 698 /* 699 * Base value for VIVS_PM_PULSE_EATER register on models where it 700 * cannot be read, extracted from vivante kernel driver. 701 */ 702 u32 pulse_eater = 0x01590880; 703 704 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 705 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 706 pulse_eater |= BIT(23); 707 708 } 709 710 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 711 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 712 pulse_eater &= ~BIT(16); 713 pulse_eater |= BIT(17); 714 } 715 716 if ((gpu->identity.revision > 0x5420) && 717 (gpu->identity.features & chipFeatures_PIPE_3D)) 718 { 719 /* Performance fix: disable internal DFS */ 720 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); 721 pulse_eater |= BIT(18); 722 } 723 724 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 725} 726 727static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 728{ 729 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || 730 gpu->state == ETNA_GPU_STATE_RESET)); 731 732 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 733 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 734 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 735 u32 mc_memory_debug; 736 737 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 738 739 if (gpu->identity.revision == 0x5007) 740 mc_memory_debug |= 0x0c; 741 else 742 mc_memory_debug |= 0x08; 743 744 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 745 } 746 747 /* enable module-level clock gating */ 748 etnaviv_gpu_enable_mlcg(gpu); 749 750 /* 751 * Update GPU AXI cache atttribute to "cacheable, no allocate". 752 * This is necessary to prevent the iMX6 SoC locking up. 753 */ 754 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 755 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 756 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 757 758 /* GC2000 rev 5108 needs a special bus config */ 759 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 760 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 761 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 762 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 763 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 764 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 765 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 766 } 767 768 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 769 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 770 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 771 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 772 } 773 774 /* setup the pulse eater */ 775 etnaviv_gpu_setup_pulse_eater(gpu); 776 777 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 778 779 gpu->state = ETNA_GPU_STATE_INITIALIZED; 780} 781 782int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 783{ 784 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 785 dma_addr_t cmdbuf_paddr; 786 int ret, i; 787 788 ret = pm_runtime_get_sync(gpu->dev); 789 if (ret < 0) { 790 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 791 goto pm_put; 792 } 793 794 etnaviv_hw_identify(gpu); 795 796 if (gpu->identity.model == 0) { 797 dev_err(gpu->dev, "Unknown GPU model\n"); 798 ret = -ENXIO; 799 goto fail; 800 } 801 802 if (gpu->identity.nn_core_count > 0) 803 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " 804 "for which the UAPI is still experimental\n"); 805 806 /* Exclude VG cores with FE2.0 */ 807 if (gpu->identity.features & chipFeatures_PIPE_VG && 808 gpu->identity.features & chipFeatures_FE20) { 809 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 810 ret = -ENXIO; 811 goto fail; 812 } 813 814 /* 815 * On cores with security features supported, we claim control over the 816 * security states. 817 */ 818 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 819 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 820 gpu->sec_mode = ETNA_SEC_KERNEL; 821 822 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 823 824 ret = etnaviv_hw_reset(gpu); 825 if (ret) { 826 dev_err(gpu->dev, "GPU reset failed\n"); 827 goto fail; 828 } 829 830 ret = etnaviv_iommu_global_init(gpu); 831 if (ret) 832 goto fail; 833 834 /* 835 * If the GPU is part of a system with DMA addressing limitations, 836 * request pages for our SHM backend buffers from the DMA32 zone to 837 * hopefully avoid performance killing SWIOTLB bounce buffering. 838 */ 839 if (dma_addressing_limited(gpu->dev)) 840 priv->shm_gfp_mask |= GFP_DMA32; 841 842 /* Create buffer: */ 843 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 844 PAGE_SIZE); 845 if (ret) { 846 dev_err(gpu->dev, "could not create command buffer\n"); 847 goto fail; 848 } 849 850 /* 851 * Set the GPU linear window to cover the cmdbuf region, as the GPU 852 * won't be able to start execution otherwise. The alignment to 128M is 853 * chosen arbitrarily but helps in debugging, as the MMU offset 854 * calculations are much more straight forward this way. 855 * 856 * On MC1.0 cores the linear window offset is ignored by the TS engine, 857 * leading to inconsistent memory views. Avoid using the offset on those 858 * cores if possible, otherwise disable the TS feature. 859 */ 860 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 861 862 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 863 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 864 if (cmdbuf_paddr >= SZ_2G) 865 priv->mmu_global->memory_base = SZ_2G; 866 else 867 priv->mmu_global->memory_base = cmdbuf_paddr; 868 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 869 dev_info(gpu->dev, 870 "Need to move linear window on MC1.0, disabling TS\n"); 871 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 872 priv->mmu_global->memory_base = SZ_2G; 873 } 874 875 /* Setup event management */ 876 spin_lock_init(&gpu->event_spinlock); 877 init_completion(&gpu->event_free); 878 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 879 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 880 complete(&gpu->event_free); 881 882 /* Now program the hardware */ 883 mutex_lock(&gpu->lock); 884 etnaviv_gpu_hw_init(gpu); 885 mutex_unlock(&gpu->lock); 886 887 pm_runtime_mark_last_busy(gpu->dev); 888 pm_runtime_put_autosuspend(gpu->dev); 889 890 return 0; 891 892fail: 893 pm_runtime_mark_last_busy(gpu->dev); 894pm_put: 895 pm_runtime_put_autosuspend(gpu->dev); 896 897 return ret; 898} 899 900#ifdef CONFIG_DEBUG_FS 901struct dma_debug { 902 u32 address[2]; 903 u32 state[2]; 904}; 905 906static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 907{ 908 u32 i; 909 910 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 911 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 912 913 for (i = 0; i < 500; i++) { 914 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 915 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 916 917 if (debug->address[0] != debug->address[1]) 918 break; 919 920 if (debug->state[0] != debug->state[1]) 921 break; 922 } 923} 924 925int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 926{ 927 struct dma_debug debug; 928 u32 dma_lo, dma_hi, axi, idle; 929 int ret; 930 931 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 932 933 ret = pm_runtime_get_sync(gpu->dev); 934 if (ret < 0) 935 goto pm_put; 936 937 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 938 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 939 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 940 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 941 942 verify_dma(gpu, &debug); 943 944 seq_puts(m, "\tidentity\n"); 945 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 946 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 947 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 948 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 949 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 950 951 seq_puts(m, "\tfeatures\n"); 952 seq_printf(m, "\t major_features: 0x%08x\n", 953 gpu->identity.features); 954 seq_printf(m, "\t minor_features0: 0x%08x\n", 955 gpu->identity.minor_features0); 956 seq_printf(m, "\t minor_features1: 0x%08x\n", 957 gpu->identity.minor_features1); 958 seq_printf(m, "\t minor_features2: 0x%08x\n", 959 gpu->identity.minor_features2); 960 seq_printf(m, "\t minor_features3: 0x%08x\n", 961 gpu->identity.minor_features3); 962 seq_printf(m, "\t minor_features4: 0x%08x\n", 963 gpu->identity.minor_features4); 964 seq_printf(m, "\t minor_features5: 0x%08x\n", 965 gpu->identity.minor_features5); 966 seq_printf(m, "\t minor_features6: 0x%08x\n", 967 gpu->identity.minor_features6); 968 seq_printf(m, "\t minor_features7: 0x%08x\n", 969 gpu->identity.minor_features7); 970 seq_printf(m, "\t minor_features8: 0x%08x\n", 971 gpu->identity.minor_features8); 972 seq_printf(m, "\t minor_features9: 0x%08x\n", 973 gpu->identity.minor_features9); 974 seq_printf(m, "\t minor_features10: 0x%08x\n", 975 gpu->identity.minor_features10); 976 seq_printf(m, "\t minor_features11: 0x%08x\n", 977 gpu->identity.minor_features11); 978 979 seq_puts(m, "\tspecs\n"); 980 seq_printf(m, "\t stream_count: %d\n", 981 gpu->identity.stream_count); 982 seq_printf(m, "\t register_max: %d\n", 983 gpu->identity.register_max); 984 seq_printf(m, "\t thread_count: %d\n", 985 gpu->identity.thread_count); 986 seq_printf(m, "\t vertex_cache_size: %d\n", 987 gpu->identity.vertex_cache_size); 988 seq_printf(m, "\t shader_core_count: %d\n", 989 gpu->identity.shader_core_count); 990 seq_printf(m, "\t nn_core_count: %d\n", 991 gpu->identity.nn_core_count); 992 seq_printf(m, "\t pixel_pipes: %d\n", 993 gpu->identity.pixel_pipes); 994 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 995 gpu->identity.vertex_output_buffer_size); 996 seq_printf(m, "\t buffer_size: %d\n", 997 gpu->identity.buffer_size); 998 seq_printf(m, "\t instruction_count: %d\n", 999 gpu->identity.instruction_count); 1000 seq_printf(m, "\t num_constants: %d\n", 1001 gpu->identity.num_constants); 1002 seq_printf(m, "\t varyings_count: %d\n", 1003 gpu->identity.varyings_count); 1004 1005 seq_printf(m, "\taxi: 0x%08x\n", axi); 1006 seq_printf(m, "\tidle: 0x%08x\n", idle); 1007 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 1008 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 1009 seq_puts(m, "\t FE is not idle\n"); 1010 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 1011 seq_puts(m, "\t DE is not idle\n"); 1012 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 1013 seq_puts(m, "\t PE is not idle\n"); 1014 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 1015 seq_puts(m, "\t SH is not idle\n"); 1016 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 1017 seq_puts(m, "\t PA is not idle\n"); 1018 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 1019 seq_puts(m, "\t SE is not idle\n"); 1020 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 1021 seq_puts(m, "\t RA is not idle\n"); 1022 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 1023 seq_puts(m, "\t TX is not idle\n"); 1024 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 1025 seq_puts(m, "\t VG is not idle\n"); 1026 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 1027 seq_puts(m, "\t IM is not idle\n"); 1028 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 1029 seq_puts(m, "\t FP is not idle\n"); 1030 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 1031 seq_puts(m, "\t TS is not idle\n"); 1032 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 1033 seq_puts(m, "\t BL is not idle\n"); 1034 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 1035 seq_puts(m, "\t ASYNCFE is not idle\n"); 1036 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 1037 seq_puts(m, "\t MC is not idle\n"); 1038 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 1039 seq_puts(m, "\t PPA is not idle\n"); 1040 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 1041 seq_puts(m, "\t WD is not idle\n"); 1042 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 1043 seq_puts(m, "\t NN is not idle\n"); 1044 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 1045 seq_puts(m, "\t TP is not idle\n"); 1046 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 1047 seq_puts(m, "\t AXI low power mode\n"); 1048 1049 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1050 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1051 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1052 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1053 1054 seq_puts(m, "\tMC\n"); 1055 seq_printf(m, "\t read0: 0x%08x\n", read0); 1056 seq_printf(m, "\t read1: 0x%08x\n", read1); 1057 seq_printf(m, "\t write: 0x%08x\n", write); 1058 } 1059 1060 seq_puts(m, "\tDMA "); 1061 1062 if (debug.address[0] == debug.address[1] && 1063 debug.state[0] == debug.state[1]) { 1064 seq_puts(m, "seems to be stuck\n"); 1065 } else if (debug.address[0] == debug.address[1]) { 1066 seq_puts(m, "address is constant\n"); 1067 } else { 1068 seq_puts(m, "is running\n"); 1069 } 1070 1071 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1072 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1073 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1074 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1075 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1076 dma_lo, dma_hi); 1077 1078 ret = 0; 1079 1080 pm_runtime_mark_last_busy(gpu->dev); 1081pm_put: 1082 pm_runtime_put_autosuspend(gpu->dev); 1083 1084 return ret; 1085} 1086#endif 1087 1088/* fence object management */ 1089struct etnaviv_fence { 1090 struct etnaviv_gpu *gpu; 1091 struct dma_fence base; 1092}; 1093 1094static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1095{ 1096 return container_of(fence, struct etnaviv_fence, base); 1097} 1098 1099static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1100{ 1101 return "etnaviv"; 1102} 1103 1104static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1105{ 1106 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1107 1108 return dev_name(f->gpu->dev); 1109} 1110 1111static bool etnaviv_fence_signaled(struct dma_fence *fence) 1112{ 1113 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1114 1115 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1116} 1117 1118static void etnaviv_fence_release(struct dma_fence *fence) 1119{ 1120 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1121 1122 kfree_rcu(f, base.rcu); 1123} 1124 1125static const struct dma_fence_ops etnaviv_fence_ops = { 1126 .get_driver_name = etnaviv_fence_get_driver_name, 1127 .get_timeline_name = etnaviv_fence_get_timeline_name, 1128 .signaled = etnaviv_fence_signaled, 1129 .release = etnaviv_fence_release, 1130}; 1131 1132static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1133{ 1134 struct etnaviv_fence *f; 1135 1136 /* 1137 * GPU lock must already be held, otherwise fence completion order might 1138 * not match the seqno order assigned here. 1139 */ 1140 lockdep_assert_held(&gpu->lock); 1141 1142 f = kzalloc(sizeof(*f), GFP_KERNEL); 1143 if (!f) 1144 return NULL; 1145 1146 f->gpu = gpu; 1147 1148 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1149 gpu->fence_context, ++gpu->next_fence); 1150 1151 return &f->base; 1152} 1153 1154/* returns true if fence a comes after fence b */ 1155static inline bool fence_after(u32 a, u32 b) 1156{ 1157 return (s32)(a - b) > 0; 1158} 1159 1160/* 1161 * event management: 1162 */ 1163 1164static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1165 unsigned int *events) 1166{ 1167 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1168 unsigned i, acquired = 0, rpm_count = 0; 1169 int ret; 1170 1171 for (i = 0; i < nr_events; i++) { 1172 unsigned long remaining; 1173 1174 remaining = wait_for_completion_timeout(&gpu->event_free, timeout); 1175 1176 if (!remaining) { 1177 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1178 ret = -EBUSY; 1179 goto out; 1180 } 1181 1182 acquired++; 1183 timeout = remaining; 1184 } 1185 1186 spin_lock(&gpu->event_spinlock); 1187 1188 for (i = 0; i < nr_events; i++) { 1189 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1190 1191 events[i] = event; 1192 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1193 set_bit(event, gpu->event_bitmap); 1194 } 1195 1196 spin_unlock(&gpu->event_spinlock); 1197 1198 for (i = 0; i < nr_events; i++) { 1199 ret = pm_runtime_resume_and_get(gpu->dev); 1200 if (ret) 1201 goto out_rpm; 1202 rpm_count++; 1203 } 1204 1205 return 0; 1206 1207out_rpm: 1208 for (i = 0; i < rpm_count; i++) 1209 pm_runtime_put_autosuspend(gpu->dev); 1210out: 1211 for (i = 0; i < acquired; i++) 1212 complete(&gpu->event_free); 1213 1214 return ret; 1215} 1216 1217static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1218{ 1219 if (!test_bit(event, gpu->event_bitmap)) { 1220 dev_warn(gpu->dev, "event %u is already marked as free", 1221 event); 1222 } else { 1223 clear_bit(event, gpu->event_bitmap); 1224 complete(&gpu->event_free); 1225 } 1226 1227 pm_runtime_put_autosuspend(gpu->dev); 1228} 1229 1230/* 1231 * Cmdstream submission/retirement: 1232 */ 1233int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1234 u32 id, struct drm_etnaviv_timespec *timeout) 1235{ 1236 struct dma_fence *fence; 1237 int ret; 1238 1239 /* 1240 * Look up the fence and take a reference. We might still find a fence 1241 * whose refcount has already dropped to zero. dma_fence_get_rcu 1242 * pretends we didn't find a fence in that case. 1243 */ 1244 rcu_read_lock(); 1245 fence = xa_load(&gpu->user_fences, id); 1246 if (fence) 1247 fence = dma_fence_get_rcu(fence); 1248 rcu_read_unlock(); 1249 1250 if (!fence) 1251 return 0; 1252 1253 if (!timeout) { 1254 /* No timeout was requested: just test for completion */ 1255 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1256 } else { 1257 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1258 1259 ret = dma_fence_wait_timeout(fence, true, remaining); 1260 if (ret == 0) 1261 ret = -ETIMEDOUT; 1262 else if (ret != -ERESTARTSYS) 1263 ret = 0; 1264 1265 } 1266 1267 dma_fence_put(fence); 1268 return ret; 1269} 1270 1271/* 1272 * Wait for an object to become inactive. This, on it's own, is not race 1273 * free: the object is moved by the scheduler off the active list, and 1274 * then the iova is put. Moreover, the object could be re-submitted just 1275 * after we notice that it's become inactive. 1276 * 1277 * Although the retirement happens under the gpu lock, we don't want to hold 1278 * that lock in this function while waiting. 1279 */ 1280int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1281 struct etnaviv_gem_object *etnaviv_obj, 1282 struct drm_etnaviv_timespec *timeout) 1283{ 1284 unsigned long remaining; 1285 long ret; 1286 1287 if (!timeout) 1288 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1289 1290 remaining = etnaviv_timeout_to_jiffies(timeout); 1291 1292 ret = wait_event_interruptible_timeout(gpu->fence_event, 1293 !is_active(etnaviv_obj), 1294 remaining); 1295 if (ret > 0) 1296 return 0; 1297 else if (ret == -ERESTARTSYS) 1298 return -ERESTARTSYS; 1299 else 1300 return -ETIMEDOUT; 1301} 1302 1303static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1304 struct etnaviv_event *event, unsigned int flags) 1305{ 1306 const struct etnaviv_gem_submit *submit = event->submit; 1307 unsigned int i; 1308 1309 for (i = 0; i < submit->nr_pmrs; i++) { 1310 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1311 1312 if (pmr->flags == flags) 1313 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1314 } 1315} 1316 1317static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1318 struct etnaviv_event *event) 1319{ 1320 u32 val; 1321 1322 /* disable clock gating */ 1323 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1324 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1325 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1326 1327 /* enable debug register */ 1328 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1329 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1330 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1331 1332 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1333} 1334 1335static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1336 struct etnaviv_event *event) 1337{ 1338 const struct etnaviv_gem_submit *submit = event->submit; 1339 unsigned int i; 1340 u32 val; 1341 1342 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1343 1344 for (i = 0; i < submit->nr_pmrs; i++) { 1345 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1346 1347 *pmr->bo_vma = pmr->sequence; 1348 } 1349 1350 /* disable debug register */ 1351 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1352 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1353 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1354 1355 /* enable clock gating */ 1356 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1357 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1358 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1359} 1360 1361 1362/* add bo's to gpu's ring, and kick gpu: */ 1363struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1364{ 1365 struct etnaviv_gpu *gpu = submit->gpu; 1366 struct dma_fence *gpu_fence; 1367 unsigned int i, nr_events = 1, event[3]; 1368 int ret; 1369 1370 /* 1371 * if there are performance monitor requests we need to have 1372 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1373 * requests. 1374 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1375 * and update the sequence number for userspace. 1376 */ 1377 if (submit->nr_pmrs) 1378 nr_events = 3; 1379 1380 ret = event_alloc(gpu, nr_events, event); 1381 if (ret) { 1382 DRM_ERROR("no free events\n"); 1383 pm_runtime_put_noidle(gpu->dev); 1384 return NULL; 1385 } 1386 1387 mutex_lock(&gpu->lock); 1388 1389 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1390 if (!gpu_fence) { 1391 for (i = 0; i < nr_events; i++) 1392 event_free(gpu, event[i]); 1393 1394 goto out_unlock; 1395 } 1396 1397 if (gpu->state == ETNA_GPU_STATE_INITIALIZED) 1398 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); 1399 1400 if (submit->prev_mmu_context) 1401 etnaviv_iommu_context_put(submit->prev_mmu_context); 1402 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); 1403 1404 if (submit->nr_pmrs) { 1405 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1406 kref_get(&submit->refcount); 1407 gpu->event[event[1]].submit = submit; 1408 etnaviv_sync_point_queue(gpu, event[1]); 1409 } 1410 1411 gpu->event[event[0]].fence = gpu_fence; 1412 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1413 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1414 event[0], &submit->cmdbuf); 1415 1416 if (submit->nr_pmrs) { 1417 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1418 kref_get(&submit->refcount); 1419 gpu->event[event[2]].submit = submit; 1420 etnaviv_sync_point_queue(gpu, event[2]); 1421 } 1422 1423out_unlock: 1424 mutex_unlock(&gpu->lock); 1425 1426 return gpu_fence; 1427} 1428 1429static void sync_point_worker(struct work_struct *work) 1430{ 1431 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1432 sync_point_work); 1433 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1434 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1435 1436 event->sync_point(gpu, event); 1437 etnaviv_submit_put(event->submit); 1438 event_free(gpu, gpu->sync_point_event); 1439 1440 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1441 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1442} 1443 1444void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit) 1445{ 1446 struct etnaviv_gpu *gpu = submit->gpu; 1447 char *comm = NULL, *cmd = NULL; 1448 struct task_struct *task; 1449 unsigned int i; 1450 1451 dev_err(gpu->dev, "recover hung GPU!\n"); 1452 1453 task = get_pid_task(submit->pid, PIDTYPE_PID); 1454 if (task) { 1455 comm = kstrdup(task->comm, GFP_KERNEL); 1456 cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 1457 put_task_struct(task); 1458 } 1459 1460 if (comm && cmd) 1461 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); 1462 1463 kfree(cmd); 1464 kfree(comm); 1465 1466 if (pm_runtime_get_sync(gpu->dev) < 0) 1467 goto pm_put; 1468 1469 mutex_lock(&gpu->lock); 1470 1471 etnaviv_hw_reset(gpu); 1472 1473 /* complete all events, the GPU won't do it after the reset */ 1474 spin_lock(&gpu->event_spinlock); 1475 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1476 event_free(gpu, i); 1477 spin_unlock(&gpu->event_spinlock); 1478 1479 etnaviv_gpu_hw_init(gpu); 1480 1481 mutex_unlock(&gpu->lock); 1482 pm_runtime_mark_last_busy(gpu->dev); 1483pm_put: 1484 pm_runtime_put_autosuspend(gpu->dev); 1485} 1486 1487static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1488{ 1489 static const char *fault_reasons[] = { 1490 "slave not present", 1491 "page not present", 1492 "write violation", 1493 "out of bounds", 1494 "read security violation", 1495 "write security violation", 1496 }; 1497 1498 u32 status_reg, status; 1499 int i; 1500 1501 if (gpu->sec_mode == ETNA_SEC_NONE) 1502 status_reg = VIVS_MMUv2_STATUS; 1503 else 1504 status_reg = VIVS_MMUv2_SEC_STATUS; 1505 1506 status = gpu_read(gpu, status_reg); 1507 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1508 1509 for (i = 0; i < 4; i++) { 1510 const char *reason = "unknown"; 1511 u32 address_reg; 1512 u32 mmu_status; 1513 1514 mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK; 1515 if (!mmu_status) 1516 continue; 1517 1518 if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons)) 1519 reason = fault_reasons[mmu_status - 1]; 1520 1521 if (gpu->sec_mode == ETNA_SEC_NONE) 1522 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1523 else 1524 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1525 1526 dev_err_ratelimited(gpu->dev, 1527 "MMU %d fault (%s) addr 0x%08x\n", 1528 i, reason, gpu_read(gpu, address_reg)); 1529 } 1530} 1531 1532static irqreturn_t irq_handler(int irq, void *data) 1533{ 1534 struct etnaviv_gpu *gpu = data; 1535 irqreturn_t ret = IRQ_NONE; 1536 1537 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1538 1539 if (intr != 0) { 1540 int event; 1541 1542 pm_runtime_mark_last_busy(gpu->dev); 1543 1544 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1545 1546 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1547 dev_err(gpu->dev, "AXI bus error\n"); 1548 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1549 } 1550 1551 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1552 dump_mmu_fault(gpu); 1553 gpu->state = ETNA_GPU_STATE_FAULT; 1554 drm_sched_fault(&gpu->sched); 1555 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1556 } 1557 1558 while ((event = ffs(intr)) != 0) { 1559 struct dma_fence *fence; 1560 1561 event -= 1; 1562 1563 intr &= ~(1 << event); 1564 1565 dev_dbg(gpu->dev, "event %u\n", event); 1566 1567 if (gpu->event[event].sync_point) { 1568 gpu->sync_point_event = event; 1569 queue_work(gpu->wq, &gpu->sync_point_work); 1570 } 1571 1572 fence = gpu->event[event].fence; 1573 if (!fence) 1574 continue; 1575 1576 gpu->event[event].fence = NULL; 1577 1578 /* 1579 * Events can be processed out of order. Eg, 1580 * - allocate and queue event 0 1581 * - allocate event 1 1582 * - event 0 completes, we process it 1583 * - allocate and queue event 0 1584 * - event 1 and event 0 complete 1585 * we can end up processing event 0 first, then 1. 1586 */ 1587 if (fence_after(fence->seqno, gpu->completed_fence)) 1588 gpu->completed_fence = fence->seqno; 1589 dma_fence_signal(fence); 1590 1591 event_free(gpu, event); 1592 } 1593 1594 ret = IRQ_HANDLED; 1595 } 1596 1597 return ret; 1598} 1599 1600static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1601{ 1602 int ret; 1603 1604 ret = clk_prepare_enable(gpu->clk_reg); 1605 if (ret) 1606 return ret; 1607 1608 ret = clk_prepare_enable(gpu->clk_bus); 1609 if (ret) 1610 goto disable_clk_reg; 1611 1612 ret = clk_prepare_enable(gpu->clk_core); 1613 if (ret) 1614 goto disable_clk_bus; 1615 1616 ret = clk_prepare_enable(gpu->clk_shader); 1617 if (ret) 1618 goto disable_clk_core; 1619 1620 return 0; 1621 1622disable_clk_core: 1623 clk_disable_unprepare(gpu->clk_core); 1624disable_clk_bus: 1625 clk_disable_unprepare(gpu->clk_bus); 1626disable_clk_reg: 1627 clk_disable_unprepare(gpu->clk_reg); 1628 1629 return ret; 1630} 1631 1632static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1633{ 1634 clk_disable_unprepare(gpu->clk_shader); 1635 clk_disable_unprepare(gpu->clk_core); 1636 clk_disable_unprepare(gpu->clk_bus); 1637 clk_disable_unprepare(gpu->clk_reg); 1638 1639 return 0; 1640} 1641 1642int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1643{ 1644 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1645 1646 do { 1647 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1648 1649 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1650 return 0; 1651 1652 if (time_is_before_jiffies(timeout)) { 1653 dev_warn(gpu->dev, 1654 "timed out waiting for idle: idle=0x%x\n", 1655 idle); 1656 return -ETIMEDOUT; 1657 } 1658 1659 udelay(5); 1660 } while (1); 1661} 1662 1663static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1664{ 1665 if (gpu->state == ETNA_GPU_STATE_RUNNING) { 1666 /* Replace the last WAIT with END */ 1667 mutex_lock(&gpu->lock); 1668 etnaviv_buffer_end(gpu); 1669 mutex_unlock(&gpu->lock); 1670 1671 /* 1672 * We know that only the FE is busy here, this should 1673 * happen quickly (as the WAIT is only 200 cycles). If 1674 * we fail, just warn and continue. 1675 */ 1676 etnaviv_gpu_wait_idle(gpu, 100); 1677 1678 gpu->state = ETNA_GPU_STATE_INITIALIZED; 1679 } 1680 1681 gpu->exec_state = -1; 1682} 1683 1684static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1685{ 1686 int ret; 1687 1688 ret = mutex_lock_killable(&gpu->lock); 1689 if (ret) 1690 return ret; 1691 1692 etnaviv_gpu_update_clock(gpu); 1693 etnaviv_gpu_hw_init(gpu); 1694 1695 mutex_unlock(&gpu->lock); 1696 1697 return 0; 1698} 1699 1700static int 1701etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1702 unsigned long *state) 1703{ 1704 *state = 6; 1705 1706 return 0; 1707} 1708 1709static int 1710etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1711 unsigned long *state) 1712{ 1713 struct etnaviv_gpu *gpu = cdev->devdata; 1714 1715 *state = gpu->freq_scale; 1716 1717 return 0; 1718} 1719 1720static int 1721etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1722 unsigned long state) 1723{ 1724 struct etnaviv_gpu *gpu = cdev->devdata; 1725 1726 mutex_lock(&gpu->lock); 1727 gpu->freq_scale = state; 1728 if (!pm_runtime_suspended(gpu->dev)) 1729 etnaviv_gpu_update_clock(gpu); 1730 mutex_unlock(&gpu->lock); 1731 1732 return 0; 1733} 1734 1735static const struct thermal_cooling_device_ops cooling_ops = { 1736 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1737 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1738 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1739}; 1740 1741static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1742 void *data) 1743{ 1744 struct drm_device *drm = data; 1745 struct etnaviv_drm_private *priv = drm->dev_private; 1746 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1747 int ret; 1748 1749 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1750 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1751 (char *)dev_name(dev), gpu, &cooling_ops); 1752 if (IS_ERR(gpu->cooling)) 1753 return PTR_ERR(gpu->cooling); 1754 } 1755 1756 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1757 if (!gpu->wq) { 1758 ret = -ENOMEM; 1759 goto out_thermal; 1760 } 1761 1762 ret = etnaviv_sched_init(gpu); 1763 if (ret) 1764 goto out_workqueue; 1765 1766 if (!IS_ENABLED(CONFIG_PM)) { 1767 ret = etnaviv_gpu_clk_enable(gpu); 1768 if (ret < 0) 1769 goto out_sched; 1770 } 1771 1772 gpu->drm = drm; 1773 gpu->fence_context = dma_fence_context_alloc(1); 1774 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); 1775 spin_lock_init(&gpu->fence_spinlock); 1776 1777 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1778 init_waitqueue_head(&gpu->fence_event); 1779 1780 priv->gpu[priv->num_gpus++] = gpu; 1781 1782 return 0; 1783 1784out_sched: 1785 etnaviv_sched_fini(gpu); 1786 1787out_workqueue: 1788 destroy_workqueue(gpu->wq); 1789 1790out_thermal: 1791 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1792 thermal_cooling_device_unregister(gpu->cooling); 1793 1794 return ret; 1795} 1796 1797static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1798 void *data) 1799{ 1800 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1801 1802 DBG("%s", dev_name(gpu->dev)); 1803 1804 destroy_workqueue(gpu->wq); 1805 1806 etnaviv_sched_fini(gpu); 1807 1808 if (IS_ENABLED(CONFIG_PM)) { 1809 pm_runtime_get_sync(gpu->dev); 1810 pm_runtime_put_sync_suspend(gpu->dev); 1811 } else { 1812 etnaviv_gpu_hw_suspend(gpu); 1813 etnaviv_gpu_clk_disable(gpu); 1814 } 1815 1816 if (gpu->mmu_context) 1817 etnaviv_iommu_context_put(gpu->mmu_context); 1818 1819 etnaviv_cmdbuf_free(&gpu->buffer); 1820 etnaviv_iommu_global_fini(gpu); 1821 1822 gpu->drm = NULL; 1823 xa_destroy(&gpu->user_fences); 1824 1825 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1826 thermal_cooling_device_unregister(gpu->cooling); 1827 gpu->cooling = NULL; 1828} 1829 1830static const struct component_ops gpu_ops = { 1831 .bind = etnaviv_gpu_bind, 1832 .unbind = etnaviv_gpu_unbind, 1833}; 1834 1835static const struct of_device_id etnaviv_gpu_match[] = { 1836 { 1837 .compatible = "vivante,gc" 1838 }, 1839 { /* sentinel */ } 1840}; 1841MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1842 1843static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1844{ 1845 struct device *dev = &pdev->dev; 1846 struct etnaviv_gpu *gpu; 1847 int err; 1848 1849 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1850 if (!gpu) 1851 return -ENOMEM; 1852 1853 gpu->dev = &pdev->dev; 1854 mutex_init(&gpu->lock); 1855 mutex_init(&gpu->sched_lock); 1856 1857 /* Map registers: */ 1858 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1859 if (IS_ERR(gpu->mmio)) 1860 return PTR_ERR(gpu->mmio); 1861 1862 /* Get Interrupt: */ 1863 gpu->irq = platform_get_irq(pdev, 0); 1864 if (gpu->irq < 0) 1865 return gpu->irq; 1866 1867 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1868 dev_name(gpu->dev), gpu); 1869 if (err) { 1870 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1871 return err; 1872 } 1873 1874 /* Get Clocks: */ 1875 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1876 DBG("clk_reg: %p", gpu->clk_reg); 1877 if (IS_ERR(gpu->clk_reg)) 1878 return PTR_ERR(gpu->clk_reg); 1879 1880 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1881 DBG("clk_bus: %p", gpu->clk_bus); 1882 if (IS_ERR(gpu->clk_bus)) 1883 return PTR_ERR(gpu->clk_bus); 1884 1885 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1886 DBG("clk_core: %p", gpu->clk_core); 1887 if (IS_ERR(gpu->clk_core)) 1888 return PTR_ERR(gpu->clk_core); 1889 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1890 1891 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1892 DBG("clk_shader: %p", gpu->clk_shader); 1893 if (IS_ERR(gpu->clk_shader)) 1894 return PTR_ERR(gpu->clk_shader); 1895 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1896 1897 /* TODO: figure out max mapped size */ 1898 dev_set_drvdata(dev, gpu); 1899 1900 /* 1901 * We treat the device as initially suspended. The runtime PM 1902 * autosuspend delay is rather arbitary: no measurements have 1903 * yet been performed to determine an appropriate value. 1904 */ 1905 pm_runtime_use_autosuspend(gpu->dev); 1906 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1907 pm_runtime_enable(gpu->dev); 1908 1909 err = component_add(&pdev->dev, &gpu_ops); 1910 if (err < 0) { 1911 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1912 return err; 1913 } 1914 1915 return 0; 1916} 1917 1918static void etnaviv_gpu_platform_remove(struct platform_device *pdev) 1919{ 1920 component_del(&pdev->dev, &gpu_ops); 1921 pm_runtime_disable(&pdev->dev); 1922} 1923 1924static int etnaviv_gpu_rpm_suspend(struct device *dev) 1925{ 1926 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1927 u32 idle, mask; 1928 1929 /* If there are any jobs in the HW queue, we're not idle */ 1930 if (atomic_read(&gpu->sched.credit_count)) 1931 return -EBUSY; 1932 1933 /* Check whether the hardware (except FE and MC) is idle */ 1934 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 1935 VIVS_HI_IDLE_STATE_MC); 1936 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1937 if (idle != mask) { 1938 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 1939 idle); 1940 return -EBUSY; 1941 } 1942 1943 etnaviv_gpu_hw_suspend(gpu); 1944 1945 gpu->state = ETNA_GPU_STATE_IDENTIFIED; 1946 1947 return etnaviv_gpu_clk_disable(gpu); 1948} 1949 1950static int etnaviv_gpu_rpm_resume(struct device *dev) 1951{ 1952 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1953 int ret; 1954 1955 ret = etnaviv_gpu_clk_enable(gpu); 1956 if (ret) 1957 return ret; 1958 1959 /* Re-initialise the basic hardware state */ 1960 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) { 1961 ret = etnaviv_gpu_hw_resume(gpu); 1962 if (ret) { 1963 etnaviv_gpu_clk_disable(gpu); 1964 return ret; 1965 } 1966 } 1967 1968 return 0; 1969} 1970 1971static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1972 RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL) 1973}; 1974 1975struct platform_driver etnaviv_gpu_driver = { 1976 .driver = { 1977 .name = "etnaviv-gpu", 1978 .owner = THIS_MODULE, 1979 .pm = pm_ptr(&etnaviv_gpu_pm_ops), 1980 .of_match_table = etnaviv_gpu_match, 1981 }, 1982 .probe = etnaviv_gpu_platform_probe, 1983 .remove_new = etnaviv_gpu_platform_remove, 1984 .id_table = gpu_ids, 1985}; 1986